source: mainline/uspace/drv/pciintel/pci.c@ b8e9acb

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b8e9acb was 91579d5, checked in by Vojtech Horky <vojtechhorky@…>, 14 years ago

C style fixes
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File size: 17.4 KB
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1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <devman.h>
51#include <ipc/devman.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ipc/ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <libarch/ddi.h>
61#include <pci_dev_iface.h>
62
63#include "pci.h"
64
65#define NAME "pciintel"
66
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
72
73/** Obtain PCI bus soft-state from DDF device node */
74#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
75
76/** Obtain PCI bus soft-state from function soft-state */
77#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
78
79static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
80{
81 pci_fun_t *fun = PCI_FUN(fnode);
82
83 if (fun == NULL)
84 return NULL;
85 return &fun->hw_resources;
86}
87
88static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
89{
90 /* This is an old ugly way, copied from ne2000 driver */
91 assert(fnode);
92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data;
93
94 sysarg_t apic;
95 sysarg_t i8259;
96
97 int irc_phone = -1;
98 int irc_service = -1;
99
100 if ((sysinfo_get_value("apic", &apic) == EOK) && (apic)) {
101 irc_service = SERVICE_APIC;
102 } else if ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259)) {
103 irc_service = SERVICE_I8259;
104 }
105
106 if (irc_service == -1) {
107 return false;
108 }
109
110 irc_phone = service_connect_blocking(irc_service, 0, 0);
111 if (irc_phone < 0) {
112 return false;
113 }
114
115 size_t i;
116 for (i = 0; i < dev_data->hw_resources.count; i++) {
117 if (dev_data->hw_resources.resources[i].type == INTERRUPT) {
118 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq;
119 int rc = async_req_1_0(irc_phone, IRC_ENABLE_INTERRUPT, irq);
120 if (rc != EOK) {
121 async_hangup(irc_phone);
122 return false;
123 }
124 }
125 }
126
127 async_hangup(irc_phone);
128 return true;
129}
130
131static int pci_config_space_write_32(
132 ddf_fun_t *fun, uint32_t address, uint32_t data)
133{
134 if (address > 252)
135 return EINVAL;
136 pci_conf_write_32(PCI_FUN(fun), address, data);
137 return EOK;
138}
139
140static int pci_config_space_write_16(
141 ddf_fun_t *fun, uint32_t address, uint16_t data)
142{
143 if (address > 254)
144 return EINVAL;
145 pci_conf_write_16(PCI_FUN(fun), address, data);
146 return EOK;
147}
148
149static int pci_config_space_write_8(
150 ddf_fun_t *fun, uint32_t address, uint8_t data)
151{
152 if (address > 255)
153 return EINVAL;
154 pci_conf_write_8(PCI_FUN(fun), address, data);
155 return EOK;
156}
157
158static int pci_config_space_read_32(
159 ddf_fun_t *fun, uint32_t address, uint32_t *data)
160{
161 if (address > 252)
162 return EINVAL;
163 *data = pci_conf_read_32(PCI_FUN(fun), address);
164 return EOK;
165}
166
167static int pci_config_space_read_16(
168 ddf_fun_t *fun, uint32_t address, uint16_t *data)
169{
170 if (address > 254)
171 return EINVAL;
172 *data = pci_conf_read_16(PCI_FUN(fun), address);
173 return EOK;
174}
175
176static int pci_config_space_read_8(
177 ddf_fun_t *fun, uint32_t address, uint8_t *data)
178{
179 if (address > 255)
180 return EINVAL;
181 *data = pci_conf_read_8(PCI_FUN(fun), address);
182 return EOK;
183}
184
185static hw_res_ops_t pciintel_hw_res_ops = {
186 &pciintel_get_resources,
187 &pciintel_enable_interrupt
188};
189
190static pci_dev_iface_t pci_dev_ops = {
191 .config_space_read_8 = &pci_config_space_read_8,
192 .config_space_read_16 = &pci_config_space_read_16,
193 .config_space_read_32 = &pci_config_space_read_32,
194 .config_space_write_8 = &pci_config_space_write_8,
195 .config_space_write_16 = &pci_config_space_write_16,
196 .config_space_write_32 = &pci_config_space_write_32
197};
198
199static ddf_dev_ops_t pci_fun_ops = {
200 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
201 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
202};
203
204static int pci_add_device(ddf_dev_t *);
205
206/** PCI bus driver standard operations */
207static driver_ops_t pci_ops = {
208 .add_device = &pci_add_device
209};
210
211/** PCI bus driver structure */
212static driver_t pci_driver = {
213 .name = NAME,
214 .driver_ops = &pci_ops
215};
216
217static pci_bus_t *pci_bus_new(void)
218{
219 pci_bus_t *bus;
220
221 bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
222 if (bus == NULL)
223 return NULL;
224
225 fibril_mutex_initialize(&bus->conf_mutex);
226 return bus;
227}
228
229static void pci_bus_delete(pci_bus_t *bus)
230{
231 assert(bus != NULL);
232 free(bus);
233}
234
235static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
236{
237 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
238
239 fibril_mutex_lock(&bus->conf_mutex);
240
241 uint32_t conf_addr;
242 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
243 void *addr = bus->conf_data_port + (reg & 3);
244
245 pio_write_32(bus->conf_addr_port, conf_addr);
246
247 switch (len) {
248 case 1:
249 buf[0] = pio_read_8(addr);
250 break;
251 case 2:
252 ((uint16_t *) buf)[0] = pio_read_16(addr);
253 break;
254 case 4:
255 ((uint32_t *) buf)[0] = pio_read_32(addr);
256 break;
257 }
258
259 fibril_mutex_unlock(&bus->conf_mutex);
260}
261
262static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
263{
264 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
265
266 fibril_mutex_lock(&bus->conf_mutex);
267
268 uint32_t conf_addr;
269 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
270 void *addr = bus->conf_data_port + (reg & 3);
271
272 pio_write_32(bus->conf_addr_port, conf_addr);
273
274 switch (len) {
275 case 1:
276 pio_write_8(addr, buf[0]);
277 break;
278 case 2:
279 pio_write_16(addr, ((uint16_t *) buf)[0]);
280 break;
281 case 4:
282 pio_write_32(addr, ((uint32_t *) buf)[0]);
283 break;
284 }
285
286 fibril_mutex_unlock(&bus->conf_mutex);
287}
288
289uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
290{
291 uint8_t res;
292 pci_conf_read(fun, reg, &res, 1);
293 return res;
294}
295
296uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
297{
298 uint16_t res;
299 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
300 return res;
301}
302
303uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
304{
305 uint32_t res;
306 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
307 return res;
308}
309
310void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
311{
312 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
313}
314
315void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
316{
317 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
318}
319
320void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
321{
322 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
323}
324
325void pci_fun_create_match_ids(pci_fun_t *fun)
326{
327 char *match_id_str;
328 int rc;
329
330 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
331 fun->vendor_id, fun->device_id);
332
333 if (match_id_str == NULL) {
334 printf(NAME ": out of memory creating match ID.\n");
335 return;
336 }
337
338 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
339 if (rc != EOK) {
340 printf(NAME ": error adding match ID: %s\n",
341 str_error(rc));
342 }
343
344 /* TODO add more ids (with subsys ids, using class id etc.) */
345}
346
347void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
348 bool io)
349{
350 hw_resource_list_t *hw_res_list = &fun->hw_resources;
351 hw_resource_t *hw_resources = hw_res_list->resources;
352 size_t count = hw_res_list->count;
353
354 assert(hw_resources != NULL);
355 assert(count < PCI_MAX_HW_RES);
356
357 if (io) {
358 hw_resources[count].type = IO_RANGE;
359 hw_resources[count].res.io_range.address = range_addr;
360 hw_resources[count].res.io_range.size = range_size;
361 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
362 } else {
363 hw_resources[count].type = MEM_RANGE;
364 hw_resources[count].res.mem_range.address = range_addr;
365 hw_resources[count].res.mem_range.size = range_size;
366 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
367 }
368
369 hw_res_list->count++;
370}
371
372/** Read the base address register (BAR) of the device and if it contains valid
373 * address add it to the devices hw resource list.
374 *
375 * @param fun PCI function
376 * @param addr The address of the BAR in the PCI configuration address space of
377 * the device
378 * @return The addr the address of the BAR which should be read next
379 */
380int pci_read_bar(pci_fun_t *fun, int addr)
381{
382 /* Value of the BAR */
383 uint32_t val, mask;
384 /* IO space address */
385 bool io;
386 /* 64-bit wide address */
387 bool addrw64;
388
389 /* Size of the io or memory range specified by the BAR */
390 size_t range_size;
391 /* Beginning of the io or memory range specified by the BAR */
392 uint64_t range_addr;
393
394 /* Get the value of the BAR. */
395 val = pci_conf_read_32(fun, addr);
396
397#define IO_MASK (~0x3)
398#define MEM_MASK (~0xf)
399
400 io = (bool) (val & 1);
401 if (io) {
402 addrw64 = false;
403 mask = IO_MASK;
404 } else {
405 mask = MEM_MASK;
406 switch ((val >> 1) & 3) {
407 case 0:
408 addrw64 = false;
409 break;
410 case 2:
411 addrw64 = true;
412 break;
413 default:
414 /* reserved, go to the next BAR */
415 return addr + 4;
416 }
417 }
418
419 /* Get the address mask. */
420 pci_conf_write_32(fun, addr, 0xffffffff);
421 mask &= pci_conf_read_32(fun, addr);
422
423 /* Restore the original value. */
424 pci_conf_write_32(fun, addr, val);
425 val = pci_conf_read_32(fun, addr);
426
427 range_size = pci_bar_mask_to_size(mask);
428
429 if (addrw64) {
430 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
431 (val & 0xfffffff0);
432 } else {
433 range_addr = (val & 0xfffffff0);
434 }
435
436 if (range_addr != 0) {
437 printf(NAME ": function %s : ", fun->fnode->name);
438 printf("address = %" PRIx64, range_addr);
439 printf(", size = %x\n", (unsigned int) range_size);
440 }
441
442 pci_add_range(fun, range_addr, range_size, io);
443
444 if (addrw64)
445 return addr + 8;
446
447 return addr + 4;
448}
449
450void pci_add_interrupt(pci_fun_t *fun, int irq)
451{
452 hw_resource_list_t *hw_res_list = &fun->hw_resources;
453 hw_resource_t *hw_resources = hw_res_list->resources;
454 size_t count = hw_res_list->count;
455
456 assert(NULL != hw_resources);
457 assert(count < PCI_MAX_HW_RES);
458
459 hw_resources[count].type = INTERRUPT;
460 hw_resources[count].res.interrupt.irq = irq;
461
462 hw_res_list->count++;
463
464 printf(NAME ": function %s uses irq %x.\n", fun->fnode->name, irq);
465}
466
467void pci_read_interrupt(pci_fun_t *fun)
468{
469 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
470 if (irq != 0xff)
471 pci_add_interrupt(fun, irq);
472}
473
474/** Enumerate (recursively) and register the devices connected to a pci bus.
475 *
476 * @param bus Host-to-PCI bridge
477 * @param bus_num Bus number
478 */
479void pci_bus_scan(pci_bus_t *bus, int bus_num)
480{
481 ddf_fun_t *fnode;
482 pci_fun_t *fun;
483
484 int child_bus = 0;
485 int dnum, fnum;
486 bool multi;
487 uint8_t header_type;
488
489 fun = pci_fun_new(bus);
490
491 for (dnum = 0; dnum < 32; dnum++) {
492 multi = true;
493 for (fnum = 0; multi && fnum < 8; fnum++) {
494 pci_fun_init(fun, bus_num, dnum, fnum);
495 fun->vendor_id = pci_conf_read_16(fun,
496 PCI_VENDOR_ID);
497 fun->device_id = pci_conf_read_16(fun,
498 PCI_DEVICE_ID);
499 if (fun->vendor_id == 0xffff) {
500 /*
501 * The device is not present, go on scanning the
502 * bus.
503 */
504 if (fnum == 0)
505 break;
506 else
507 continue;
508 }
509
510 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
511 if (fnum == 0) {
512 /* Is the device multifunction? */
513 multi = header_type >> 7;
514 }
515 /* Clear the multifunction bit. */
516 header_type = header_type & 0x7F;
517
518 char *fun_name = pci_fun_create_name(fun);
519 if (fun_name == NULL) {
520 printf(NAME ": out of memory.\n");
521 return;
522 }
523
524 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
525 if (fnode == NULL) {
526 printf(NAME ": error creating function.\n");
527 return;
528 }
529
530 free(fun_name);
531 fun->fnode = fnode;
532
533 pci_alloc_resource_list(fun);
534 pci_read_bars(fun);
535 pci_read_interrupt(fun);
536
537 fnode->ops = &pci_fun_ops;
538 fnode->driver_data = fun;
539
540 printf(NAME ": adding new function %s.\n",
541 fnode->name);
542
543 pci_fun_create_match_ids(fun);
544
545 if (ddf_fun_bind(fnode) != EOK) {
546 pci_clean_resource_list(fun);
547 clean_match_ids(&fnode->match_ids);
548 free((char *) fnode->name);
549 fnode->name = NULL;
550 continue;
551 }
552
553 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
554 header_type == PCI_HEADER_TYPE_CARDBUS) {
555 child_bus = pci_conf_read_8(fun,
556 PCI_BRIDGE_SEC_BUS_NUM);
557 printf(NAME ": device is pci-to-pci bridge, "
558 "secondary bus number = %d.\n", bus_num);
559 if (child_bus > bus_num)
560 pci_bus_scan(bus, child_bus);
561 }
562
563 fun = pci_fun_new(bus);
564 }
565 }
566
567 if (fun->vendor_id == 0xffff) {
568 /* Free the auxiliary function structure. */
569 pci_fun_delete(fun);
570 }
571}
572
573static int pci_add_device(ddf_dev_t *dnode)
574{
575 pci_bus_t *bus = NULL;
576 ddf_fun_t *ctl = NULL;
577 bool got_res = false;
578 int rc;
579
580 printf(NAME ": pci_add_device\n");
581 dnode->parent_phone = -1;
582
583 bus = pci_bus_new();
584 if (bus == NULL) {
585 printf(NAME ": pci_add_device allocation failed.\n");
586 rc = ENOMEM;
587 goto fail;
588 }
589 bus->dnode = dnode;
590 dnode->driver_data = bus;
591
592 dnode->parent_phone = devman_parent_device_connect(dnode->handle,
593 IPC_FLAG_BLOCKING);
594 if (dnode->parent_phone < 0) {
595 printf(NAME ": pci_add_device failed to connect to the "
596 "parent's driver.\n");
597 rc = dnode->parent_phone;
598 goto fail;
599 }
600
601 hw_resource_list_t hw_resources;
602
603 rc = hw_res_get_resource_list(dnode->parent_phone, &hw_resources);
604 if (rc != EOK) {
605 printf(NAME ": pci_add_device failed to get hw resources for "
606 "the device.\n");
607 goto fail;
608 }
609 got_res = true;
610
611 printf(NAME ": conf_addr = %" PRIx64 ".\n",
612 hw_resources.resources[0].res.io_range.address);
613
614 assert(hw_resources.count > 0);
615 assert(hw_resources.resources[0].type == IO_RANGE);
616 assert(hw_resources.resources[0].res.io_range.size == 8);
617
618 bus->conf_io_addr =
619 (uint32_t) hw_resources.resources[0].res.io_range.address;
620
621 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
622 &bus->conf_addr_port)) {
623 printf(NAME ": failed to enable configuration ports.\n");
624 rc = EADDRNOTAVAIL;
625 goto fail;
626 }
627 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
628
629 /* Make the bus device more visible. It has no use yet. */
630 printf(NAME ": adding a 'ctl' function\n");
631
632 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
633 if (ctl == NULL) {
634 printf(NAME ": error creating control function.\n");
635 rc = ENOMEM;
636 goto fail;
637 }
638
639 rc = ddf_fun_bind(ctl);
640 if (rc != EOK) {
641 printf(NAME ": error binding control function.\n");
642 goto fail;
643 }
644
645 /* Enumerate functions. */
646 printf(NAME ": scanning the bus\n");
647 pci_bus_scan(bus, 0);
648
649 hw_res_clean_resource_list(&hw_resources);
650
651 return EOK;
652
653fail:
654 if (bus != NULL)
655 pci_bus_delete(bus);
656 if (dnode->parent_phone >= 0)
657 async_hangup(dnode->parent_phone);
658 if (got_res)
659 hw_res_clean_resource_list(&hw_resources);
660 if (ctl != NULL)
661 ddf_fun_destroy(ctl);
662
663 return rc;
664}
665
666static void pciintel_init(void)
667{
668 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
669 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
670}
671
672pci_fun_t *pci_fun_new(pci_bus_t *bus)
673{
674 pci_fun_t *fun;
675
676 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
677 if (fun == NULL)
678 return NULL;
679
680 fun->busptr = bus;
681 return fun;
682}
683
684void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
685{
686 fun->bus = bus;
687 fun->dev = dev;
688 fun->fn = fn;
689}
690
691void pci_fun_delete(pci_fun_t *fun)
692{
693 assert(fun != NULL);
694 hw_res_clean_resource_list(&fun->hw_resources);
695 free(fun);
696}
697
698char *pci_fun_create_name(pci_fun_t *fun)
699{
700 char *name = NULL;
701
702 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
703 fun->fn);
704 return name;
705}
706
707bool pci_alloc_resource_list(pci_fun_t *fun)
708{
709 fun->hw_resources.resources =
710 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
711 return fun->hw_resources.resources != NULL;
712}
713
714void pci_clean_resource_list(pci_fun_t *fun)
715{
716 if (fun->hw_resources.resources != NULL) {
717 free(fun->hw_resources.resources);
718 fun->hw_resources.resources = NULL;
719 }
720}
721
722/** Read the base address registers (BARs) of the function and add the addresses
723 * to its HW resource list.
724 *
725 * @param fun PCI function
726 */
727void pci_read_bars(pci_fun_t *fun)
728{
729 /*
730 * Position of the BAR in the PCI configuration address space of the
731 * device.
732 */
733 int addr = PCI_BASE_ADDR_0;
734
735 while (addr <= PCI_BASE_ADDR_5)
736 addr = pci_read_bar(fun, addr);
737}
738
739size_t pci_bar_mask_to_size(uint32_t mask)
740{
741 size_t size = mask & ~(mask - 1);
742 return size;
743}
744
745int main(int argc, char *argv[])
746{
747 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
748 pciintel_init();
749 return ddf_driver_main(&pci_driver);
750}
751
752/**
753 * @}
754 */
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