source: mainline/uspace/drv/pciintel/pci.c@ 8e7d724

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8e7d724 was 51e5608, checked in by Vojtech Horky <vojtechhorky@…>, 14 years ago

Merge mainline changes (0.4.3 Sashimi)
  • Property mode set to 100644
File size: 17.3 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <devman.h>
51#include <ipc/devman.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ipc/ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <libarch/ddi.h>
61#include <pci_dev_iface.h>
62
63#include "pci.h"
64
65#define NAME "pciintel"
66
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
72
73/** Obtain PCI bus soft-state from DDF device node */
74#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
75
76/** Obtain PCI bus soft-state from function soft-state */
77#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
78
79static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
80{
81 pci_fun_t *fun = PCI_FUN(fnode);
82
83 if (fun == NULL)
84 return NULL;
85 return &fun->hw_resources;
86}
87
88static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
89{
90 /* This is an old ugly way, copied from ne2000 driver */
91 assert(fnode);
92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data;
93
94 sysarg_t apic;
95 sysarg_t i8259;
96
97 int irc_phone = ENOTSUP;
98
99 if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
100 || ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
101 irc_phone = service_connect_blocking(SERVICE_IRC, 0, 0);
102 }
103
104 if (irc_phone < 0) {
105 return false;
106 }
107
108 size_t i;
109 for (i = 0; i < dev_data->hw_resources.count; i++) {
110 if (dev_data->hw_resources.resources[i].type == INTERRUPT) {
111 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq;
112 int rc = async_req_1_0(irc_phone, IRC_ENABLE_INTERRUPT, irq);
113 if (rc != EOK) {
114 async_hangup(irc_phone);
115 return false;
116 }
117 }
118 }
119
120 async_hangup(irc_phone);
121 return true;
122}
123
124static int pci_config_space_write_32(
125 ddf_fun_t *fun, uint32_t address, uint32_t data)
126{
127 if (address > 252)
128 return EINVAL;
129 pci_conf_write_32(PCI_FUN(fun), address, data);
130 return EOK;
131}
132
133static int pci_config_space_write_16(
134 ddf_fun_t *fun, uint32_t address, uint16_t data)
135{
136 if (address > 254)
137 return EINVAL;
138 pci_conf_write_16(PCI_FUN(fun), address, data);
139 return EOK;
140}
141
142static int pci_config_space_write_8(
143 ddf_fun_t *fun, uint32_t address, uint8_t data)
144{
145 if (address > 255)
146 return EINVAL;
147 pci_conf_write_8(PCI_FUN(fun), address, data);
148 return EOK;
149}
150
151static int pci_config_space_read_32(
152 ddf_fun_t *fun, uint32_t address, uint32_t *data)
153{
154 if (address > 252)
155 return EINVAL;
156 *data = pci_conf_read_32(PCI_FUN(fun), address);
157 return EOK;
158}
159
160static int pci_config_space_read_16(
161 ddf_fun_t *fun, uint32_t address, uint16_t *data)
162{
163 if (address > 254)
164 return EINVAL;
165 *data = pci_conf_read_16(PCI_FUN(fun), address);
166 return EOK;
167}
168
169static int pci_config_space_read_8(
170 ddf_fun_t *fun, uint32_t address, uint8_t *data)
171{
172 if (address > 255)
173 return EINVAL;
174 *data = pci_conf_read_8(PCI_FUN(fun), address);
175 return EOK;
176}
177
178static hw_res_ops_t pciintel_hw_res_ops = {
179 &pciintel_get_resources,
180 &pciintel_enable_interrupt
181};
182
183static pci_dev_iface_t pci_dev_ops = {
184 .config_space_read_8 = &pci_config_space_read_8,
185 .config_space_read_16 = &pci_config_space_read_16,
186 .config_space_read_32 = &pci_config_space_read_32,
187 .config_space_write_8 = &pci_config_space_write_8,
188 .config_space_write_16 = &pci_config_space_write_16,
189 .config_space_write_32 = &pci_config_space_write_32
190};
191
192static ddf_dev_ops_t pci_fun_ops = {
193 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
194 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
195};
196
197static int pci_add_device(ddf_dev_t *);
198
199/** PCI bus driver standard operations */
200static driver_ops_t pci_ops = {
201 .add_device = &pci_add_device
202};
203
204/** PCI bus driver structure */
205static driver_t pci_driver = {
206 .name = NAME,
207 .driver_ops = &pci_ops
208};
209
210static pci_bus_t *pci_bus_new(void)
211{
212 pci_bus_t *bus;
213
214 bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
215 if (bus == NULL)
216 return NULL;
217
218 fibril_mutex_initialize(&bus->conf_mutex);
219 return bus;
220}
221
222static void pci_bus_delete(pci_bus_t *bus)
223{
224 assert(bus != NULL);
225 free(bus);
226}
227
228static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
229{
230 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
231
232 fibril_mutex_lock(&bus->conf_mutex);
233
234 uint32_t conf_addr;
235 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
236 void *addr = bus->conf_data_port + (reg & 3);
237
238 pio_write_32(bus->conf_addr_port, conf_addr);
239
240 switch (len) {
241 case 1:
242 buf[0] = pio_read_8(addr);
243 break;
244 case 2:
245 ((uint16_t *) buf)[0] = pio_read_16(addr);
246 break;
247 case 4:
248 ((uint32_t *) buf)[0] = pio_read_32(addr);
249 break;
250 }
251
252 fibril_mutex_unlock(&bus->conf_mutex);
253}
254
255static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
256{
257 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
258
259 fibril_mutex_lock(&bus->conf_mutex);
260
261 uint32_t conf_addr;
262 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
263 void *addr = bus->conf_data_port + (reg & 3);
264
265 pio_write_32(bus->conf_addr_port, conf_addr);
266
267 switch (len) {
268 case 1:
269 pio_write_8(addr, buf[0]);
270 break;
271 case 2:
272 pio_write_16(addr, ((uint16_t *) buf)[0]);
273 break;
274 case 4:
275 pio_write_32(addr, ((uint32_t *) buf)[0]);
276 break;
277 }
278
279 fibril_mutex_unlock(&bus->conf_mutex);
280}
281
282uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
283{
284 uint8_t res;
285 pci_conf_read(fun, reg, &res, 1);
286 return res;
287}
288
289uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
290{
291 uint16_t res;
292 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
293 return res;
294}
295
296uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
297{
298 uint32_t res;
299 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
300 return res;
301}
302
303void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
304{
305 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
306}
307
308void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
309{
310 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
311}
312
313void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
314{
315 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
316}
317
318void pci_fun_create_match_ids(pci_fun_t *fun)
319{
320 char *match_id_str;
321 int rc;
322
323 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
324 fun->vendor_id, fun->device_id);
325
326 if (match_id_str == NULL) {
327 printf(NAME ": out of memory creating match ID.\n");
328 return;
329 }
330
331 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
332 if (rc != EOK) {
333 printf(NAME ": error adding match ID: %s\n",
334 str_error(rc));
335 }
336
337 /* TODO add more ids (with subsys ids, using class id etc.) */
338}
339
340void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
341 bool io)
342{
343 hw_resource_list_t *hw_res_list = &fun->hw_resources;
344 hw_resource_t *hw_resources = hw_res_list->resources;
345 size_t count = hw_res_list->count;
346
347 assert(hw_resources != NULL);
348 assert(count < PCI_MAX_HW_RES);
349
350 if (io) {
351 hw_resources[count].type = IO_RANGE;
352 hw_resources[count].res.io_range.address = range_addr;
353 hw_resources[count].res.io_range.size = range_size;
354 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
355 } else {
356 hw_resources[count].type = MEM_RANGE;
357 hw_resources[count].res.mem_range.address = range_addr;
358 hw_resources[count].res.mem_range.size = range_size;
359 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
360 }
361
362 hw_res_list->count++;
363}
364
365/** Read the base address register (BAR) of the device and if it contains valid
366 * address add it to the devices hw resource list.
367 *
368 * @param fun PCI function
369 * @param addr The address of the BAR in the PCI configuration address space of
370 * the device
371 * @return The addr the address of the BAR which should be read next
372 */
373int pci_read_bar(pci_fun_t *fun, int addr)
374{
375 /* Value of the BAR */
376 uint32_t val, mask;
377 /* IO space address */
378 bool io;
379 /* 64-bit wide address */
380 bool addrw64;
381
382 /* Size of the io or memory range specified by the BAR */
383 size_t range_size;
384 /* Beginning of the io or memory range specified by the BAR */
385 uint64_t range_addr;
386
387 /* Get the value of the BAR. */
388 val = pci_conf_read_32(fun, addr);
389
390#define IO_MASK (~0x3)
391#define MEM_MASK (~0xf)
392
393 io = (bool) (val & 1);
394 if (io) {
395 addrw64 = false;
396 mask = IO_MASK;
397 } else {
398 mask = MEM_MASK;
399 switch ((val >> 1) & 3) {
400 case 0:
401 addrw64 = false;
402 break;
403 case 2:
404 addrw64 = true;
405 break;
406 default:
407 /* reserved, go to the next BAR */
408 return addr + 4;
409 }
410 }
411
412 /* Get the address mask. */
413 pci_conf_write_32(fun, addr, 0xffffffff);
414 mask &= pci_conf_read_32(fun, addr);
415
416 /* Restore the original value. */
417 pci_conf_write_32(fun, addr, val);
418 val = pci_conf_read_32(fun, addr);
419
420 range_size = pci_bar_mask_to_size(mask);
421
422 if (addrw64) {
423 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
424 (val & 0xfffffff0);
425 } else {
426 range_addr = (val & 0xfffffff0);
427 }
428
429 if (range_addr != 0) {
430 printf(NAME ": function %s : ", fun->fnode->name);
431 printf("address = %" PRIx64, range_addr);
432 printf(", size = %x\n", (unsigned int) range_size);
433 }
434
435 pci_add_range(fun, range_addr, range_size, io);
436
437 if (addrw64)
438 return addr + 8;
439
440 return addr + 4;
441}
442
443void pci_add_interrupt(pci_fun_t *fun, int irq)
444{
445 hw_resource_list_t *hw_res_list = &fun->hw_resources;
446 hw_resource_t *hw_resources = hw_res_list->resources;
447 size_t count = hw_res_list->count;
448
449 assert(NULL != hw_resources);
450 assert(count < PCI_MAX_HW_RES);
451
452 hw_resources[count].type = INTERRUPT;
453 hw_resources[count].res.interrupt.irq = irq;
454
455 hw_res_list->count++;
456
457 printf(NAME ": function %s uses irq %x.\n", fun->fnode->name, irq);
458}
459
460void pci_read_interrupt(pci_fun_t *fun)
461{
462 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
463 if (irq != 0xff)
464 pci_add_interrupt(fun, irq);
465}
466
467/** Enumerate (recursively) and register the devices connected to a pci bus.
468 *
469 * @param bus Host-to-PCI bridge
470 * @param bus_num Bus number
471 */
472void pci_bus_scan(pci_bus_t *bus, int bus_num)
473{
474 ddf_fun_t *fnode;
475 pci_fun_t *fun;
476
477 int child_bus = 0;
478 int dnum, fnum;
479 bool multi;
480 uint8_t header_type;
481
482 fun = pci_fun_new(bus);
483
484 for (dnum = 0; dnum < 32; dnum++) {
485 multi = true;
486 for (fnum = 0; multi && fnum < 8; fnum++) {
487 pci_fun_init(fun, bus_num, dnum, fnum);
488 fun->vendor_id = pci_conf_read_16(fun,
489 PCI_VENDOR_ID);
490 fun->device_id = pci_conf_read_16(fun,
491 PCI_DEVICE_ID);
492 if (fun->vendor_id == 0xffff) {
493 /*
494 * The device is not present, go on scanning the
495 * bus.
496 */
497 if (fnum == 0)
498 break;
499 else
500 continue;
501 }
502
503 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
504 if (fnum == 0) {
505 /* Is the device multifunction? */
506 multi = header_type >> 7;
507 }
508 /* Clear the multifunction bit. */
509 header_type = header_type & 0x7F;
510
511 char *fun_name = pci_fun_create_name(fun);
512 if (fun_name == NULL) {
513 printf(NAME ": out of memory.\n");
514 return;
515 }
516
517 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
518 if (fnode == NULL) {
519 printf(NAME ": error creating function.\n");
520 return;
521 }
522
523 free(fun_name);
524 fun->fnode = fnode;
525
526 pci_alloc_resource_list(fun);
527 pci_read_bars(fun);
528 pci_read_interrupt(fun);
529
530 fnode->ops = &pci_fun_ops;
531 fnode->driver_data = fun;
532
533 printf(NAME ": adding new function %s.\n",
534 fnode->name);
535
536 pci_fun_create_match_ids(fun);
537
538 if (ddf_fun_bind(fnode) != EOK) {
539 pci_clean_resource_list(fun);
540 clean_match_ids(&fnode->match_ids);
541 free((char *) fnode->name);
542 fnode->name = NULL;
543 continue;
544 }
545
546 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
547 header_type == PCI_HEADER_TYPE_CARDBUS) {
548 child_bus = pci_conf_read_8(fun,
549 PCI_BRIDGE_SEC_BUS_NUM);
550 printf(NAME ": device is pci-to-pci bridge, "
551 "secondary bus number = %d.\n", bus_num);
552 if (child_bus > bus_num)
553 pci_bus_scan(bus, child_bus);
554 }
555
556 fun = pci_fun_new(bus);
557 }
558 }
559
560 if (fun->vendor_id == 0xffff) {
561 /* Free the auxiliary function structure. */
562 pci_fun_delete(fun);
563 }
564}
565
566static int pci_add_device(ddf_dev_t *dnode)
567{
568 pci_bus_t *bus = NULL;
569 ddf_fun_t *ctl = NULL;
570 bool got_res = false;
571 int rc;
572
573 printf(NAME ": pci_add_device\n");
574 dnode->parent_phone = -1;
575
576 bus = pci_bus_new();
577 if (bus == NULL) {
578 printf(NAME ": pci_add_device allocation failed.\n");
579 rc = ENOMEM;
580 goto fail;
581 }
582 bus->dnode = dnode;
583 dnode->driver_data = bus;
584
585 dnode->parent_phone = devman_parent_device_connect(dnode->handle,
586 IPC_FLAG_BLOCKING);
587 if (dnode->parent_phone < 0) {
588 printf(NAME ": pci_add_device failed to connect to the "
589 "parent's driver.\n");
590 rc = dnode->parent_phone;
591 goto fail;
592 }
593
594 hw_resource_list_t hw_resources;
595
596 rc = hw_res_get_resource_list(dnode->parent_phone, &hw_resources);
597 if (rc != EOK) {
598 printf(NAME ": pci_add_device failed to get hw resources for "
599 "the device.\n");
600 goto fail;
601 }
602 got_res = true;
603
604 printf(NAME ": conf_addr = %" PRIx64 ".\n",
605 hw_resources.resources[0].res.io_range.address);
606
607 assert(hw_resources.count > 0);
608 assert(hw_resources.resources[0].type == IO_RANGE);
609 assert(hw_resources.resources[0].res.io_range.size == 8);
610
611 bus->conf_io_addr =
612 (uint32_t) hw_resources.resources[0].res.io_range.address;
613
614 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
615 &bus->conf_addr_port)) {
616 printf(NAME ": failed to enable configuration ports.\n");
617 rc = EADDRNOTAVAIL;
618 goto fail;
619 }
620 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
621
622 /* Make the bus device more visible. It has no use yet. */
623 printf(NAME ": adding a 'ctl' function\n");
624
625 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
626 if (ctl == NULL) {
627 printf(NAME ": error creating control function.\n");
628 rc = ENOMEM;
629 goto fail;
630 }
631
632 rc = ddf_fun_bind(ctl);
633 if (rc != EOK) {
634 printf(NAME ": error binding control function.\n");
635 goto fail;
636 }
637
638 /* Enumerate functions. */
639 printf(NAME ": scanning the bus\n");
640 pci_bus_scan(bus, 0);
641
642 hw_res_clean_resource_list(&hw_resources);
643
644 return EOK;
645
646fail:
647 if (bus != NULL)
648 pci_bus_delete(bus);
649 if (dnode->parent_phone >= 0)
650 async_hangup(dnode->parent_phone);
651 if (got_res)
652 hw_res_clean_resource_list(&hw_resources);
653 if (ctl != NULL)
654 ddf_fun_destroy(ctl);
655
656 return rc;
657}
658
659static void pciintel_init(void)
660{
661 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
662 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
663}
664
665pci_fun_t *pci_fun_new(pci_bus_t *bus)
666{
667 pci_fun_t *fun;
668
669 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
670 if (fun == NULL)
671 return NULL;
672
673 fun->busptr = bus;
674 return fun;
675}
676
677void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
678{
679 fun->bus = bus;
680 fun->dev = dev;
681 fun->fn = fn;
682}
683
684void pci_fun_delete(pci_fun_t *fun)
685{
686 assert(fun != NULL);
687 hw_res_clean_resource_list(&fun->hw_resources);
688 free(fun);
689}
690
691char *pci_fun_create_name(pci_fun_t *fun)
692{
693 char *name = NULL;
694
695 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
696 fun->fn);
697 return name;
698}
699
700bool pci_alloc_resource_list(pci_fun_t *fun)
701{
702 fun->hw_resources.resources =
703 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
704 return fun->hw_resources.resources != NULL;
705}
706
707void pci_clean_resource_list(pci_fun_t *fun)
708{
709 if (fun->hw_resources.resources != NULL) {
710 free(fun->hw_resources.resources);
711 fun->hw_resources.resources = NULL;
712 }
713}
714
715/** Read the base address registers (BARs) of the function and add the addresses
716 * to its HW resource list.
717 *
718 * @param fun PCI function
719 */
720void pci_read_bars(pci_fun_t *fun)
721{
722 /*
723 * Position of the BAR in the PCI configuration address space of the
724 * device.
725 */
726 int addr = PCI_BASE_ADDR_0;
727
728 while (addr <= PCI_BASE_ADDR_5)
729 addr = pci_read_bar(fun, addr);
730}
731
732size_t pci_bar_mask_to_size(uint32_t mask)
733{
734 size_t size = mask & ~(mask - 1);
735 return size;
736}
737
738int main(int argc, char *argv[])
739{
740 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
741 pciintel_init();
742 return ddf_driver_main(&pci_driver);
743}
744
745/**
746 * @}
747 */
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