source: mainline/uspace/drv/pciintel/pci.c@ 8b1e15ac

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8b1e15ac was 8b1e15ac, checked in by Jiri Svoboda <jiri@…>, 14 years ago

Finish splitting device node: devman client in C library, drv library. Update device drivers accordingly.
  • Property mode set to 100644
File size: 15.2 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @defgroup pciintel pci bus driver for intel method 1.
31 * @brief HelenOS root pci bus driver for intel method 1.
32 * @{
33 */
34
35/** @file
36 */
37
38#include <assert.h>
39#include <stdio.h>
40#include <errno.h>
41#include <bool.h>
42#include <fibril_synch.h>
43#include <str.h>
44#include <ctype.h>
45#include <macros.h>
46
47#include <driver.h>
48#include <devman.h>
49#include <ipc/devman.h>
50#include <ipc/dev_iface.h>
51#include <ops/hw_res.h>
52#include <device/hw_res.h>
53#include <ddi.h>
54#include <libarch/ddi.h>
55
56#include "pci.h"
57
58#define NAME "pciintel"
59
60#define CONF_ADDR(bus, dev, fn, reg) \
61 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
62
63static hw_resource_list_t *pciintel_get_child_resources(function_t *fun)
64{
65 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
66
67 if (fun_data == NULL)
68 return NULL;
69 return &fun_data->hw_resources;
70}
71
72static bool pciintel_enable_child_interrupt(function_t *fun)
73{
74 /* TODO */
75
76 return false;
77}
78
79static hw_res_ops_t pciintel_child_hw_res_ops = {
80 &pciintel_get_child_resources,
81 &pciintel_enable_child_interrupt
82};
83
84static device_ops_t pci_child_ops;
85
86static int pci_add_device(device_t *);
87
88/** The pci bus driver's standard operations. */
89static driver_ops_t pci_ops = {
90 .add_device = &pci_add_device
91};
92
93/** The pci bus driver structure. */
94static driver_t pci_driver = {
95 .name = NAME,
96 .driver_ops = &pci_ops
97};
98
99typedef struct pciintel_bus_data {
100 uint32_t conf_io_addr;
101 void *conf_data_port;
102 void *conf_addr_port;
103 fibril_mutex_t conf_mutex;
104} pci_bus_data_t;
105
106static pci_bus_data_t *create_pci_bus_data(void)
107{
108 pci_bus_data_t *bus_data;
109
110 bus_data = (pci_bus_data_t *) malloc(sizeof(pci_bus_data_t));
111 if (bus_data != NULL) {
112 memset(bus_data, 0, sizeof(pci_bus_data_t));
113 fibril_mutex_initialize(&bus_data->conf_mutex);
114 }
115
116 return bus_data;
117}
118
119static void delete_pci_bus_data(pci_bus_data_t *bus_data)
120{
121 free(bus_data);
122}
123
124static void pci_conf_read(function_t *fun, int reg, uint8_t *buf, size_t len)
125{
126 assert(fun->dev != NULL);
127
128 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
129 pci_bus_data_t *bus_data = (pci_bus_data_t *) fun->dev->driver_data;
130
131 fibril_mutex_lock(&bus_data->conf_mutex);
132
133 uint32_t conf_addr;
134 conf_addr = CONF_ADDR(fun_data->bus, fun_data->dev, fun_data->fn, reg);
135 void *addr = bus_data->conf_data_port + (reg & 3);
136
137 pio_write_32(bus_data->conf_addr_port, conf_addr);
138
139 switch (len) {
140 case 1:
141 buf[0] = pio_read_8(addr);
142 break;
143 case 2:
144 ((uint16_t *) buf)[0] = pio_read_16(addr);
145 break;
146 case 4:
147 ((uint32_t *) buf)[0] = pio_read_32(addr);
148 break;
149 }
150
151 fibril_mutex_unlock(&bus_data->conf_mutex);
152}
153
154static void pci_conf_write(function_t *fun, int reg, uint8_t *buf, size_t len)
155{
156 assert(fun->dev != NULL);
157
158 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
159 pci_bus_data_t *bus_data = (pci_bus_data_t *) fun->dev->driver_data;
160
161 fibril_mutex_lock(&bus_data->conf_mutex);
162
163 uint32_t conf_addr;
164 conf_addr = CONF_ADDR(fun_data->bus, fun_data->dev, fun_data->fn, reg);
165 void *addr = bus_data->conf_data_port + (reg & 3);
166
167 pio_write_32(bus_data->conf_addr_port, conf_addr);
168
169 switch (len) {
170 case 1:
171 pio_write_8(addr, buf[0]);
172 break;
173 case 2:
174 pio_write_16(addr, ((uint16_t *) buf)[0]);
175 break;
176 case 4:
177 pio_write_32(addr, ((uint32_t *) buf)[0]);
178 break;
179 }
180
181 fibril_mutex_unlock(&bus_data->conf_mutex);
182}
183
184uint8_t pci_conf_read_8(function_t *fun, int reg)
185{
186 uint8_t res;
187 pci_conf_read(fun, reg, &res, 1);
188 return res;
189}
190
191uint16_t pci_conf_read_16(function_t *fun, int reg)
192{
193 uint16_t res;
194 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
195 return res;
196}
197
198uint32_t pci_conf_read_32(function_t *fun, int reg)
199{
200 uint32_t res;
201 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
202 return res;
203}
204
205void pci_conf_write_8(function_t *fun, int reg, uint8_t val)
206{
207 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
208}
209
210void pci_conf_write_16(function_t *fun, int reg, uint16_t val)
211{
212 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
213}
214
215void pci_conf_write_32(function_t *fun, int reg, uint32_t val)
216{
217 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
218}
219
220void create_pci_match_ids(function_t *fun)
221{
222 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
223 match_id_t *match_id = NULL;
224 char *match_id_str;
225
226 match_id = create_match_id();
227 if (match_id != NULL) {
228 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
229 fun_data->vendor_id, fun_data->device_id);
230 match_id->id = match_id_str;
231 match_id->score = 90;
232 add_match_id(&fun->match_ids, match_id);
233 }
234
235 /* TODO add more ids (with subsys ids, using class id etc.) */
236}
237
238void
239pci_add_range(function_t *fun, uint64_t range_addr, size_t range_size, bool io)
240{
241 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
242 hw_resource_list_t *hw_res_list = &fun_data->hw_resources;
243 hw_resource_t *hw_resources = hw_res_list->resources;
244 size_t count = hw_res_list->count;
245
246 assert(hw_resources != NULL);
247 assert(count < PCI_MAX_HW_RES);
248
249 if (io) {
250 hw_resources[count].type = IO_RANGE;
251 hw_resources[count].res.io_range.address = range_addr;
252 hw_resources[count].res.io_range.size = range_size;
253 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
254 } else {
255 hw_resources[count].type = MEM_RANGE;
256 hw_resources[count].res.mem_range.address = range_addr;
257 hw_resources[count].res.mem_range.size = range_size;
258 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
259 }
260
261 hw_res_list->count++;
262}
263
264/** Read the base address register (BAR) of the device and if it contains valid
265 * address add it to the devices hw resource list.
266 *
267 * @param dev The pci device.
268 * @param addr The address of the BAR in the PCI configuration address space of
269 * the device.
270 * @return The addr the address of the BAR which should be read next.
271 */
272int pci_read_bar(function_t *fun, int addr)
273{
274 /* Value of the BAR */
275 uint32_t val, mask;
276 /* IO space address */
277 bool io;
278 /* 64-bit wide address */
279 bool addrw64;
280
281 /* Size of the io or memory range specified by the BAR */
282 size_t range_size;
283 /* Beginning of the io or memory range specified by the BAR */
284 uint64_t range_addr;
285
286 /* Get the value of the BAR. */
287 val = pci_conf_read_32(fun, addr);
288
289 io = (bool) (val & 1);
290 if (io) {
291 addrw64 = false;
292 } else {
293 switch ((val >> 1) & 3) {
294 case 0:
295 addrw64 = false;
296 break;
297 case 2:
298 addrw64 = true;
299 break;
300 default:
301 /* reserved, go to the next BAR */
302 return addr + 4;
303 }
304 }
305
306 /* Get the address mask. */
307 pci_conf_write_32(fun, addr, 0xffffffff);
308 mask = pci_conf_read_32(fun, addr);
309
310 /* Restore the original value. */
311 pci_conf_write_32(fun, addr, val);
312 val = pci_conf_read_32(fun, addr);
313
314 range_size = pci_bar_mask_to_size(mask);
315
316 if (addrw64) {
317 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
318 (val & 0xfffffff0);
319 } else {
320 range_addr = (val & 0xfffffff0);
321 }
322
323 if (range_addr != 0) {
324 printf(NAME ": function %s : ", fun->name);
325 printf("address = %" PRIx64, range_addr);
326 printf(", size = %x\n", (unsigned int) range_size);
327 }
328
329 pci_add_range(fun, range_addr, range_size, io);
330
331 if (addrw64)
332 return addr + 8;
333
334 return addr + 4;
335}
336
337void pci_add_interrupt(function_t *fun, int irq)
338{
339 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
340 hw_resource_list_t *hw_res_list = &fun_data->hw_resources;
341 hw_resource_t *hw_resources = hw_res_list->resources;
342 size_t count = hw_res_list->count;
343
344 assert(NULL != hw_resources);
345 assert(count < PCI_MAX_HW_RES);
346
347 hw_resources[count].type = INTERRUPT;
348 hw_resources[count].res.interrupt.irq = irq;
349
350 hw_res_list->count++;
351
352 printf(NAME ": function %s uses irq %x.\n", fun->name, irq);
353}
354
355void pci_read_interrupt(function_t *fun)
356{
357 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
358 if (irq != 0xff)
359 pci_add_interrupt(fun, irq);
360}
361
362/** Enumerate (recursively) and register the devices connected to a pci bus.
363 *
364 * @param dev The host-to-pci bridge device.
365 * @param bus_num The bus number.
366 */
367void pci_bus_scan(device_t *dev, int bus_num)
368{
369 function_t *fun = create_function();
370 pci_fun_data_t *fun_data = create_pci_fun_data();
371 fun->driver_data = fun_data;
372
373 int child_bus = 0;
374 int dnum, fnum;
375 bool multi;
376 uint8_t header_type;
377
378 /* We need this early, before registering. */
379 fun->dev = dev;
380
381 for (dnum = 0; dnum < 32; dnum++) {
382 multi = true;
383 for (fnum = 0; multi && fnum < 8; fnum++) {
384 init_pci_fun_data(fun_data, bus_num, dnum, fnum);
385 fun_data->vendor_id = pci_conf_read_16(fun,
386 PCI_VENDOR_ID);
387 fun_data->device_id = pci_conf_read_16(fun,
388 PCI_DEVICE_ID);
389 if (fun_data->vendor_id == 0xffff) {
390 /*
391 * The device is not present, go on scanning the
392 * bus.
393 */
394 if (fnum == 0)
395 break;
396 else
397 continue;
398 }
399
400 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
401 if (fnum == 0) {
402 /* Is the device multifunction? */
403 multi = header_type >> 7;
404 }
405 /* Clear the multifunction bit. */
406 header_type = header_type & 0x7F;
407
408 create_pci_fun_name(fun);
409
410 pci_alloc_resource_list(fun);
411 pci_read_bars(fun);
412 pci_read_interrupt(fun);
413
414 fun->ftype = fun_inner;
415 fun->ops = &pci_child_ops;
416
417 printf(NAME ": adding new function %s.\n",
418 fun->name);
419
420 create_pci_match_ids(fun);
421
422 if (register_function(fun, dev) != EOK) {
423 pci_clean_resource_list(fun);
424 clean_match_ids(&fun->match_ids);
425 free((char *) fun->name);
426 fun->name = NULL;
427 continue;
428 }
429
430 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
431 header_type == PCI_HEADER_TYPE_CARDBUS) {
432 child_bus = pci_conf_read_8(fun,
433 PCI_BRIDGE_SEC_BUS_NUM);
434 printf(NAME ": device is pci-to-pci bridge, "
435 "secondary bus number = %d.\n", bus_num);
436 if (child_bus > bus_num)
437 pci_bus_scan(dev, child_bus);
438 }
439
440 /* Alloc new aux. fun. structure. */
441 fun = create_function();
442
443 /* We need this early, before registering. */
444 fun->dev = dev;
445
446 fun_data = create_pci_fun_data();
447 fun->driver_data = fun_data;
448 }
449 }
450
451 if (fun_data->vendor_id == 0xffff) {
452 delete_function(fun);
453 /* Free the auxiliary function structure. */
454 delete_pci_fun_data(fun_data);
455 }
456}
457
458static int pci_add_device(device_t *dev)
459{
460 int rc;
461
462 printf(NAME ": pci_add_device\n");
463
464 pci_bus_data_t *bus_data = create_pci_bus_data();
465 if (bus_data == NULL) {
466 printf(NAME ": pci_add_device allocation failed.\n");
467 return ENOMEM;
468 }
469
470 dev->parent_phone = devman_parent_device_connect(dev->handle,
471 IPC_FLAG_BLOCKING);
472 if (dev->parent_phone < 0) {
473 printf(NAME ": pci_add_device failed to connect to the "
474 "parent's driver.\n");
475 delete_pci_bus_data(bus_data);
476 return dev->parent_phone;
477 }
478
479 hw_resource_list_t hw_resources;
480
481 rc = hw_res_get_resource_list(dev->parent_phone, &hw_resources);
482 if (rc != EOK) {
483 printf(NAME ": pci_add_device failed to get hw resources for "
484 "the device.\n");
485 delete_pci_bus_data(bus_data);
486 async_hangup(dev->parent_phone);
487 return rc;
488 }
489
490 printf(NAME ": conf_addr = %" PRIx64 ".\n",
491 hw_resources.resources[0].res.io_range.address);
492
493 assert(hw_resources.count > 0);
494 assert(hw_resources.resources[0].type == IO_RANGE);
495 assert(hw_resources.resources[0].res.io_range.size == 8);
496
497 bus_data->conf_io_addr =
498 (uint32_t) hw_resources.resources[0].res.io_range.address;
499
500 if (pio_enable((void *)(uintptr_t)bus_data->conf_io_addr, 8,
501 &bus_data->conf_addr_port)) {
502 printf(NAME ": failed to enable configuration ports.\n");
503 delete_pci_bus_data(bus_data);
504 async_hangup(dev->parent_phone);
505 hw_res_clean_resource_list(&hw_resources);
506 return EADDRNOTAVAIL;
507 }
508 bus_data->conf_data_port = (char *) bus_data->conf_addr_port + 4;
509
510 dev->driver_data = bus_data;
511
512 /* Make the bus device more visible. Does not do anything. */
513 printf(NAME ": adding a 'ctl' function\n");
514
515 function_t *ctl = create_function();
516 ctl->ftype = fun_exposed;
517 ctl->name = "ctl";
518 register_function(ctl, dev);
519
520 /* Enumerate child devices. */
521 printf(NAME ": scanning the bus\n");
522 pci_bus_scan(dev, 0);
523
524 hw_res_clean_resource_list(&hw_resources);
525
526 return EOK;
527}
528
529static void pciintel_init(void)
530{
531 pci_child_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_child_hw_res_ops;
532}
533
534pci_fun_data_t *create_pci_fun_data(void)
535{
536 pci_fun_data_t *res = (pci_fun_data_t *) malloc(sizeof(pci_fun_data_t));
537
538 if (res != NULL)
539 memset(res, 0, sizeof(pci_fun_data_t));
540 return res;
541}
542
543void init_pci_fun_data(pci_fun_data_t *fun_data, int bus, int dev, int fn)
544{
545 fun_data->bus = bus;
546 fun_data->dev = dev;
547 fun_data->fn = fn;
548}
549
550void delete_pci_fun_data(pci_fun_data_t *fun_data)
551{
552 if (fun_data != NULL) {
553 hw_res_clean_resource_list(&fun_data->hw_resources);
554 free(fun_data);
555 }
556}
557
558void create_pci_fun_name(function_t *fun)
559{
560 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
561 char *name = NULL;
562
563 asprintf(&name, "%02x:%02x.%01x", fun_data->bus, fun_data->dev,
564 fun_data->fn);
565 fun->name = name;
566}
567
568bool pci_alloc_resource_list(function_t *fun)
569{
570 pci_fun_data_t *fun_data = (pci_fun_data_t *)fun->driver_data;
571
572 fun_data->hw_resources.resources =
573 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
574 return fun_data->hw_resources.resources != NULL;
575}
576
577void pci_clean_resource_list(function_t *fun)
578{
579 pci_fun_data_t *fun_data = (pci_fun_data_t *) fun->driver_data;
580
581 if (fun_data->hw_resources.resources != NULL) {
582 free(fun_data->hw_resources.resources);
583 fun_data->hw_resources.resources = NULL;
584 }
585}
586
587/** Read the base address registers (BARs) of the device and adds the addresses
588 * to its hw resource list.
589 *
590 * @param dev the pci device.
591 */
592void pci_read_bars(function_t *fun)
593{
594 /*
595 * Position of the BAR in the PCI configuration address space of the
596 * device.
597 */
598 int addr = PCI_BASE_ADDR_0;
599
600 while (addr <= PCI_BASE_ADDR_5)
601 addr = pci_read_bar(fun, addr);
602}
603
604size_t pci_bar_mask_to_size(uint32_t mask)
605{
606 return ((mask & 0xfffffff0) ^ 0xffffffff) + 1;
607}
608
609int main(int argc, char *argv[])
610{
611 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
612 pciintel_init();
613 return driver_main(&pci_driver);
614}
615
616/**
617 * @}
618 */
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