source: mainline/uspace/drv/pciintel/pci.c@ 472020fc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 472020fc was 472020fc, checked in by Jakub Jermar <jakub@…>, 15 years ago

Mark EPARTY for replacement by another error code.
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1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @defgroup pciintel pci bus driver for intel method 1.
31 * @brief HelenOS root pci bus driver for intel method 1.
32 * @{
33 */
34
35/** @file
36 */
37
38#include <assert.h>
39#include <stdio.h>
40#include <errno.h>
41#include <bool.h>
42#include <fibril_synch.h>
43#include <str.h>
44#include <ctype.h>
45#include <macros.h>
46
47#include <driver.h>
48#include <devman.h>
49#include <ipc/devman.h>
50#include <ipc/dev_iface.h>
51#include <resource.h>
52#include <device/hw_res.h>
53#include <ddi.h>
54#include <libarch/ddi.h>
55
56#include "pci.h"
57
58#define NAME "pciintel"
59
60#define CONF_ADDR(bus, dev, fn, reg) ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
61
62
63static hw_resource_list_t * pciintel_get_child_resources(device_t *dev)
64{
65 pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
66 if (NULL == dev_data) {
67 return NULL;
68 }
69 return &dev_data->hw_resources;
70}
71
72static bool pciintel_enable_child_interrupt(device_t *dev)
73{
74 // TODO
75
76 return false;
77}
78
79static resource_iface_t pciintel_child_res_iface = {
80 &pciintel_get_child_resources,
81 &pciintel_enable_child_interrupt
82};
83
84static device_ops_t pci_child_ops;
85
86
87static int pci_add_device(device_t *dev);
88
89/** The pci bus driver's standard operations.
90 */
91static driver_ops_t pci_ops = {
92 .add_device = &pci_add_device
93};
94
95/** The pci bus driver structure.
96 */
97static driver_t pci_driver = {
98 .name = NAME,
99 .driver_ops = &pci_ops
100};
101
102typedef struct pciintel_bus_data {
103 uint32_t conf_io_addr;
104 void *conf_data_port;
105 void *conf_addr_port;
106 fibril_mutex_t conf_mutex;
107} pci_bus_data_t;
108
109static inline pci_bus_data_t *create_pci_bus_data()
110{
111 pci_bus_data_t *bus_data = (pci_bus_data_t *)malloc(sizeof(pci_bus_data_t));
112 if(NULL != bus_data) {
113 memset(bus_data, 0, sizeof(pci_bus_data_t));
114 fibril_mutex_initialize(&bus_data->conf_mutex);
115 }
116 return bus_data;
117}
118
119static inline void delete_pci_bus_data(pci_bus_data_t *bus_data)
120{
121 free(bus_data);
122}
123
124static void pci_conf_read(device_t *dev, int reg, uint8_t *buf, size_t len)
125{
126 assert(NULL != dev->parent);
127
128 pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
129 pci_bus_data_t *bus_data = (pci_bus_data_t *)dev->parent->driver_data;
130
131 fibril_mutex_lock(&bus_data->conf_mutex);
132
133 uint32_t conf_addr = CONF_ADDR(dev_data->bus, dev_data->dev, dev_data->fn, reg);
134 void *addr = bus_data->conf_data_port + (reg & 3);
135
136 pio_write_32(bus_data->conf_addr_port, conf_addr);
137
138 switch (len) {
139 case 1:
140 buf[0] = pio_read_8(addr);
141 break;
142 case 2:
143 ((uint16_t *)buf)[0] = pio_read_16(addr);
144 break;
145 case 4:
146 ((uint32_t *)buf)[0] = pio_read_32(addr);
147 break;
148 }
149
150 fibril_mutex_unlock(&bus_data->conf_mutex);
151}
152
153static void pci_conf_write(device_t *dev, int reg, uint8_t *buf, size_t len)
154{
155 assert(NULL != dev->parent);
156
157 pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
158 pci_bus_data_t *bus_data = (pci_bus_data_t *)dev->parent->driver_data;
159
160 fibril_mutex_lock(&bus_data->conf_mutex);
161
162 uint32_t conf_addr = CONF_ADDR(dev_data->bus, dev_data->dev, dev_data->fn, reg);
163 void *addr = bus_data->conf_data_port + (reg & 3);
164
165 pio_write_32(bus_data->conf_addr_port, conf_addr);
166
167 switch (len) {
168 case 1:
169 pio_write_8(addr, buf[0]);
170 break;
171 case 2:
172 pio_write_16(addr, ((uint16_t *)buf)[0]);
173 break;
174 case 4:
175 pio_write_32(addr, ((uint32_t *)buf)[0]);
176 break;
177 }
178
179 fibril_mutex_unlock(&bus_data->conf_mutex);
180}
181
182uint8_t pci_conf_read_8(device_t *dev, int reg)
183{
184 uint8_t res;
185 pci_conf_read(dev, reg, &res, 1);
186 return res;
187}
188
189uint16_t pci_conf_read_16(device_t *dev, int reg)
190{
191 uint16_t res;
192 pci_conf_read(dev, reg, (uint8_t *)&res, 2);
193 return res;
194}
195
196uint32_t pci_conf_read_32(device_t *dev, int reg)
197{
198 uint32_t res;
199 pci_conf_read(dev, reg, (uint8_t *)&res, 4);
200 return res;
201}
202
203void pci_conf_write_8(device_t *dev, int reg, uint8_t val)
204{
205 pci_conf_write(dev, reg, (uint8_t *)&val, 1);
206}
207
208void pci_conf_write_16(device_t *dev, int reg, uint16_t val)
209{
210 pci_conf_write(dev, reg, (uint8_t *)&val, 2);
211}
212
213void pci_conf_write_32(device_t *dev, int reg, uint32_t val)
214{
215 pci_conf_write(dev, reg, (uint8_t *)&val, 4);
216}
217
218
219void create_pci_match_ids(device_t *dev)
220{
221 pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
222 match_id_t *match_id = NULL;
223 char *match_id_str;
224 match_id = create_match_id();
225 if (NULL != match_id) {
226 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x", dev_data->vendor_id, dev_data->device_id);
227 match_id->id = match_id_str;
228 match_id->score = 90;
229 add_match_id(&dev->match_ids, match_id);
230 }
231 // TODO add more ids (with subsys ids, using class id etc.)
232}
233
234void pci_add_range(device_t *dev, uint64_t range_addr, size_t range_size, bool io)
235{
236 pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
237 hw_resource_list_t *hw_res_list = &dev_data->hw_resources;
238 hw_resource_t *hw_resources = hw_res_list->resources;
239 size_t count = hw_res_list->count;
240
241 assert(NULL != hw_resources);
242 assert(count < PCI_MAX_HW_RES);
243
244 if (io) {
245 hw_resources[count].type = IO_RANGE;
246 hw_resources[count].res.io_range.address = range_addr;
247 hw_resources[count].res.io_range.size = range_size;
248 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
249 } else {
250 hw_resources[count].type = MEM_RANGE;
251 hw_resources[count].res.mem_range.address = range_addr;
252 hw_resources[count].res.mem_range.size = range_size;
253 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
254 }
255
256 hw_res_list->count++;
257}
258
259
260/** Read the base address register (BAR) of the device
261 * and if it contains valid address add it to the devices hw resource list.
262 *
263 * @param dev the pci device.
264 * @param addr the address of the BAR in the PCI configuration address space of the device.
265 *
266 * @return the addr the address of the BAR which should be read next.
267 */
268int pci_read_bar(device_t *dev, int addr)
269{
270 // value of the BAR
271 uint32_t val, mask;
272 // IO space address
273 bool io;
274 // 64-bit wide address
275 bool w64;
276
277 // size of the io or memory range specified by the BAR
278 size_t range_size;
279 // beginning of the io or memory range specified by the BAR
280 uint64_t range_addr;
281
282 // get the value of the BAR
283 val = pci_conf_read_32(dev, addr);
284
285 io = (bool)(val & 1);
286 if (io) {
287 w64 = false;
288 } else {
289 switch ((val >> 1) & 3) {
290 case 0:
291 w64 = false;
292 break;
293 case 2:
294 w64 = true;
295 break;
296 default:
297 // reserved, go to the next BAR
298 return addr + 4;
299 }
300 }
301
302 // get the address mask
303 pci_conf_write_32(dev, addr, 0xffffffff);
304 mask = pci_conf_read_32(dev, addr);
305
306 // restore the original value
307 pci_conf_write_32(dev, addr, val);
308 val = pci_conf_read_32(dev, addr);
309
310 range_size = pci_bar_mask_to_size(mask);
311
312 if (w64) {
313 range_addr = ((uint64_t)pci_conf_read_32(dev, addr + 4) << 32) | (val & 0xfffffff0);
314 } else {
315 range_addr = (val & 0xfffffff0);
316 }
317 if (0 != range_addr) {
318 printf(NAME ": device %s : ", dev->name);
319 printf("address = %x", range_addr);
320 printf(", size = %x\n", range_size);
321 }
322
323 pci_add_range(dev, range_addr, range_size, io);
324
325 if (w64) {
326 return addr + 8;
327 }
328 return addr + 4;
329}
330
331void pci_add_interrupt(device_t *dev, int irq)
332{
333 pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
334 hw_resource_list_t *hw_res_list = &dev_data->hw_resources;
335 hw_resource_t *hw_resources = hw_res_list->resources;
336 size_t count = hw_res_list->count;
337
338 assert(NULL != hw_resources);
339 assert(count < PCI_MAX_HW_RES);
340
341 hw_resources[count].type = INTERRUPT;
342 hw_resources[count].res.interrupt.irq = irq;
343
344 hw_res_list->count++;
345
346
347 printf(NAME ": device %s uses irq %x.\n", dev->name, irq);
348}
349
350void pci_read_interrupt(device_t *dev)
351{
352 uint8_t irq = pci_conf_read_8(dev, PCI_BRIDGE_INT_LINE);
353 if (0xff != irq) {
354 pci_add_interrupt(dev, irq);
355 }
356}
357
358/** Enumerate (recursively) and register the devices connected to a pci bus.
359 *
360 * @param parent the host-to-pci bridge device.
361 * @param bus_num the bus number.
362 */
363void pci_bus_scan(device_t *parent, int bus_num)
364{
365 device_t *dev = create_device();
366 pci_dev_data_t *dev_data = create_pci_dev_data();
367 dev->driver_data = dev_data;
368 dev->parent = parent;
369
370 int child_bus = 0;
371 int dnum, fnum;
372 bool multi;
373 uint8_t header_type;
374
375 for (dnum = 0; dnum < 32; dnum++) {
376 multi = true;
377 for (fnum = 0; multi && fnum < 8; fnum++) {
378 init_pci_dev_data(dev_data, bus_num, dnum, fnum);
379 dev_data->vendor_id = pci_conf_read_16(dev, PCI_VENDOR_ID);
380 dev_data->device_id = pci_conf_read_16(dev, PCI_DEVICE_ID);
381 if (dev_data->vendor_id == 0xffff) { // device is not present, go on scanning the bus
382 if (fnum == 0) {
383 break;
384 } else {
385 continue;
386 }
387 }
388 header_type = pci_conf_read_8(dev, PCI_HEADER_TYPE);
389 if (fnum == 0) {
390 multi = header_type >> 7; // is the device multifunction?
391 }
392 header_type = header_type & 0x7F; // clear the multifunction bit
393
394 create_pci_dev_name(dev);
395
396 pci_alloc_resource_list(dev);
397 pci_read_bars(dev);
398 pci_read_interrupt(dev);
399
400 dev->ops = &pci_child_ops;
401
402 printf(NAME ": adding new child device %s.\n", dev->name);
403
404 create_pci_match_ids(dev);
405
406 if (EOK != child_device_register(dev, parent)) {
407 pci_clean_resource_list(dev);
408 clean_match_ids(&dev->match_ids);
409 free((char *)dev->name);
410 dev->name = NULL;
411 continue;
412 }
413
414 //printf(NAME ": new device %s was successfully registered by device manager.\n", dev->name);
415
416 if (header_type == PCI_HEADER_TYPE_BRIDGE || header_type == PCI_HEADER_TYPE_CARDBUS ) {
417 child_bus = pci_conf_read_8(dev, PCI_BRIDGE_SEC_BUS_NUM);
418 printf(NAME ": device is pci-to-pci bridge, secondary bus number = %d.\n", bus_num);
419 if(child_bus > bus_num) {
420 pci_bus_scan(parent, child_bus);
421 }
422 }
423
424 dev = create_device(); // alloc new aux. dev. structure
425 dev_data = create_pci_dev_data();
426 dev->driver_data = dev_data;
427 dev->parent = parent;
428 }
429 }
430
431 if (dev_data->vendor_id == 0xffff) {
432 delete_device(dev);
433 delete_pci_dev_data(dev_data); // free the auxiliary device structure
434 }
435}
436
437static int pci_add_device(device_t *dev)
438{
439 printf(NAME ": pci_add_device\n");
440
441 pci_bus_data_t *bus_data = create_pci_bus_data();
442 if (NULL == bus_data) {
443 printf(NAME ": pci_add_device allocation failed.\n");
444 return ENOMEM;
445 }
446
447 dev->parent_phone = devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);
448 if (dev->parent_phone <= 0) {
449 printf(NAME ": pci_add_device failed to connect to the parent's driver.\n");
450 delete_pci_bus_data(bus_data);
451 return EPARTY; /* FIXME: use another EC */
452 }
453
454 hw_resource_list_t hw_resources;
455
456 if (!get_hw_resources(dev->parent_phone, &hw_resources)) {
457 printf(NAME ": pci_add_device failed to get hw resources for the device.\n");
458 delete_pci_bus_data(bus_data);
459 ipc_hangup(dev->parent_phone);
460 return EPARTY; /* FIXME: use another EC */
461 }
462
463 printf(NAME ": conf_addr = %x.\n", hw_resources.resources[0].res.io_range.address);
464
465 assert(hw_resources.count > 0);
466 assert(hw_resources.resources[0].type == IO_RANGE);
467 assert(hw_resources.resources[0].res.io_range.size == 8);
468
469 bus_data->conf_io_addr = (uint32_t)hw_resources.resources[0].res.io_range.address;
470
471 if (pio_enable((void *)bus_data->conf_io_addr, 8, &bus_data->conf_addr_port)) {
472 printf(NAME ": failed to enable configuration ports.\n");
473 delete_pci_bus_data(bus_data);
474 ipc_hangup(dev->parent_phone);
475 clean_hw_resource_list(&hw_resources);
476 return EADDRNOTAVAIL;
477 }
478 bus_data->conf_data_port = (char *)bus_data->conf_addr_port + 4;
479
480 dev->driver_data = bus_data;
481
482 // enumerate child devices
483 printf(NAME ": scanning the bus\n");
484 pci_bus_scan(dev, 0);
485
486 clean_hw_resource_list(&hw_resources);
487
488 return EOK;
489}
490
491static void pciintel_init()
492{
493 pci_child_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_child_res_iface;
494}
495
496int main(int argc, char *argv[])
497{
498 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
499 pciintel_init();
500 return driver_main(&pci_driver);
501}
502
503/**
504 * @}
505 */
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