source: mainline/uspace/drv/pciintel/pci.c@ 40a5d40

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 40a5d40 was 40a5d40, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Add EHCI stub and implement BIOS handover.
  • Property mode set to 100644
File size: 17.4 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <devman.h>
51#include <ipc/devman.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ipc/ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <libarch/ddi.h>
61#include <pci_dev_iface.h>
62
63#include "pci.h"
64
65#define NAME "pciintel"
66
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
72
73/** Obtain PCI bus soft-state from DDF device node */
74#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
75
76/** Obtain PCI bus soft-state from function soft-state */
77#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
78
79static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
80{
81 pci_fun_t *fun = PCI_FUN(fnode);
82
83 if (fun == NULL)
84 return NULL;
85 return &fun->hw_resources;
86}
87
88static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
89{
90 /* This is an old ugly way, copied from ne2000 driver */
91 assert(fnode);
92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data;
93
94 sysarg_t apic;
95 sysarg_t i8259;
96
97 int irc_phone = -1;
98 int irc_service = 0;
99
100 if ((sysinfo_get_value("apic", &apic) == EOK) && (apic)) {
101 irc_service = SERVICE_APIC;
102 } else if ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259)) {
103 irc_service = SERVICE_I8259;
104 }
105
106 if (irc_service == 0)
107 return false;
108
109 irc_phone = service_connect_blocking(irc_service, 0, 0);
110 if (irc_phone < 0)
111 return false;
112
113 size_t i;
114 for (i = 0; i < dev_data->hw_resources.count; i++) {
115 if (dev_data->hw_resources.resources[i].type == INTERRUPT) {
116 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq;
117 int rc = async_req_1_0(irc_phone, IRC_ENABLE_INTERRUPT, irq);
118 if (rc != EOK) {
119 async_hangup(irc_phone);
120 return false;
121 }
122 }
123 }
124
125 async_hangup(irc_phone);
126 return true;
127}
128
129static int pci_config_space_write_32(
130 ddf_fun_t *fun, uint32_t address, uint32_t data)
131{
132 if (address > 252)
133 return EINVAL;
134 pci_conf_write_32(PCI_FUN(fun), address, data);
135 return EOK;
136}
137
138static int pci_config_space_write_16(
139 ddf_fun_t *fun, uint32_t address, uint16_t data)
140{
141 if (address > 254)
142 return EINVAL;
143 pci_conf_write_16(PCI_FUN(fun), address, data);
144 return EOK;
145}
146
147static int pci_config_space_write_8(
148 ddf_fun_t *fun, uint32_t address, uint8_t data)
149{
150 if (address > 255)
151 return EINVAL;
152 pci_conf_write_8(PCI_FUN(fun), address, data);
153 return EOK;
154}
155
156static int pci_config_space_read_32(
157 ddf_fun_t *fun, uint32_t address, uint32_t *data)
158{
159 if (address > 252)
160 return EINVAL;
161 *data = pci_conf_read_32(PCI_FUN(fun), address);
162 return EOK;
163}
164
165static int pci_config_space_read_16(
166 ddf_fun_t *fun, uint32_t address, uint16_t *data)
167{
168 if (address > 254)
169 return EINVAL;
170 *data = pci_conf_read_16(PCI_FUN(fun), address);
171 return EOK;
172}
173
174static int pci_config_space_read_8(
175 ddf_fun_t *fun, uint32_t address, uint8_t *data)
176{
177 if (address > 255)
178 return EINVAL;
179 *data = pci_conf_read_8(PCI_FUN(fun), address);
180 return EOK;
181}
182
183static hw_res_ops_t pciintel_hw_res_ops = {
184 &pciintel_get_resources,
185 &pciintel_enable_interrupt
186};
187
188static pci_dev_iface_t pci_dev_ops = {
189 .config_space_read_8 = &pci_config_space_read_8,
190 .config_space_read_16 = &pci_config_space_read_16,
191 .config_space_read_32 = &pci_config_space_read_32,
192 .config_space_write_8 = &pci_config_space_write_8,
193 .config_space_write_16 = &pci_config_space_write_16,
194 .config_space_write_32 = &pci_config_space_write_32
195};
196
197static ddf_dev_ops_t pci_fun_ops = {
198 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
199 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
200};
201
202static int pci_add_device(ddf_dev_t *);
203
204/** PCI bus driver standard operations */
205static driver_ops_t pci_ops = {
206 .add_device = &pci_add_device
207};
208
209/** PCI bus driver structure */
210static driver_t pci_driver = {
211 .name = NAME,
212 .driver_ops = &pci_ops
213};
214
215static pci_bus_t *pci_bus_new(void)
216{
217 pci_bus_t *bus;
218
219 bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
220 if (bus == NULL)
221 return NULL;
222
223 fibril_mutex_initialize(&bus->conf_mutex);
224 return bus;
225}
226
227static void pci_bus_delete(pci_bus_t *bus)
228{
229 assert(bus != NULL);
230 free(bus);
231}
232
233static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
234{
235 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
236
237 fibril_mutex_lock(&bus->conf_mutex);
238
239 uint32_t conf_addr;
240 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
241 void *addr = bus->conf_data_port + (reg & 3);
242
243 pio_write_32(bus->conf_addr_port, conf_addr);
244
245 switch (len) {
246 case 1:
247 buf[0] = pio_read_8(addr);
248 break;
249 case 2:
250 ((uint16_t *) buf)[0] = pio_read_16(addr);
251 break;
252 case 4:
253 ((uint32_t *) buf)[0] = pio_read_32(addr);
254 break;
255 }
256
257 fibril_mutex_unlock(&bus->conf_mutex);
258}
259
260static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
261{
262 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
263
264 fibril_mutex_lock(&bus->conf_mutex);
265
266 uint32_t conf_addr;
267 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
268 void *addr = bus->conf_data_port + (reg & 3);
269
270 pio_write_32(bus->conf_addr_port, conf_addr);
271
272 switch (len) {
273 case 1:
274 pio_write_8(addr, buf[0]);
275 break;
276 case 2:
277 pio_write_16(addr, ((uint16_t *) buf)[0]);
278 break;
279 case 4:
280 pio_write_32(addr, ((uint32_t *) buf)[0]);
281 break;
282 }
283
284 fibril_mutex_unlock(&bus->conf_mutex);
285}
286
287uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
288{
289 uint8_t res;
290 pci_conf_read(fun, reg, &res, 1);
291 return res;
292}
293
294uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
295{
296 uint16_t res;
297 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
298 return res;
299}
300
301uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
302{
303 uint32_t res;
304 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
305 return res;
306}
307
308void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
309{
310 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
311}
312
313void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
314{
315 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
316}
317
318void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
319{
320 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
321}
322
323void pci_fun_create_match_ids(pci_fun_t *fun)
324{
325 char *match_id_str;
326 int rc;
327
328 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
329 fun->vendor_id, fun->device_id);
330
331 if (match_id_str == NULL) {
332 printf(NAME ": out of memory creating match ID.\n");
333 return;
334 }
335
336 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
337 if (rc != EOK) {
338 printf(NAME ": error adding match ID: %s\n",
339 str_error(rc));
340 }
341
342 /* TODO add more ids (with subsys ids, using class id etc.) */
343}
344
345void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
346 bool io)
347{
348 hw_resource_list_t *hw_res_list = &fun->hw_resources;
349 hw_resource_t *hw_resources = hw_res_list->resources;
350 size_t count = hw_res_list->count;
351
352 assert(hw_resources != NULL);
353 assert(count < PCI_MAX_HW_RES);
354
355 if (io) {
356 hw_resources[count].type = IO_RANGE;
357 hw_resources[count].res.io_range.address = range_addr;
358 hw_resources[count].res.io_range.size = range_size;
359 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
360 } else {
361 hw_resources[count].type = MEM_RANGE;
362 hw_resources[count].res.mem_range.address = range_addr;
363 hw_resources[count].res.mem_range.size = range_size;
364 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
365 }
366
367 hw_res_list->count++;
368}
369
370/** Read the base address register (BAR) of the device and if it contains valid
371 * address add it to the devices hw resource list.
372 *
373 * @param fun PCI function
374 * @param addr The address of the BAR in the PCI configuration address space of
375 * the device
376 * @return The addr the address of the BAR which should be read next
377 */
378int pci_read_bar(pci_fun_t *fun, int addr)
379{
380 /* Value of the BAR */
381 uint32_t val, mask;
382 /* IO space address */
383 bool io;
384 /* 64-bit wide address */
385 bool addrw64;
386
387 /* Size of the io or memory range specified by the BAR */
388 size_t range_size;
389 /* Beginning of the io or memory range specified by the BAR */
390 uint64_t range_addr;
391
392 /* Get the value of the BAR. */
393 val = pci_conf_read_32(fun, addr);
394
395#define IO_MASK (~0x3)
396#define MEM_MASK (~0xf)
397
398 io = (bool) (val & 1);
399 if (io) {
400 addrw64 = false;
401 mask = IO_MASK;
402 } else {
403 mask = MEM_MASK;
404 switch ((val >> 1) & 3) {
405 case 0:
406 addrw64 = false;
407 break;
408 case 2:
409 addrw64 = true;
410 break;
411 default:
412 /* reserved, go to the next BAR */
413 return addr + 4;
414 }
415 }
416
417 /* Get the address mask. */
418 pci_conf_write_32(fun, addr, 0xffffffff);
419 mask &= pci_conf_read_32(fun, addr);
420
421 /* Restore the original value. */
422 pci_conf_write_32(fun, addr, val);
423 val = pci_conf_read_32(fun, addr);
424
425 range_size = pci_bar_mask_to_size(mask);
426
427 if (addrw64) {
428 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
429 (val & 0xfffffff0);
430 } else {
431 range_addr = (val & 0xfffffff0);
432 }
433
434 if (range_addr != 0) {
435 printf(NAME ": function %s : ", fun->fnode->name);
436 printf("address = %" PRIx64, range_addr);
437 printf(", size = %x\n", (unsigned int) range_size);
438 }
439
440 pci_add_range(fun, range_addr, range_size, io);
441
442 if (addrw64)
443 return addr + 8;
444
445 return addr + 4;
446}
447
448void pci_add_interrupt(pci_fun_t *fun, int irq)
449{
450 hw_resource_list_t *hw_res_list = &fun->hw_resources;
451 hw_resource_t *hw_resources = hw_res_list->resources;
452 size_t count = hw_res_list->count;
453
454 assert(NULL != hw_resources);
455 assert(count < PCI_MAX_HW_RES);
456
457 hw_resources[count].type = INTERRUPT;
458 hw_resources[count].res.interrupt.irq = irq;
459
460 hw_res_list->count++;
461
462 printf(NAME ": function %s uses irq %x.\n", fun->fnode->name, irq);
463}
464
465void pci_read_interrupt(pci_fun_t *fun)
466{
467 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
468 if (irq != 0xff)
469 pci_add_interrupt(fun, irq);
470}
471
472/** Enumerate (recursively) and register the devices connected to a pci bus.
473 *
474 * @param bus Host-to-PCI bridge
475 * @param bus_num Bus number
476 */
477void pci_bus_scan(pci_bus_t *bus, int bus_num)
478{
479 ddf_fun_t *fnode;
480 pci_fun_t *fun;
481
482 int child_bus = 0;
483 int dnum, fnum;
484 bool multi;
485 uint8_t header_type;
486
487 fun = pci_fun_new(bus);
488
489 for (dnum = 0; dnum < 32; dnum++) {
490 multi = true;
491 for (fnum = 0; multi && fnum < 8; fnum++) {
492 pci_fun_init(fun, bus_num, dnum, fnum);
493 fun->vendor_id = pci_conf_read_16(fun,
494 PCI_VENDOR_ID);
495 fun->device_id = pci_conf_read_16(fun,
496 PCI_DEVICE_ID);
497 if (fun->vendor_id == 0xffff) {
498 /*
499 * The device is not present, go on scanning the
500 * bus.
501 */
502 if (fnum == 0)
503 break;
504 else
505 continue;
506 }
507
508 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
509 if (fnum == 0) {
510 /* Is the device multifunction? */
511 multi = header_type >> 7;
512 }
513 /* Clear the multifunction bit. */
514 header_type = header_type & 0x7F;
515
516 char *fun_name = pci_fun_create_name(fun);
517 if (fun_name == NULL) {
518 printf(NAME ": out of memory.\n");
519 return;
520 }
521
522 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
523 if (fnode == NULL) {
524 printf(NAME ": error creating function.\n");
525 return;
526 }
527
528 free(fun_name);
529 fun->fnode = fnode;
530
531 pci_alloc_resource_list(fun);
532 pci_read_bars(fun);
533 pci_read_interrupt(fun);
534
535 fnode->ops = &pci_fun_ops;
536 fnode->driver_data = fun;
537
538 printf(NAME ": adding new function %s.\n",
539 fnode->name);
540
541 pci_fun_create_match_ids(fun);
542
543 if (ddf_fun_bind(fnode) != EOK) {
544 pci_clean_resource_list(fun);
545 clean_match_ids(&fnode->match_ids);
546 free((char *) fnode->name);
547 fnode->name = NULL;
548 continue;
549 }
550
551 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
552 header_type == PCI_HEADER_TYPE_CARDBUS) {
553 child_bus = pci_conf_read_8(fun,
554 PCI_BRIDGE_SEC_BUS_NUM);
555 printf(NAME ": device is pci-to-pci bridge, "
556 "secondary bus number = %d.\n", bus_num);
557 if (child_bus > bus_num)
558 pci_bus_scan(bus, child_bus);
559 }
560
561 fun = pci_fun_new(bus);
562 }
563 }
564
565 if (fun->vendor_id == 0xffff) {
566 /* Free the auxiliary function structure. */
567 pci_fun_delete(fun);
568 }
569}
570
571static int pci_add_device(ddf_dev_t *dnode)
572{
573 pci_bus_t *bus = NULL;
574 ddf_fun_t *ctl = NULL;
575 bool got_res = false;
576 int rc;
577
578 printf(NAME ": pci_add_device\n");
579 dnode->parent_phone = -1;
580
581 bus = pci_bus_new();
582 if (bus == NULL) {
583 printf(NAME ": pci_add_device allocation failed.\n");
584 rc = ENOMEM;
585 goto fail;
586 }
587 bus->dnode = dnode;
588 dnode->driver_data = bus;
589
590 dnode->parent_phone = devman_parent_device_connect(dnode->handle,
591 IPC_FLAG_BLOCKING);
592 if (dnode->parent_phone < 0) {
593 printf(NAME ": pci_add_device failed to connect to the "
594 "parent's driver.\n");
595 rc = dnode->parent_phone;
596 goto fail;
597 }
598
599 hw_resource_list_t hw_resources;
600
601 rc = hw_res_get_resource_list(dnode->parent_phone, &hw_resources);
602 if (rc != EOK) {
603 printf(NAME ": pci_add_device failed to get hw resources for "
604 "the device.\n");
605 goto fail;
606 }
607 got_res = true;
608
609 printf(NAME ": conf_addr = %" PRIx64 ".\n",
610 hw_resources.resources[0].res.io_range.address);
611
612 assert(hw_resources.count > 0);
613 assert(hw_resources.resources[0].type == IO_RANGE);
614 assert(hw_resources.resources[0].res.io_range.size == 8);
615
616 bus->conf_io_addr =
617 (uint32_t) hw_resources.resources[0].res.io_range.address;
618
619 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
620 &bus->conf_addr_port)) {
621 printf(NAME ": failed to enable configuration ports.\n");
622 rc = EADDRNOTAVAIL;
623 goto fail;
624 }
625 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
626
627 /* Make the bus device more visible. It has no use yet. */
628 printf(NAME ": adding a 'ctl' function\n");
629
630 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
631 if (ctl == NULL) {
632 printf(NAME ": error creating control function.\n");
633 rc = ENOMEM;
634 goto fail;
635 }
636
637 rc = ddf_fun_bind(ctl);
638 if (rc != EOK) {
639 printf(NAME ": error binding control function.\n");
640 goto fail;
641 }
642
643 /* Enumerate functions. */
644 printf(NAME ": scanning the bus\n");
645 pci_bus_scan(bus, 0);
646
647 hw_res_clean_resource_list(&hw_resources);
648
649 return EOK;
650
651fail:
652 if (bus != NULL)
653 pci_bus_delete(bus);
654 if (dnode->parent_phone >= 0)
655 async_hangup(dnode->parent_phone);
656 if (got_res)
657 hw_res_clean_resource_list(&hw_resources);
658 if (ctl != NULL)
659 ddf_fun_destroy(ctl);
660
661 return rc;
662}
663
664static void pciintel_init(void)
665{
666 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
667 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
668}
669
670pci_fun_t *pci_fun_new(pci_bus_t *bus)
671{
672 pci_fun_t *fun;
673
674 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
675 if (fun == NULL)
676 return NULL;
677
678 fun->busptr = bus;
679 return fun;
680}
681
682void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
683{
684 fun->bus = bus;
685 fun->dev = dev;
686 fun->fn = fn;
687}
688
689void pci_fun_delete(pci_fun_t *fun)
690{
691 assert(fun != NULL);
692 hw_res_clean_resource_list(&fun->hw_resources);
693 free(fun);
694}
695
696char *pci_fun_create_name(pci_fun_t *fun)
697{
698 char *name = NULL;
699
700 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
701 fun->fn);
702 return name;
703}
704
705bool pci_alloc_resource_list(pci_fun_t *fun)
706{
707 fun->hw_resources.resources =
708 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
709 return fun->hw_resources.resources != NULL;
710}
711
712void pci_clean_resource_list(pci_fun_t *fun)
713{
714 if (fun->hw_resources.resources != NULL) {
715 free(fun->hw_resources.resources);
716 fun->hw_resources.resources = NULL;
717 }
718}
719
720/** Read the base address registers (BARs) of the function and add the addresses
721 * to its HW resource list.
722 *
723 * @param fun PCI function
724 */
725void pci_read_bars(pci_fun_t *fun)
726{
727 /*
728 * Position of the BAR in the PCI configuration address space of the
729 * device.
730 */
731 int addr = PCI_BASE_ADDR_0;
732
733 while (addr <= PCI_BASE_ADDR_5)
734 addr = pci_read_bar(fun, addr);
735}
736
737size_t pci_bar_mask_to_size(uint32_t mask)
738{
739 size_t size = mask & ~(mask - 1);
740 return size;
741}
742
743int main(int argc, char *argv[])
744{
745 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
746 pciintel_init();
747 return ddf_driver_main(&pci_driver);
748}
749
750/**
751 * @}
752 */
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