source: mainline/uspace/drv/pciintel/pci.c@ 0f31e2b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0f31e2b was 99e6bfb, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

Implement access to device config space
  • Property mode set to 100644
File size: 16.3 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <devman.h>
51#include <ipc/devman.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ipc/ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <libarch/ddi.h>
61#include <pci_dev_iface.h>
62
63#include "pci.h"
64
65#define NAME "pciintel"
66
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
72
73/** Obtain PCI bus soft-state from DDF device node */
74#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
75
76/** Obtain PCI bus soft-state from function soft-state */
77#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
78
79static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
80{
81 pci_fun_t *fun = PCI_FUN(fnode);
82
83 if (fun == NULL)
84 return NULL;
85 return &fun->hw_resources;
86}
87
88static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
89{
90 /* This is an old ugly way, copied from ne2000 driver */
91 assert(fnode);
92 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data;
93
94 sysarg_t apic;
95 sysarg_t i8259;
96 int irc_phone = -1;
97 int irc_service = 0;
98
99 if ((sysinfo_get_value("apic", &apic) == EOK) && (apic)) {
100 irc_service = SERVICE_APIC;
101 } else if ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259)) {
102 irc_service = SERVICE_I8259;
103 }
104
105 if (irc_service) {
106 while (irc_phone < 0)
107 irc_phone = service_connect_blocking(irc_service, 0, 0);
108 } else {
109 return false;
110 }
111
112 size_t i;
113 for (i = 0; i < dev_data->hw_resources.count; i++) {
114 if (dev_data->hw_resources.resources[i].type == INTERRUPT) {
115 int irq = dev_data->hw_resources.resources[i].res.interrupt.irq;
116 async_msg_1(irc_phone, IRC_ENABLE_INTERRUPT, irq);
117 }
118 }
119
120 async_hangup(irc_phone);
121 return true;
122}
123
124static int pci_config_space_write_16(ddf_fun_t *fun, uint32_t address, uint16_t data)
125{
126 if (address > 254)
127 return EINVAL;
128 pci_conf_write_16(PCI_FUN(fun), address, data);
129 return EOK;
130}
131
132
133static hw_res_ops_t pciintel_hw_res_ops = {
134 &pciintel_get_resources,
135 &pciintel_enable_interrupt
136};
137
138static pci_dev_iface_t pci_dev_ops = {
139 .config_space_read_8 = NULL,
140 .config_space_read_16 = NULL,
141 .config_space_read_32 = NULL,
142 .config_space_write_8 = NULL,
143 .config_space_write_16 = &pci_config_space_write_16,
144 .config_space_write_32 = NULL
145};
146
147static ddf_dev_ops_t pci_fun_ops = {
148 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
149 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
150};
151
152static int pci_add_device(ddf_dev_t *);
153
154/** PCI bus driver standard operations */
155static driver_ops_t pci_ops = {
156 .add_device = &pci_add_device
157};
158
159/** PCI bus driver structure */
160static driver_t pci_driver = {
161 .name = NAME,
162 .driver_ops = &pci_ops
163};
164
165static pci_bus_t *pci_bus_new(void)
166{
167 pci_bus_t *bus;
168
169 bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
170 if (bus == NULL)
171 return NULL;
172
173 fibril_mutex_initialize(&bus->conf_mutex);
174 return bus;
175}
176
177static void pci_bus_delete(pci_bus_t *bus)
178{
179 assert(bus != NULL);
180 free(bus);
181}
182
183static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
184{
185 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
186
187 fibril_mutex_lock(&bus->conf_mutex);
188
189 uint32_t conf_addr;
190 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
191 void *addr = bus->conf_data_port + (reg & 3);
192
193 pio_write_32(bus->conf_addr_port, conf_addr);
194
195 switch (len) {
196 case 1:
197 buf[0] = pio_read_8(addr);
198 break;
199 case 2:
200 ((uint16_t *) buf)[0] = pio_read_16(addr);
201 break;
202 case 4:
203 ((uint32_t *) buf)[0] = pio_read_32(addr);
204 break;
205 }
206
207 fibril_mutex_unlock(&bus->conf_mutex);
208}
209
210static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
211{
212 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
213
214 fibril_mutex_lock(&bus->conf_mutex);
215
216 uint32_t conf_addr;
217 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
218 void *addr = bus->conf_data_port + (reg & 3);
219
220 pio_write_32(bus->conf_addr_port, conf_addr);
221
222 switch (len) {
223 case 1:
224 pio_write_8(addr, buf[0]);
225 break;
226 case 2:
227 pio_write_16(addr, ((uint16_t *) buf)[0]);
228 break;
229 case 4:
230 pio_write_32(addr, ((uint32_t *) buf)[0]);
231 break;
232 }
233
234 fibril_mutex_unlock(&bus->conf_mutex);
235}
236
237uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
238{
239 uint8_t res;
240 pci_conf_read(fun, reg, &res, 1);
241 return res;
242}
243
244uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
245{
246 uint16_t res;
247 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
248 return res;
249}
250
251uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
252{
253 uint32_t res;
254 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
255 return res;
256}
257
258void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
259{
260 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
261}
262
263void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
264{
265 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
266}
267
268void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
269{
270 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
271}
272
273void pci_fun_create_match_ids(pci_fun_t *fun)
274{
275 char *match_id_str;
276 int rc;
277
278 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
279 fun->vendor_id, fun->device_id);
280
281 if (match_id_str == NULL) {
282 printf(NAME ": out of memory creating match ID.\n");
283 return;
284 }
285
286 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
287 if (rc != EOK) {
288 printf(NAME ": error adding match ID: %s\n",
289 str_error(rc));
290 }
291
292 /* TODO add more ids (with subsys ids, using class id etc.) */
293}
294
295void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
296 bool io)
297{
298 hw_resource_list_t *hw_res_list = &fun->hw_resources;
299 hw_resource_t *hw_resources = hw_res_list->resources;
300 size_t count = hw_res_list->count;
301
302 assert(hw_resources != NULL);
303 assert(count < PCI_MAX_HW_RES);
304
305 if (io) {
306 hw_resources[count].type = IO_RANGE;
307 hw_resources[count].res.io_range.address = range_addr;
308 hw_resources[count].res.io_range.size = range_size;
309 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
310 } else {
311 hw_resources[count].type = MEM_RANGE;
312 hw_resources[count].res.mem_range.address = range_addr;
313 hw_resources[count].res.mem_range.size = range_size;
314 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
315 }
316
317 hw_res_list->count++;
318}
319
320/** Read the base address register (BAR) of the device and if it contains valid
321 * address add it to the devices hw resource list.
322 *
323 * @param fun PCI function
324 * @param addr The address of the BAR in the PCI configuration address space of
325 * the device
326 * @return The addr the address of the BAR which should be read next
327 */
328int pci_read_bar(pci_fun_t *fun, int addr)
329{
330 /* Value of the BAR */
331 uint32_t val, mask;
332 /* IO space address */
333 bool io;
334 /* 64-bit wide address */
335 bool addrw64;
336
337 /* Size of the io or memory range specified by the BAR */
338 size_t range_size;
339 /* Beginning of the io or memory range specified by the BAR */
340 uint64_t range_addr;
341
342 /* Get the value of the BAR. */
343 val = pci_conf_read_32(fun, addr);
344
345#define IO_MASK (~0x3)
346#define MEM_MASK (~0xf)
347
348 io = (bool) (val & 1);
349 if (io) {
350 addrw64 = false;
351 mask = IO_MASK;
352 } else {
353 mask = MEM_MASK;
354 switch ((val >> 1) & 3) {
355 case 0:
356 addrw64 = false;
357 break;
358 case 2:
359 addrw64 = true;
360 break;
361 default:
362 /* reserved, go to the next BAR */
363 return addr + 4;
364 }
365 }
366
367 /* Get the address mask. */
368 pci_conf_write_32(fun, addr, 0xffffffff);
369 mask &= pci_conf_read_32(fun, addr);
370
371 /* Restore the original value. */
372 pci_conf_write_32(fun, addr, val);
373 val = pci_conf_read_32(fun, addr);
374
375 range_size = pci_bar_mask_to_size(mask);
376
377 if (addrw64) {
378 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
379 (val & 0xfffffff0);
380 } else {
381 range_addr = (val & 0xfffffff0);
382 }
383
384 if (range_addr != 0) {
385 printf(NAME ": function %s : ", fun->fnode->name);
386 printf("address = %" PRIx64, range_addr);
387 printf(", size = %x\n", (unsigned int) range_size);
388 }
389
390 pci_add_range(fun, range_addr, range_size, io);
391
392 if (addrw64)
393 return addr + 8;
394
395 return addr + 4;
396}
397
398void pci_add_interrupt(pci_fun_t *fun, int irq)
399{
400 hw_resource_list_t *hw_res_list = &fun->hw_resources;
401 hw_resource_t *hw_resources = hw_res_list->resources;
402 size_t count = hw_res_list->count;
403
404 assert(NULL != hw_resources);
405 assert(count < PCI_MAX_HW_RES);
406
407 hw_resources[count].type = INTERRUPT;
408 hw_resources[count].res.interrupt.irq = irq;
409
410 hw_res_list->count++;
411
412 printf(NAME ": function %s uses irq %x.\n", fun->fnode->name, irq);
413}
414
415void pci_read_interrupt(pci_fun_t *fun)
416{
417 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
418 if (irq != 0xff)
419 pci_add_interrupt(fun, irq);
420}
421
422/** Enumerate (recursively) and register the devices connected to a pci bus.
423 *
424 * @param bus Host-to-PCI bridge
425 * @param bus_num Bus number
426 */
427void pci_bus_scan(pci_bus_t *bus, int bus_num)
428{
429 ddf_fun_t *fnode;
430 pci_fun_t *fun;
431
432 int child_bus = 0;
433 int dnum, fnum;
434 bool multi;
435 uint8_t header_type;
436
437 fun = pci_fun_new(bus);
438
439 for (dnum = 0; dnum < 32; dnum++) {
440 multi = true;
441 for (fnum = 0; multi && fnum < 8; fnum++) {
442 pci_fun_init(fun, bus_num, dnum, fnum);
443 fun->vendor_id = pci_conf_read_16(fun,
444 PCI_VENDOR_ID);
445 fun->device_id = pci_conf_read_16(fun,
446 PCI_DEVICE_ID);
447 if (fun->vendor_id == 0xffff) {
448 /*
449 * The device is not present, go on scanning the
450 * bus.
451 */
452 if (fnum == 0)
453 break;
454 else
455 continue;
456 }
457
458 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
459 if (fnum == 0) {
460 /* Is the device multifunction? */
461 multi = header_type >> 7;
462 }
463 /* Clear the multifunction bit. */
464 header_type = header_type & 0x7F;
465
466 char *fun_name = pci_fun_create_name(fun);
467 if (fun_name == NULL) {
468 printf(NAME ": out of memory.\n");
469 return;
470 }
471
472 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
473 if (fnode == NULL) {
474 printf(NAME ": error creating function.\n");
475 return;
476 }
477
478 free(fun_name);
479 fun->fnode = fnode;
480
481 pci_alloc_resource_list(fun);
482 pci_read_bars(fun);
483 pci_read_interrupt(fun);
484
485 fnode->ops = &pci_fun_ops;
486 fnode->driver_data = fun;
487
488 printf(NAME ": adding new function %s.\n",
489 fnode->name);
490
491 pci_fun_create_match_ids(fun);
492
493 if (ddf_fun_bind(fnode) != EOK) {
494 pci_clean_resource_list(fun);
495 clean_match_ids(&fnode->match_ids);
496 free((char *) fnode->name);
497 fnode->name = NULL;
498 continue;
499 }
500
501 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
502 header_type == PCI_HEADER_TYPE_CARDBUS) {
503 child_bus = pci_conf_read_8(fun,
504 PCI_BRIDGE_SEC_BUS_NUM);
505 printf(NAME ": device is pci-to-pci bridge, "
506 "secondary bus number = %d.\n", bus_num);
507 if (child_bus > bus_num)
508 pci_bus_scan(bus, child_bus);
509 }
510
511 fun = pci_fun_new(bus);
512 }
513 }
514
515 if (fun->vendor_id == 0xffff) {
516 /* Free the auxiliary function structure. */
517 pci_fun_delete(fun);
518 }
519}
520
521static int pci_add_device(ddf_dev_t *dnode)
522{
523 pci_bus_t *bus = NULL;
524 ddf_fun_t *ctl = NULL;
525 bool got_res = false;
526 int rc;
527
528 printf(NAME ": pci_add_device\n");
529 dnode->parent_phone = -1;
530
531 bus = pci_bus_new();
532 if (bus == NULL) {
533 printf(NAME ": pci_add_device allocation failed.\n");
534 rc = ENOMEM;
535 goto fail;
536 }
537 bus->dnode = dnode;
538 dnode->driver_data = bus;
539
540 dnode->parent_phone = devman_parent_device_connect(dnode->handle,
541 IPC_FLAG_BLOCKING);
542 if (dnode->parent_phone < 0) {
543 printf(NAME ": pci_add_device failed to connect to the "
544 "parent's driver.\n");
545 rc = dnode->parent_phone;
546 goto fail;
547 }
548
549 hw_resource_list_t hw_resources;
550
551 rc = hw_res_get_resource_list(dnode->parent_phone, &hw_resources);
552 if (rc != EOK) {
553 printf(NAME ": pci_add_device failed to get hw resources for "
554 "the device.\n");
555 goto fail;
556 }
557 got_res = true;
558
559 printf(NAME ": conf_addr = %" PRIx64 ".\n",
560 hw_resources.resources[0].res.io_range.address);
561
562 assert(hw_resources.count > 0);
563 assert(hw_resources.resources[0].type == IO_RANGE);
564 assert(hw_resources.resources[0].res.io_range.size == 8);
565
566 bus->conf_io_addr =
567 (uint32_t) hw_resources.resources[0].res.io_range.address;
568
569 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
570 &bus->conf_addr_port)) {
571 printf(NAME ": failed to enable configuration ports.\n");
572 rc = EADDRNOTAVAIL;
573 goto fail;
574 }
575 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
576
577 /* Make the bus device more visible. It has no use yet. */
578 printf(NAME ": adding a 'ctl' function\n");
579
580 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
581 if (ctl == NULL) {
582 printf(NAME ": error creating control function.\n");
583 rc = ENOMEM;
584 goto fail;
585 }
586
587 rc = ddf_fun_bind(ctl);
588 if (rc != EOK) {
589 printf(NAME ": error binding control function.\n");
590 goto fail;
591 }
592
593 /* Enumerate functions. */
594 printf(NAME ": scanning the bus\n");
595 pci_bus_scan(bus, 0);
596
597 hw_res_clean_resource_list(&hw_resources);
598
599 return EOK;
600
601fail:
602 if (bus != NULL)
603 pci_bus_delete(bus);
604 if (dnode->parent_phone >= 0)
605 async_hangup(dnode->parent_phone);
606 if (got_res)
607 hw_res_clean_resource_list(&hw_resources);
608 if (ctl != NULL)
609 ddf_fun_destroy(ctl);
610
611 return rc;
612}
613
614static void pciintel_init(void)
615{
616 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
617 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
618}
619
620pci_fun_t *pci_fun_new(pci_bus_t *bus)
621{
622 pci_fun_t *fun;
623
624 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
625 if (fun == NULL)
626 return NULL;
627
628 fun->busptr = bus;
629 return fun;
630}
631
632void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
633{
634 fun->bus = bus;
635 fun->dev = dev;
636 fun->fn = fn;
637}
638
639void pci_fun_delete(pci_fun_t *fun)
640{
641 assert(fun != NULL);
642 hw_res_clean_resource_list(&fun->hw_resources);
643 free(fun);
644}
645
646char *pci_fun_create_name(pci_fun_t *fun)
647{
648 char *name = NULL;
649
650 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
651 fun->fn);
652 return name;
653}
654
655bool pci_alloc_resource_list(pci_fun_t *fun)
656{
657 fun->hw_resources.resources =
658 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
659 return fun->hw_resources.resources != NULL;
660}
661
662void pci_clean_resource_list(pci_fun_t *fun)
663{
664 if (fun->hw_resources.resources != NULL) {
665 free(fun->hw_resources.resources);
666 fun->hw_resources.resources = NULL;
667 }
668}
669
670/** Read the base address registers (BARs) of the function and add the addresses
671 * to its HW resource list.
672 *
673 * @param fun PCI function
674 */
675void pci_read_bars(pci_fun_t *fun)
676{
677 /*
678 * Position of the BAR in the PCI configuration address space of the
679 * device.
680 */
681 int addr = PCI_BASE_ADDR_0;
682
683 while (addr <= PCI_BASE_ADDR_5)
684 addr = pci_read_bar(fun, addr);
685}
686
687size_t pci_bar_mask_to_size(uint32_t mask)
688{
689 size_t size = mask & ~(mask - 1);
690 return size;
691}
692
693int main(int argc, char *argv[])
694{
695 printf(NAME ": HelenOS pci bus driver (intel method 1).\n");
696 pciintel_init();
697 return ddf_driver_main(&pci_driver);
698}
699
700/**
701 * @}
702 */
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