source: mainline/uspace/drv/pciintel/pci.c@ 5b72635

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5b72635 was ebcb05a, checked in by Jiri Svoboda <jiri@…>, 15 years ago

Logging functions should append newline automatically. Since one has no
choice but to end log message with a newline, there is no need to do it
manually in every invocation.
  • Property mode set to 100644
File size: 14.8 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <ddf/log.h>
51#include <devman.h>
52#include <ipc/devman.h>
53#include <ipc/dev_iface.h>
54#include <ops/hw_res.h>
55#include <device/hw_res.h>
56#include <ddi.h>
57#include <libarch/ddi.h>
58
59#include "pci.h"
60
61#define NAME "pciintel"
62
63#define CONF_ADDR(bus, dev, fn, reg) \
64 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
65
66/** Obtain PCI function soft-state from DDF function node */
67#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
68
69/** Obtain PCI bus soft-state from DDF device node */
70#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
71
72/** Obtain PCI bus soft-state from function soft-state */
73#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
74
75static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
76{
77 pci_fun_t *fun = PCI_FUN(fnode);
78
79 if (fun == NULL)
80 return NULL;
81 return &fun->hw_resources;
82}
83
84static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
85{
86 /* TODO */
87
88 return false;
89}
90
91static hw_res_ops_t pciintel_hw_res_ops = {
92 &pciintel_get_resources,
93 &pciintel_enable_interrupt
94};
95
96static ddf_dev_ops_t pci_fun_ops;
97
98static int pci_add_device(ddf_dev_t *);
99
100/** PCI bus driver standard operations */
101static driver_ops_t pci_ops = {
102 .add_device = &pci_add_device
103};
104
105/** PCI bus driver structure */
106static driver_t pci_driver = {
107 .name = NAME,
108 .driver_ops = &pci_ops
109};
110
111static pci_bus_t *pci_bus_new(void)
112{
113 pci_bus_t *bus;
114
115 bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
116 if (bus == NULL)
117 return NULL;
118
119 fibril_mutex_initialize(&bus->conf_mutex);
120 return bus;
121}
122
123static void pci_bus_delete(pci_bus_t *bus)
124{
125 assert(bus != NULL);
126 free(bus);
127}
128
129static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
130{
131 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
132
133 fibril_mutex_lock(&bus->conf_mutex);
134
135 uint32_t conf_addr;
136 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
137 void *addr = bus->conf_data_port + (reg & 3);
138
139 pio_write_32(bus->conf_addr_port, conf_addr);
140
141 switch (len) {
142 case 1:
143 buf[0] = pio_read_8(addr);
144 break;
145 case 2:
146 ((uint16_t *) buf)[0] = pio_read_16(addr);
147 break;
148 case 4:
149 ((uint32_t *) buf)[0] = pio_read_32(addr);
150 break;
151 }
152
153 fibril_mutex_unlock(&bus->conf_mutex);
154}
155
156static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
157{
158 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
159
160 fibril_mutex_lock(&bus->conf_mutex);
161
162 uint32_t conf_addr;
163 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
164 void *addr = bus->conf_data_port + (reg & 3);
165
166 pio_write_32(bus->conf_addr_port, conf_addr);
167
168 switch (len) {
169 case 1:
170 pio_write_8(addr, buf[0]);
171 break;
172 case 2:
173 pio_write_16(addr, ((uint16_t *) buf)[0]);
174 break;
175 case 4:
176 pio_write_32(addr, ((uint32_t *) buf)[0]);
177 break;
178 }
179
180 fibril_mutex_unlock(&bus->conf_mutex);
181}
182
183uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
184{
185 uint8_t res;
186 pci_conf_read(fun, reg, &res, 1);
187 return res;
188}
189
190uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
191{
192 uint16_t res;
193 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
194 return res;
195}
196
197uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
198{
199 uint32_t res;
200 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
201 return res;
202}
203
204void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
205{
206 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
207}
208
209void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
210{
211 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
212}
213
214void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
215{
216 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
217}
218
219void pci_fun_create_match_ids(pci_fun_t *fun)
220{
221 char *match_id_str;
222 int rc;
223
224 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
225 fun->vendor_id, fun->device_id);
226
227 if (match_id_str == NULL) {
228 ddf_msg(LVL_ERROR, "Out of memory creating match ID.");
229 return;
230 }
231
232 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
233 if (rc != EOK) {
234 ddf_msg(LVL_ERROR, "Failed adding match ID: %s",
235 str_error(rc));
236 }
237
238 /* TODO add more ids (with subsys ids, using class id etc.) */
239}
240
241void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
242 bool io)
243{
244 hw_resource_list_t *hw_res_list = &fun->hw_resources;
245 hw_resource_t *hw_resources = hw_res_list->resources;
246 size_t count = hw_res_list->count;
247
248 assert(hw_resources != NULL);
249 assert(count < PCI_MAX_HW_RES);
250
251 if (io) {
252 hw_resources[count].type = IO_RANGE;
253 hw_resources[count].res.io_range.address = range_addr;
254 hw_resources[count].res.io_range.size = range_size;
255 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
256 } else {
257 hw_resources[count].type = MEM_RANGE;
258 hw_resources[count].res.mem_range.address = range_addr;
259 hw_resources[count].res.mem_range.size = range_size;
260 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
261 }
262
263 hw_res_list->count++;
264}
265
266/** Read the base address register (BAR) of the device and if it contains valid
267 * address add it to the devices hw resource list.
268 *
269 * @param fun PCI function
270 * @param addr The address of the BAR in the PCI configuration address space of
271 * the device
272 * @return The addr the address of the BAR which should be read next
273 */
274int pci_read_bar(pci_fun_t *fun, int addr)
275{
276 /* Value of the BAR */
277 uint32_t val, mask;
278 /* IO space address */
279 bool io;
280 /* 64-bit wide address */
281 bool addrw64;
282
283 /* Size of the io or memory range specified by the BAR */
284 size_t range_size;
285 /* Beginning of the io or memory range specified by the BAR */
286 uint64_t range_addr;
287
288 /* Get the value of the BAR. */
289 val = pci_conf_read_32(fun, addr);
290
291 io = (bool) (val & 1);
292 if (io) {
293 addrw64 = false;
294 } else {
295 switch ((val >> 1) & 3) {
296 case 0:
297 addrw64 = false;
298 break;
299 case 2:
300 addrw64 = true;
301 break;
302 default:
303 /* reserved, go to the next BAR */
304 return addr + 4;
305 }
306 }
307
308 /* Get the address mask. */
309 pci_conf_write_32(fun, addr, 0xffffffff);
310 mask = pci_conf_read_32(fun, addr);
311
312 /* Restore the original value. */
313 pci_conf_write_32(fun, addr, val);
314 val = pci_conf_read_32(fun, addr);
315
316 range_size = pci_bar_mask_to_size(mask);
317
318 if (addrw64) {
319 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
320 (val & 0xfffffff0);
321 } else {
322 range_addr = (val & 0xfffffff0);
323 }
324
325 if (range_addr != 0) {
326 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
327 ", size = %x", fun->fnode->name, range_addr,
328 (unsigned int) range_size);
329 }
330
331 pci_add_range(fun, range_addr, range_size, io);
332
333 if (addrw64)
334 return addr + 8;
335
336 return addr + 4;
337}
338
339void pci_add_interrupt(pci_fun_t *fun, int irq)
340{
341 hw_resource_list_t *hw_res_list = &fun->hw_resources;
342 hw_resource_t *hw_resources = hw_res_list->resources;
343 size_t count = hw_res_list->count;
344
345 assert(NULL != hw_resources);
346 assert(count < PCI_MAX_HW_RES);
347
348 hw_resources[count].type = INTERRUPT;
349 hw_resources[count].res.interrupt.irq = irq;
350
351 hw_res_list->count++;
352
353 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", fun->fnode->name, irq);
354}
355
356void pci_read_interrupt(pci_fun_t *fun)
357{
358 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
359 if (irq != 0xff)
360 pci_add_interrupt(fun, irq);
361}
362
363/** Enumerate (recursively) and register the devices connected to a pci bus.
364 *
365 * @param bus Host-to-PCI bridge
366 * @param bus_num Bus number
367 */
368void pci_bus_scan(pci_bus_t *bus, int bus_num)
369{
370 ddf_fun_t *fnode;
371 pci_fun_t *fun;
372
373 int child_bus = 0;
374 int dnum, fnum;
375 bool multi;
376 uint8_t header_type;
377
378 fun = pci_fun_new(bus);
379
380 for (dnum = 0; dnum < 32; dnum++) {
381 multi = true;
382 for (fnum = 0; multi && fnum < 8; fnum++) {
383 pci_fun_init(fun, bus_num, dnum, fnum);
384 fun->vendor_id = pci_conf_read_16(fun,
385 PCI_VENDOR_ID);
386 fun->device_id = pci_conf_read_16(fun,
387 PCI_DEVICE_ID);
388 if (fun->vendor_id == 0xffff) {
389 /*
390 * The device is not present, go on scanning the
391 * bus.
392 */
393 if (fnum == 0)
394 break;
395 else
396 continue;
397 }
398
399 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
400 if (fnum == 0) {
401 /* Is the device multifunction? */
402 multi = header_type >> 7;
403 }
404 /* Clear the multifunction bit. */
405 header_type = header_type & 0x7F;
406
407 char *fun_name = pci_fun_create_name(fun);
408 if (fun_name == NULL) {
409 ddf_msg(LVL_ERROR, "Out of memory.");
410 return;
411 }
412
413 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
414 if (fnode == NULL) {
415 ddf_msg(LVL_ERROR, "Failed creating function.");
416 return;
417 }
418
419 free(fun_name);
420 fun->fnode = fnode;
421
422 pci_alloc_resource_list(fun);
423 pci_read_bars(fun);
424 pci_read_interrupt(fun);
425
426 fnode->ops = &pci_fun_ops;
427 fnode->driver_data = fun;
428
429 ddf_msg(LVL_DEBUG, "Adding new function %s.",
430 fnode->name);
431
432 pci_fun_create_match_ids(fun);
433
434 if (ddf_fun_bind(fnode) != EOK) {
435 pci_clean_resource_list(fun);
436 clean_match_ids(&fnode->match_ids);
437 free((char *) fnode->name);
438 fnode->name = NULL;
439 continue;
440 }
441
442 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
443 header_type == PCI_HEADER_TYPE_CARDBUS) {
444 child_bus = pci_conf_read_8(fun,
445 PCI_BRIDGE_SEC_BUS_NUM);
446 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
447 "bridge, secondary bus number = %d.",
448 bus_num);
449 if (child_bus > bus_num)
450 pci_bus_scan(bus, child_bus);
451 }
452
453 fun = pci_fun_new(bus);
454 }
455 }
456
457 if (fun->vendor_id == 0xffff) {
458 /* Free the auxiliary function structure. */
459 pci_fun_delete(fun);
460 }
461}
462
463static int pci_add_device(ddf_dev_t *dnode)
464{
465 pci_bus_t *bus = NULL;
466 ddf_fun_t *ctl = NULL;
467 bool got_res = false;
468 int rc;
469
470 ddf_msg(LVL_DEBUG, "pci_add_device");
471 dnode->parent_phone = -1;
472
473 bus = pci_bus_new();
474 if (bus == NULL) {
475 ddf_msg(LVL_ERROR, "pci_add_device allocation failed.");
476 rc = ENOMEM;
477 goto fail;
478 }
479 bus->dnode = dnode;
480 dnode->driver_data = bus;
481
482 dnode->parent_phone = devman_parent_device_connect(dnode->handle,
483 IPC_FLAG_BLOCKING);
484 if (dnode->parent_phone < 0) {
485 ddf_msg(LVL_ERROR, "pci_add_device failed to connect to the "
486 "parent's driver.");
487 rc = dnode->parent_phone;
488 goto fail;
489 }
490
491 hw_resource_list_t hw_resources;
492
493 rc = hw_res_get_resource_list(dnode->parent_phone, &hw_resources);
494 if (rc != EOK) {
495 ddf_msg(LVL_ERROR, "pci_add_device failed to get hw resources "
496 "for the device.");
497 goto fail;
498 }
499 got_res = true;
500
501 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
502 hw_resources.resources[0].res.io_range.address);
503
504 assert(hw_resources.count > 0);
505 assert(hw_resources.resources[0].type == IO_RANGE);
506 assert(hw_resources.resources[0].res.io_range.size == 8);
507
508 bus->conf_io_addr =
509 (uint32_t) hw_resources.resources[0].res.io_range.address;
510
511 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
512 &bus->conf_addr_port)) {
513 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
514 rc = EADDRNOTAVAIL;
515 goto fail;
516 }
517 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
518
519 /* Make the bus device more visible. It has no use yet. */
520 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
521
522 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
523 if (ctl == NULL) {
524 ddf_msg(LVL_ERROR, "Failed creating control function.");
525 rc = ENOMEM;
526 goto fail;
527 }
528
529 rc = ddf_fun_bind(ctl);
530 if (rc != EOK) {
531 ddf_msg(LVL_ERROR, "Failed binding control function.");
532 goto fail;
533 }
534
535 /* Enumerate functions. */
536 ddf_msg(LVL_DEBUG, "Scanning the bus");
537 pci_bus_scan(bus, 0);
538
539 hw_res_clean_resource_list(&hw_resources);
540
541 return EOK;
542
543fail:
544 if (bus != NULL)
545 pci_bus_delete(bus);
546 if (dnode->parent_phone >= 0)
547 async_hangup(dnode->parent_phone);
548 if (got_res)
549 hw_res_clean_resource_list(&hw_resources);
550 if (ctl != NULL)
551 ddf_fun_destroy(ctl);
552
553 return rc;
554}
555
556static void pciintel_init(void)
557{
558 ddf_log_init(NAME, LVL_ERROR);
559 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
560}
561
562pci_fun_t *pci_fun_new(pci_bus_t *bus)
563{
564 pci_fun_t *fun;
565
566 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
567 if (fun == NULL)
568 return NULL;
569
570 fun->busptr = bus;
571 return fun;
572}
573
574void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
575{
576 fun->bus = bus;
577 fun->dev = dev;
578 fun->fn = fn;
579}
580
581void pci_fun_delete(pci_fun_t *fun)
582{
583 assert(fun != NULL);
584 hw_res_clean_resource_list(&fun->hw_resources);
585 free(fun);
586}
587
588char *pci_fun_create_name(pci_fun_t *fun)
589{
590 char *name = NULL;
591
592 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
593 fun->fn);
594 return name;
595}
596
597bool pci_alloc_resource_list(pci_fun_t *fun)
598{
599 fun->hw_resources.resources =
600 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
601 return fun->hw_resources.resources != NULL;
602}
603
604void pci_clean_resource_list(pci_fun_t *fun)
605{
606 if (fun->hw_resources.resources != NULL) {
607 free(fun->hw_resources.resources);
608 fun->hw_resources.resources = NULL;
609 }
610}
611
612/** Read the base address registers (BARs) of the function and add the addresses
613 * to its HW resource list.
614 *
615 * @param fun PCI function
616 */
617void pci_read_bars(pci_fun_t *fun)
618{
619 /*
620 * Position of the BAR in the PCI configuration address space of the
621 * device.
622 */
623 int addr = PCI_BASE_ADDR_0;
624
625 while (addr <= PCI_BASE_ADDR_5)
626 addr = pci_read_bar(fun, addr);
627}
628
629size_t pci_bar_mask_to_size(uint32_t mask)
630{
631 return ((mask & 0xfffffff0) ^ 0xffffffff) + 1;
632}
633
634int main(int argc, char *argv[])
635{
636 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
637 pciintel_init();
638 return ddf_driver_main(&pci_driver);
639}
640
641/**
642 * @}
643 */
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