source: mainline/uspace/drv/ohci/ohci_regs.h@ 2bf8f8c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2bf8f8c was e7bc999, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Add interrupt support

Fix register structure
Interrupts disabled as there is no way to access mm registers in the handler

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohcihc
30 * @{
31 */
32/** @file
33 * @brief OHCI host controller register structure
34 */
35#ifndef DRV_OHCI_OHCI_REGS_H
36#define DRV_OHCI_OHCI_REGS_H
37#include <stdint.h>
38
39typedef struct ohci_regs
40{
41 volatile uint32_t revision;
42 volatile uint32_t control;
43 volatile uint32_t command_status;
44 volatile uint32_t interrupt_status;
45 volatile uint32_t interupt_enable;
46#define IE_SO (1 << 0)
47#define IE_WDH (1 << 1)
48#define IE_SF (1 << 2)
49#define IE_RD (1 << 3)
50#define IE_UE (1 << 4)
51#define IE_FNO (1 << 5)
52#define IE_RHSC (1 << 6)
53#define IE_OC (1 << 30)
54#define IE_MIE (1 << 31)
55
56 volatile uint32_t interrupt_disable;
57 volatile uint32_t hcca;
58 volatile uint32_t period_corrent;
59 volatile uint32_t control_head;
60 volatile uint32_t control_current;
61 volatile uint32_t bulk_head;
62 volatile uint32_t bulk_current;
63 volatile uint32_t done_head;
64 volatile uint32_t fm_interval;
65 volatile uint32_t fm_remaining;
66 volatile uint32_t fm_number;
67 volatile uint32_t periodic_start;
68 volatile uint32_t ls_threshold;
69 volatile uint32_t rh_desc_a;
70 volatile uint32_t rh_desc_b;
71 volatile uint32_t rh_status;
72 volatile uint32_t rh_port_status[];
73} __attribute__((packed)) ohci_regs_t;
74#endif
75/**
76 * @}
77 */
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