| 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup drvusbohcihc
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| 29 | * @{
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| 30 | */
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| 31 | /** @file
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| 32 | * @brief OHCI host controller register structure
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| 33 | */
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| 34 | #ifndef DRV_OHCI_OHCI_REGS_H
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| 35 | #define DRV_OHCI_OHCI_REGS_H
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| 36 | #include <stdint.h>
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| 37 |
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| 38 | typedef struct ohci_regs
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| 39 | {
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| 40 | const volatile uint32_t revision;
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| 41 | volatile uint32_t control;
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| 42 | #define C_CSBR_MASK (0x3) /* Control-bulk service ratio */
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| 43 | #define C_CSBR_1_1 (0x0)
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| 44 | #define C_CSBR_1_2 (0x1)
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| 45 | #define C_CSBR_1_3 (0x2)
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| 46 | #define C_CSBR_1_4 (0x3)
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| 47 | #define C_CSBR_SHIFT (0)
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| 48 |
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| 49 | #define C_PLE (1 << 2) /* Periodic list enable */
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| 50 | #define C_IE (1 << 3) /* Isochronous enable */
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| 51 | #define C_CLE (1 << 4) /* Control list enable */
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| 52 | #define C_BLE (1 << 5) /* Bulk list enable */
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| 53 |
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| 54 | #define C_HCFS_MASK (0x3) /* Host controller functional state */
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| 55 | #define C_HCFS_RESET (0x0)
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| 56 | #define C_HCFS_RESUME (0x1)
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| 57 | #define C_HCFS_OPERATIONAL (0x2)
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| 58 | #define C_HCFS_SUSPEND (0x3)
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| 59 | #define C_HCFS_SHIFT (6)
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| 60 |
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| 61 | #define C_IR (1 << 8) /* Interrupt routing, make sure it's 0 */
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| 62 | #define C_RWC (1 << 9) /* Remote wakeup connected, host specific */
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| 63 | #define C_RWE (1 << 10) /* Remote wakeup enable */
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| 64 |
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| 65 | volatile uint32_t command_status;
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| 66 | #define CS_HCR (1 << 0) /* Host controller reset */
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| 67 | #define CS_CLF (1 << 1) /* Control list filled */
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| 68 | #define CS_BLF (1 << 2) /* Bulk list filled */
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| 69 | #define CS_OCR (1 << 3) /* Ownership change request */
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| 70 | #define CS_SOC_MASK (0x3) /* Scheduling overrun count */
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| 71 | #define CS_SOC_SHIFT (16)
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| 72 |
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| 73 | /** Interupt enable/disable/status,
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| 74 | * reads give the same value,
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| 75 | * writing causes enable/disable,
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| 76 | * status is write-clean (writing 1 clears the bit*/
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| 77 | volatile uint32_t interrupt_status;
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| 78 | volatile uint32_t interrupt_enable;
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| 79 | volatile uint32_t interrupt_disable;
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| 80 | #define I_SO (1 << 0) /* Scheduling overrun */
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| 81 | #define I_WDH (1 << 1) /* Done head write-back */
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| 82 | #define I_SF (1 << 2) /* Start of frame */
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| 83 | #define I_RD (1 << 3) /* Resume detect */
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| 84 | #define I_UE (1 << 4) /* Unrecoverable error */
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| 85 | #define I_FNO (1 << 5) /* Frame number overflow */
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| 86 | #define I_RHSC (1 << 6) /* Root hub status change */
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| 87 | #define I_OC (1 << 30) /* Ownership change */
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| 88 | #define I_MI (1 << 31) /* Master interrupt (all/any interrupts) */
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| 89 |
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| 90 | /** HCCA pointer (see hw_struct hcca.h) */
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| 91 | volatile uint32_t hcca;
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| 92 | #define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
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| 93 |
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| 94 | /** Currently executed periodic endpoint */
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| 95 | const volatile uint32_t periodic_current;
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| 96 |
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| 97 | /** The first control endpoint */
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| 98 | volatile uint32_t control_head;
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| 99 |
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| 100 | /** Currently executed control endpoint */
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| 101 | volatile uint32_t control_current;
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| 102 |
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| 103 | /** The first bulk endpoint */
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| 104 | volatile uint32_t bulk_head;
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| 105 |
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| 106 | /** Currently executed bulk endpoint */
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| 107 | volatile uint32_t bulk_current;
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| 108 |
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| 109 | /** Done TD list, this value is periodically written to HCCA */
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| 110 | const volatile uint32_t done_head;
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| 111 |
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| 112 | /** Frame time and max packet size for all transfers */
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| 113 | volatile uint32_t fm_interval;
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| 114 | #define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
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| 115 | #define FMI_FI_SHIFT (0)
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| 116 | #define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
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| 117 | #define FMI_FSMPS_SHIFT (16)
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| 118 | #define FMI_TOGGLE_FLAG (1 << 31)
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| 119 |
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| 120 | /** Bit times remaining in current frame */
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| 121 | const volatile uint32_t fm_remaining;
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| 122 | #define FMR_FR_MASK FMI_FI_MASK
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| 123 | #define FMR_FR_SHIFT FMI_FI_SHIFT
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| 124 | #define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
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| 125 |
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| 126 | /** Frame number */
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| 127 | const volatile uint32_t fm_number;
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| 128 | #define FMN_NUMBER_MASK (0xffff)
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| 129 |
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| 130 | /** Remaining bit time in frame to start periodic transfers */
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| 131 | volatile uint32_t periodic_start;
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| 132 | #define PS_PS_MASK (0x3fff) /* bit time when periodic get priority (0x3e67) */
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| 133 |
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| 134 | /** Threshold for starting LS transaction */
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| 135 | volatile uint32_t ls_threshold;
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| 136 | #define LST_LST_MASK (0x7fff)
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| 137 |
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| 138 | /** The first root hub control register */
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| 139 | volatile uint32_t rh_desc_a;
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| 140 | #define RHDA_NDS_MASK (0xff) /* Number of downstream ports, max 15 */
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| 141 | #define RHDA_NDS_SHIFT (0)
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| 142 | #define RHDA_PSM_FLAG (1 << 8) /* Power switching mode: 0-global, 1-per port*/
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| 143 | #define RHDA_NPS_FLAG (1 << 9) /* No power switch: 1-power on, 0-use PSM*/
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| 144 | #define RHDA_DT_FLAG (1 << 10) /* 1-Compound device, must be 0 */
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| 145 | #define RHDA_OCPM_FLAG (1 << 11) /* Over-current mode: 0-global, 1-per port */
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| 146 | #define RHDA_NOCP (1 << 12) /* OC control: 0-use OCPM, 1-OC off */
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| 147 | #define RHDA_POTPGT_MASK (0xff) /* Power on to power good time */
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| 148 | #define RHDA_POTPGT_SHIFT (24)
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| 149 |
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| 150 | /** The other root hub control register */
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| 151 | volatile uint32_t rh_desc_b;
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| 152 | #define RHDB_DR_MASK (0xffff) /* Device removable mask */
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| 153 | #define RHDB_DR_SHIFT (0)
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| 154 | #define RHDB_PCC_MASK (0xffff) /* Power control mask */
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| 155 | #define RHDB_PCC_SHIFT (16)
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| 156 |
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| 157 | /* Port device removable status */
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| 158 | #define RHDB_DR_FLAG(port) (((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
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| 159 | /* Port power control status: 1-per port power control, 0-global power switch */
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| 160 | #define RHDB_PPC_FLAG(port) (((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
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| 161 |
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| 162 | /** Root hub status register */
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| 163 | volatile uint32_t rh_status;
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| 164 | #define RHS_LPS_FLAG (1 << 0)/* read: 0,
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| 165 | * write: 0-no effect,
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| 166 | * 1-turn off port power for ports
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| 167 | * specified in PPCM(RHDB), or all ports,
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| 168 | * if power is set globally */
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| 169 | #define RHS_CLEAR_PORT_POWER RHS_LPS_FLAG /* synonym for the above */
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| 170 | #define RHS_OCI_FLAG (1 << 1)/* Over-current indicator, if per-port: 0 */
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| 171 | #define RHS_DRWE_FLAG (1 << 15)/* read: 0-connect status change does not wake HC
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| 172 | * 1-connect status change wakes HC
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| 173 | * write: 1-set DRWE, 0-no effect */
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| 174 | #define RHS_SET_DRWE RHS_DRWE_FLAG
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| 175 | #define RHS_LPSC_FLAG (1 << 16)/* read: 0,
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| 176 | * write: 0-no effect
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| 177 | * 1-turn on port power for ports
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| 178 | * specified in PPCM(RHDB), or all ports,
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| 179 | * if power is set globally */
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| 180 | #define RHS_SET_PORT_POWER RHS_LPSC_FLAG /* synonym for the above */
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| 181 | #define RHS_OCIC_FLAG (1 << 17)/* Over-current indicator change */
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| 182 | #define RHS_CLEAR_DRWE (1 << 31)
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| 183 |
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| 184 | /** Root hub per port status */
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| 185 | volatile uint32_t rh_port_status[];
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| 186 | #define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
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| 187 | * w: 1-clear port enable, 0-nothing */
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| 188 | #define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
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| 189 | #define RHPS_PES_FLAG (1 << 1) /* r: port enable status
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| 190 | * w: 1-set port enable, 0-nothing */
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| 191 | #define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
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| 192 | #define RHPS_PSS_FLAG (1 << 2) /* r: port suspend status
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| 193 | * w: 1-set port suspend, 0-nothing */
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| 194 | #define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
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| 195 | #define RHPS_POCI_FLAG (1 << 3) /* r: port over-current (if reports are per-port
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| 196 | * w: 1-clear port suspend (start resume
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| 197 | * if suspened)
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| 198 | * 0-nothing */
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| 199 | #define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
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| 200 | #define RHPS_PRS_FLAG (1 << 4) /* r: port reset status
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| 201 | * w: 1-set port reset, 0-nothing */
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| 202 | #define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
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| 203 | #define RHPS_PPS_FLAG (1 << 8) /* r: port power status
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| 204 | * w: 1-set port power, 0-nothing */
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| 205 | #define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
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| 206 | #define RHPS_LSDA_FLAG (1 << 9) /* r: low speed device attached
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| 207 | * w: 1-clear port power, 0-nothing */
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| 208 | #define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
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| 209 | #define RHPS_CSC_FLAG (1 << 16) /* connect status change Write-Clean */
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| 210 | #define RHPS_PESC_FLAG (1 << 17) /* port enable status change WC */
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| 211 | #define RHPS_PSSC_FLAG (1 << 18) /* port suspend status change WC */
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| 212 | #define RHPS_OCIC_FLAG (1 << 19) /* port over-current change WC */
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| 213 | #define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
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| 214 | #define RHPS_CHANGE_WC_MASK 0x1f0000
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| 215 | } __attribute__((packed)) ohci_regs_t;
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| 216 | #endif
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| 217 | /**
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| 218 | * @}
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| 219 | */
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