source: mainline/uspace/drv/ohci/hc.c@ 76ef94e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 76ef94e was 62265ce, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

OHCI initialization refactoring
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File size: 17.1 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohcihc
29 * @{
30 */
31/** @file
32 * @brief OHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb/usbdevice.h>
43
44#include "hc.h"
45#include "hcd_endpoint.h"
46
47#define OHCI_USED_INTERRUPTS \
48 (I_SO | I_WDH | I_UE | I_RHSC)
49static int interrupt_emulator(hc_t *instance);
50static void hc_gain_control(hc_t *instance);
51static int hc_init_transfer_lists(hc_t *instance);
52static int hc_init_memory(hc_t *instance);
53/*----------------------------------------------------------------------------*/
54int hc_register_hub(hc_t *instance, ddf_fun_t *hub_fun)
55{
56 assert(instance);
57 assert(hub_fun);
58
59 int ret;
60
61 usb_address_t hub_address =
62 device_keeper_get_free_address(&instance->manager, USB_SPEED_FULL);
63 if (hub_address <= 0) {
64 usb_log_error("Failed to get OHCI root hub address.\n");
65 return hub_address;
66 }
67 instance->rh.address = hub_address;
68 usb_device_keeper_bind(
69 &instance->manager, hub_address, hub_fun->handle);
70
71 ret = hc_add_endpoint(instance, hub_address, 0, USB_SPEED_FULL,
72 USB_TRANSFER_CONTROL, USB_DIRECTION_BOTH, 64, 0, 0);
73 if (ret != EOK) {
74 usb_log_error("Failed to add OHCI rh endpoint 0.\n");
75 usb_device_keeper_release(&instance->manager, hub_address);
76 return ret;
77 }
78
79 char *match_str = NULL;
80 /* DDF needs heap allocated string */
81 ret = asprintf(&match_str, "usb&class=hub");
82 if (ret < 0) {
83 usb_log_error(
84 "Failed(%d) to create root hub match-id string.\n", ret);
85 usb_device_keeper_release(&instance->manager, hub_address);
86 return ret;
87 }
88
89 ret = ddf_fun_add_match_id(hub_fun, match_str, 100);
90 if (ret != EOK) {
91 usb_log_error("Failed add root hub match-id.\n");
92 }
93 ret = ddf_fun_bind(hub_fun);
94 return ret;
95}
96/*----------------------------------------------------------------------------*/
97int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
98{
99 assert(instance);
100 int ret = EOK;
101#define CHECK_RET_RETURN(ret, message...) \
102if (ret != EOK) { \
103 usb_log_error(message); \
104 return ret; \
105} else (void)0
106
107 ret = pio_enable((void*)regs, reg_size, (void**)&instance->registers);
108 CHECK_RET_RETURN(ret,
109 "Failed(%d) to gain access to device registers: %s.\n",
110 ret, str_error(ret));
111
112 list_initialize(&instance->pending_batches);
113 usb_device_keeper_init(&instance->manager);
114 ret = usb_endpoint_manager_init(&instance->ep_manager,
115 BANDWIDTH_AVAILABLE_USB11);
116 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
117 str_error(ret));
118
119 ret = hc_init_memory(instance);
120 CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
121 str_error(ret));
122#undef CHECK_RET_RETURN
123
124
125// hc_init_hw(instance);
126 hc_gain_control(instance);
127 fibril_mutex_initialize(&instance->guard);
128
129 rh_init(&instance->rh, instance->registers);
130
131 if (!interrupts) {
132 instance->interrupt_emulator =
133 fibril_create((int(*)(void*))interrupt_emulator, instance);
134 fibril_add_ready(instance->interrupt_emulator);
135 }
136
137 return EOK;
138}
139/*----------------------------------------------------------------------------*/
140int hc_add_endpoint(
141 hc_t *instance, usb_address_t address, usb_endpoint_t endpoint,
142 usb_speed_t speed, usb_transfer_type_t type, usb_direction_t direction,
143 size_t mps, size_t size, unsigned interval)
144{
145 endpoint_t *ep = malloc(sizeof(endpoint_t));
146 if (ep == NULL)
147 return ENOMEM;
148 int ret =
149 endpoint_init(ep, address, endpoint, direction, type, speed, mps);
150 if (ret != EOK) {
151 free(ep);
152 return ret;
153 }
154
155 hcd_endpoint_t *hcd_ep = hcd_endpoint_assign(ep);
156 if (hcd_ep == NULL) {
157 endpoint_destroy(ep);
158 return ENOMEM;
159 }
160
161 ret = usb_endpoint_manager_register_ep(&instance->ep_manager, ep, size);
162 if (ret != EOK) {
163 hcd_endpoint_clear(ep);
164 endpoint_destroy(ep);
165 return ret;
166 }
167
168 /* Enqueue hcd_ep */
169 switch (ep->transfer_type) {
170 case USB_TRANSFER_CONTROL:
171 instance->registers->control &= ~C_CLE;
172 endpoint_list_add_ep(
173 &instance->lists[ep->transfer_type], hcd_ep);
174 instance->registers->control_current = 0;
175 instance->registers->control |= C_CLE;
176 break;
177 case USB_TRANSFER_BULK:
178 instance->registers->control &= ~C_BLE;
179 endpoint_list_add_ep(
180 &instance->lists[ep->transfer_type], hcd_ep);
181 instance->registers->control |= C_BLE;
182 break;
183 case USB_TRANSFER_ISOCHRONOUS:
184 case USB_TRANSFER_INTERRUPT:
185 instance->registers->control &= (~C_PLE & ~C_IE);
186 endpoint_list_add_ep(
187 &instance->lists[ep->transfer_type], hcd_ep);
188 instance->registers->control |= C_PLE | C_IE;
189 break;
190 default:
191 break;
192 }
193
194 return EOK;
195}
196/*----------------------------------------------------------------------------*/
197int hc_remove_endpoint(hc_t *instance, usb_address_t address,
198 usb_endpoint_t endpoint, usb_direction_t direction)
199{
200 assert(instance);
201 fibril_mutex_lock(&instance->guard);
202 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
203 address, endpoint, direction, NULL);
204 if (ep == NULL) {
205 usb_log_error("Endpoint unregister failed: No such EP.\n");
206 fibril_mutex_unlock(&instance->guard);
207 return ENOENT;
208 }
209
210 hcd_endpoint_t *hcd_ep = hcd_endpoint_get(ep);
211 if (hcd_ep) {
212 /* Dequeue hcd_ep */
213 switch (ep->transfer_type) {
214 case USB_TRANSFER_CONTROL:
215 instance->registers->control &= ~C_CLE;
216 endpoint_list_remove_ep(
217 &instance->lists[ep->transfer_type], hcd_ep);
218 instance->registers->control_current = 0;
219 instance->registers->control |= C_CLE;
220 break;
221 case USB_TRANSFER_BULK:
222 instance->registers->control &= ~C_BLE;
223 endpoint_list_remove_ep(
224 &instance->lists[ep->transfer_type], hcd_ep);
225 instance->registers->control |= C_BLE;
226 break;
227 case USB_TRANSFER_ISOCHRONOUS:
228 case USB_TRANSFER_INTERRUPT:
229 instance->registers->control &= (~C_PLE & ~C_IE);
230 endpoint_list_remove_ep(
231 &instance->lists[ep->transfer_type], hcd_ep);
232 instance->registers->control |= C_PLE | C_IE;
233 break;
234 default:
235 break;
236 }
237 hcd_endpoint_clear(ep);
238 } else {
239 usb_log_warning("Endpoint without hcd equivalent structure.\n");
240 }
241 int ret = usb_endpoint_manager_unregister_ep(&instance->ep_manager,
242 address, endpoint, direction);
243 fibril_mutex_unlock(&instance->guard);
244 return ret;
245}
246/*----------------------------------------------------------------------------*/
247endpoint_t * hc_get_endpoint(hc_t *instance, usb_address_t address,
248 usb_endpoint_t endpoint, usb_direction_t direction, size_t *bw)
249{
250 assert(instance);
251 fibril_mutex_lock(&instance->guard);
252 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
253 address, endpoint, direction, bw);
254 fibril_mutex_unlock(&instance->guard);
255 return ep;
256}
257/*----------------------------------------------------------------------------*/
258int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
259{
260 assert(instance);
261 assert(batch);
262 assert(batch->ep);
263
264 /* check for root hub communication */
265 if (batch->ep->address == instance->rh.address) {
266 return rh_request(&instance->rh, batch);
267 }
268
269 fibril_mutex_lock(&instance->guard);
270 list_append(&batch->link, &instance->pending_batches);
271 batch_commit(batch);
272 switch (batch->ep->transfer_type) {
273 case USB_TRANSFER_CONTROL:
274 instance->registers->command_status |= CS_CLF;
275 break;
276 case USB_TRANSFER_BULK:
277 instance->registers->command_status |= CS_BLF;
278 break;
279 default:
280 break;
281 }
282
283 fibril_mutex_unlock(&instance->guard);
284 return EOK;
285}
286/*----------------------------------------------------------------------------*/
287void hc_interrupt(hc_t *instance, uint32_t status)
288{
289 assert(instance);
290 usb_log_debug("OHCI(%p) interrupt: %x.\n", instance, status);
291 if ((status & ~I_SF) == 0) /* ignore sof status */
292 return;
293 if (status & I_RHSC)
294 rh_interrupt(&instance->rh);
295
296
297 if (status & I_WDH) {
298 fibril_mutex_lock(&instance->guard);
299 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
300 instance->registers->hcca,
301 (void *) addr_to_phys(instance->hcca));
302 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
303 instance->registers->periodic_current);
304
305 link_t *current = instance->pending_batches.next;
306 while (current != &instance->pending_batches) {
307 link_t *next = current->next;
308 usb_transfer_batch_t *batch =
309 usb_transfer_batch_from_link(current);
310
311 if (batch_is_complete(batch)) {
312 list_remove(current);
313 usb_transfer_batch_finish(batch);
314 }
315 current = next;
316 }
317 fibril_mutex_unlock(&instance->guard);
318 }
319}
320/*----------------------------------------------------------------------------*/
321int interrupt_emulator(hc_t *instance)
322{
323 assert(instance);
324 usb_log_info("Started interrupt emulator.\n");
325 while (1) {
326 const uint32_t status = instance->registers->interrupt_status;
327 instance->registers->interrupt_status = status;
328 hc_interrupt(instance, status);
329 async_usleep(50000);
330 }
331 return EOK;
332}
333/*----------------------------------------------------------------------------*/
334void hc_gain_control(hc_t *instance)
335{
336 assert(instance);
337 usb_log_debug("Requesting OHCI control.\n");
338 /* Turn off legacy emulation */
339 volatile uint32_t *ohci_emulation_reg =
340 (uint32_t*)((char*)instance->registers + 0x100);
341 usb_log_debug("OHCI legacy register %p: %x.\n",
342 ohci_emulation_reg, *ohci_emulation_reg);
343 /* Do not change A20 state */
344 *ohci_emulation_reg &= 0x100;
345 usb_log_debug("OHCI legacy register %p: %x.\n",
346 ohci_emulation_reg, *ohci_emulation_reg);
347
348 /* Interrupt routing enabled => smm driver is active */
349 if (instance->registers->control & C_IR) {
350 usb_log_debug("SMM driver: request ownership change.\n");
351 instance->registers->command_status |= CS_OCR;
352 while (instance->registers->control & C_IR) {
353 async_usleep(1000);
354 }
355 usb_log_info("SMM driver: Ownership taken.\n");
356 instance->registers->control &= (C_HCFS_RESET << C_HCFS_SHIFT);
357 async_usleep(50000);
358 return;
359 }
360
361 const unsigned hc_status =
362 (instance->registers->control >> C_HCFS_SHIFT) & C_HCFS_MASK;
363 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
364 if (hc_status != C_HCFS_RESET) {
365 usb_log_debug("BIOS driver found.\n");
366 if (hc_status == C_HCFS_OPERATIONAL) {
367 usb_log_info("BIOS driver: HC operational.\n");
368 return;
369 }
370 /* HC is suspended assert resume for 20ms */
371 instance->registers->control &= (C_HCFS_RESUME << C_HCFS_SHIFT);
372 async_usleep(20000);
373 usb_log_info("BIOS driver: HC resumed.\n");
374 return;
375 }
376
377 /* HC is in reset (hw startup) => no other driver
378 * maintain reset for at least the time specified in USB spec (50 ms)*/
379 usb_log_info("HC found in reset.\n");
380 async_usleep(50000);
381}
382/*----------------------------------------------------------------------------*/
383void hc_start_hw(hc_t *instance)
384{
385 /* OHCI guide page 42 */
386 assert(instance);
387 usb_log_debug2("Started hc initialization routine.\n");
388
389 /* Save contents of fm_interval register */
390 const uint32_t fm_interval = instance->registers->fm_interval;
391 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
392
393 /* Reset hc */
394 usb_log_debug2("HC reset.\n");
395 size_t time = 0;
396 instance->registers->command_status = CS_HCR;
397 while (instance->registers->command_status & CS_HCR) {
398 async_usleep(10);
399 time += 10;
400 }
401 usb_log_debug2("HC reset complete in %zu us.\n", time);
402
403 /* Restore fm_interval */
404 instance->registers->fm_interval = fm_interval;
405 assert((instance->registers->command_status & CS_HCR) == 0);
406
407 /* hc is now in suspend state */
408 usb_log_debug2("HC should be in suspend state(%x).\n",
409 instance->registers->control);
410
411 /* Use HCCA */
412 instance->registers->hcca = addr_to_phys(instance->hcca);
413
414 /* Use queues */
415 instance->registers->bulk_head =
416 instance->lists[USB_TRANSFER_BULK].list_head_pa;
417 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
418 instance->lists[USB_TRANSFER_BULK].list_head,
419 instance->lists[USB_TRANSFER_BULK].list_head_pa);
420
421 instance->registers->control_head =
422 instance->lists[USB_TRANSFER_CONTROL].list_head_pa;
423 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
424 instance->lists[USB_TRANSFER_CONTROL].list_head,
425 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
426
427 /* Enable queues */
428 instance->registers->control |= (C_PLE | C_IE | C_CLE | C_BLE);
429 usb_log_debug2("All queues enabled(%x).\n",
430 instance->registers->control);
431
432 /* Enable interrupts */
433 instance->registers->interrupt_enable = OHCI_USED_INTERRUPTS;
434 usb_log_debug2("Enabled interrupts: %x.\n",
435 instance->registers->interrupt_enable);
436 instance->registers->interrupt_enable = I_MI;
437
438 /* Set periodic start to 90% */
439 uint32_t frame_length = ((fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK);
440 instance->registers->periodic_start = (frame_length / 10) * 9;
441 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
442 instance->registers->periodic_start,
443 instance->registers->periodic_start, frame_length);
444
445 instance->registers->control &= (C_HCFS_OPERATIONAL << C_HCFS_SHIFT);
446 usb_log_info("OHCI HC up and running(%x).\n",
447 instance->registers->control);
448}
449/*----------------------------------------------------------------------------*/
450int hc_init_transfer_lists(hc_t *instance)
451{
452 assert(instance);
453
454#define SETUP_ENDPOINT_LIST(type) \
455do { \
456 const char *name = usb_str_transfer_type(type); \
457 int ret = endpoint_list_init(&instance->lists[type], name); \
458 if (ret != EOK) { \
459 usb_log_error("Failed(%d) to setup %s endpoint list.\n", \
460 ret, name); \
461 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]); \
462 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
463 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
464 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
465 } \
466} while (0)
467
468 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
469 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
470 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
471 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
472#undef SETUP_ENDPOINT_LIST
473 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
474 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
475
476 return EOK;
477}
478/*----------------------------------------------------------------------------*/
479int hc_init_memory(hc_t *instance)
480{
481 assert(instance);
482
483 bzero(&instance->rh, sizeof(instance->rh));
484 /* Init queues */
485 hc_init_transfer_lists(instance);
486
487 /*Init HCCA */
488 instance->hcca = malloc32(sizeof(hcca_t));
489 if (instance->hcca == NULL)
490 return ENOMEM;
491 bzero(instance->hcca, sizeof(hcca_t));
492 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
493
494 unsigned i = 0;
495 for (; i < 32; ++i) {
496 instance->hcca->int_ep[i] =
497 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa;
498 }
499 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
500 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
501 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
502
503 /* Init interrupt code */
504 instance->interrupt_code.cmds = instance->interrupt_commands;
505 {
506 /* Read status register */
507 instance->interrupt_commands[0].cmd = CMD_MEM_READ_32;
508 instance->interrupt_commands[0].dstarg = 1;
509 instance->interrupt_commands[0].addr =
510 (void*)&instance->registers->interrupt_status;
511
512 /* Test whether we are the interrupt cause */
513 instance->interrupt_commands[1].cmd = CMD_BTEST;
514 instance->interrupt_commands[1].value =
515 OHCI_USED_INTERRUPTS;
516 instance->interrupt_commands[1].srcarg = 1;
517 instance->interrupt_commands[1].dstarg = 2;
518
519 /* Predicate cleaning and accepting */
520 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
521 instance->interrupt_commands[2].value = 2;
522 instance->interrupt_commands[2].srcarg = 2;
523
524 /* Write clean status register */
525 instance->interrupt_commands[3].cmd = CMD_MEM_WRITE_A_32;
526 instance->interrupt_commands[3].srcarg = 1;
527 instance->interrupt_commands[3].addr =
528 (void*)&instance->registers->interrupt_status;
529
530 /* Accept interrupt */
531 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
532
533 instance->interrupt_code.cmdcount = OHCI_NEEDED_IRQ_COMMANDS;
534 }
535
536 return EOK;
537}
538/**
539 * @}
540 */
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