source: mainline/uspace/drv/ohci/hc.c@ 68b9f148

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 68b9f148 was 68b9f148, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

OHCI: restart hw on unrecoverable error
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File size: 17.1 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohcihc
29 * @{
30 */
31/** @file
32 * @brief OHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42
43#include "hc.h"
44#include "hcd_endpoint.h"
45
46#define OHCI_USED_INTERRUPTS \
47 (I_SO | I_WDH | I_UE | I_RHSC)
48static int interrupt_emulator(hc_t *instance);
49static void hc_gain_control(hc_t *instance);
50static int hc_init_transfer_lists(hc_t *instance);
51static int hc_init_memory(hc_t *instance);
52/*----------------------------------------------------------------------------*/
53int hc_register_hub(hc_t *instance, ddf_fun_t *hub_fun)
54{
55 assert(instance);
56 assert(hub_fun);
57
58 int ret;
59
60 usb_address_t hub_address =
61 device_keeper_get_free_address(&instance->manager, USB_SPEED_FULL);
62 if (hub_address <= 0) {
63 usb_log_error("Failed to get OHCI root hub address.\n");
64 return hub_address;
65 }
66 instance->rh.address = hub_address;
67 usb_device_keeper_bind(
68 &instance->manager, hub_address, hub_fun->handle);
69
70 ret = hc_add_endpoint(instance, hub_address, 0, USB_SPEED_FULL,
71 USB_TRANSFER_CONTROL, USB_DIRECTION_BOTH, 64, 0, 0);
72 if (ret != EOK) {
73 usb_log_error("Failed to add OHCI rh endpoint 0.\n");
74 usb_device_keeper_release(&instance->manager, hub_address);
75 return ret;
76 }
77
78 char *match_str = NULL;
79 /* DDF needs heap allocated string */
80 ret = asprintf(&match_str, "usb&class=hub");
81 if (ret < 0) {
82 usb_log_error(
83 "Failed(%d) to create root hub match-id string.\n", ret);
84 usb_device_keeper_release(&instance->manager, hub_address);
85 return ret;
86 }
87
88 ret = ddf_fun_add_match_id(hub_fun, match_str, 100);
89 if (ret != EOK) {
90 usb_log_error("Failed add root hub match-id.\n");
91 }
92 ret = ddf_fun_bind(hub_fun);
93 return ret;
94}
95/*----------------------------------------------------------------------------*/
96int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
97{
98 assert(instance);
99 int ret = EOK;
100#define CHECK_RET_RETURN(ret, message...) \
101if (ret != EOK) { \
102 usb_log_error(message); \
103 return ret; \
104} else (void)0
105
106 ret = pio_enable((void*)regs, reg_size, (void**)&instance->registers);
107 CHECK_RET_RETURN(ret,
108 "Failed(%d) to gain access to device registers: %s.\n",
109 ret, str_error(ret));
110
111 list_initialize(&instance->pending_batches);
112 usb_device_keeper_init(&instance->manager);
113 ret = usb_endpoint_manager_init(&instance->ep_manager,
114 BANDWIDTH_AVAILABLE_USB11);
115 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
116 str_error(ret));
117
118 ret = hc_init_memory(instance);
119 CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
120 str_error(ret));
121#undef CHECK_RET_RETURN
122
123
124// hc_init_hw(instance);
125 hc_gain_control(instance);
126 fibril_mutex_initialize(&instance->guard);
127
128 rh_init(&instance->rh, instance->registers);
129
130 if (!interrupts) {
131 instance->interrupt_emulator =
132 fibril_create((int(*)(void*))interrupt_emulator, instance);
133 fibril_add_ready(instance->interrupt_emulator);
134 }
135
136 return EOK;
137}
138/*----------------------------------------------------------------------------*/
139int hc_add_endpoint(
140 hc_t *instance, usb_address_t address, usb_endpoint_t endpoint,
141 usb_speed_t speed, usb_transfer_type_t type, usb_direction_t direction,
142 size_t mps, size_t size, unsigned interval)
143{
144 endpoint_t *ep = malloc(sizeof(endpoint_t));
145 if (ep == NULL)
146 return ENOMEM;
147 int ret =
148 endpoint_init(ep, address, endpoint, direction, type, speed, mps);
149 if (ret != EOK) {
150 free(ep);
151 return ret;
152 }
153
154 hcd_endpoint_t *hcd_ep = hcd_endpoint_assign(ep);
155 if (hcd_ep == NULL) {
156 endpoint_destroy(ep);
157 return ENOMEM;
158 }
159
160 ret = usb_endpoint_manager_register_ep(&instance->ep_manager, ep, size);
161 if (ret != EOK) {
162 hcd_endpoint_clear(ep);
163 endpoint_destroy(ep);
164 return ret;
165 }
166
167 /* Enqueue hcd_ep */
168 switch (ep->transfer_type) {
169 case USB_TRANSFER_CONTROL:
170 instance->registers->control &= ~C_CLE;
171 endpoint_list_add_ep(
172 &instance->lists[ep->transfer_type], hcd_ep);
173 instance->registers->control_current = 0;
174 instance->registers->control |= C_CLE;
175 break;
176 case USB_TRANSFER_BULK:
177 instance->registers->control &= ~C_BLE;
178 endpoint_list_add_ep(
179 &instance->lists[ep->transfer_type], hcd_ep);
180 instance->registers->control |= C_BLE;
181 break;
182 case USB_TRANSFER_ISOCHRONOUS:
183 case USB_TRANSFER_INTERRUPT:
184 instance->registers->control &= (~C_PLE & ~C_IE);
185 endpoint_list_add_ep(
186 &instance->lists[ep->transfer_type], hcd_ep);
187 instance->registers->control |= C_PLE | C_IE;
188 break;
189 default:
190 break;
191 }
192
193 return EOK;
194}
195/*----------------------------------------------------------------------------*/
196int hc_remove_endpoint(hc_t *instance, usb_address_t address,
197 usb_endpoint_t endpoint, usb_direction_t direction)
198{
199 assert(instance);
200 fibril_mutex_lock(&instance->guard);
201 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
202 address, endpoint, direction, NULL);
203 if (ep == NULL) {
204 usb_log_error("Endpoint unregister failed: No such EP.\n");
205 fibril_mutex_unlock(&instance->guard);
206 return ENOENT;
207 }
208
209 hcd_endpoint_t *hcd_ep = hcd_endpoint_get(ep);
210 if (hcd_ep) {
211 /* Dequeue hcd_ep */
212 switch (ep->transfer_type) {
213 case USB_TRANSFER_CONTROL:
214 instance->registers->control &= ~C_CLE;
215 endpoint_list_remove_ep(
216 &instance->lists[ep->transfer_type], hcd_ep);
217 instance->registers->control_current = 0;
218 instance->registers->control |= C_CLE;
219 break;
220 case USB_TRANSFER_BULK:
221 instance->registers->control &= ~C_BLE;
222 endpoint_list_remove_ep(
223 &instance->lists[ep->transfer_type], hcd_ep);
224 instance->registers->control |= C_BLE;
225 break;
226 case USB_TRANSFER_ISOCHRONOUS:
227 case USB_TRANSFER_INTERRUPT:
228 instance->registers->control &= (~C_PLE & ~C_IE);
229 endpoint_list_remove_ep(
230 &instance->lists[ep->transfer_type], hcd_ep);
231 instance->registers->control |= C_PLE | C_IE;
232 break;
233 default:
234 break;
235 }
236 hcd_endpoint_clear(ep);
237 } else {
238 usb_log_warning("Endpoint without hcd equivalent structure.\n");
239 }
240 int ret = usb_endpoint_manager_unregister_ep(&instance->ep_manager,
241 address, endpoint, direction);
242 fibril_mutex_unlock(&instance->guard);
243 return ret;
244}
245/*----------------------------------------------------------------------------*/
246endpoint_t * hc_get_endpoint(hc_t *instance, usb_address_t address,
247 usb_endpoint_t endpoint, usb_direction_t direction, size_t *bw)
248{
249 assert(instance);
250 fibril_mutex_lock(&instance->guard);
251 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
252 address, endpoint, direction, bw);
253 fibril_mutex_unlock(&instance->guard);
254 return ep;
255}
256/*----------------------------------------------------------------------------*/
257int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
258{
259 assert(instance);
260 assert(batch);
261 assert(batch->ep);
262
263 /* check for root hub communication */
264 if (batch->ep->address == instance->rh.address) {
265 return rh_request(&instance->rh, batch);
266 }
267
268 fibril_mutex_lock(&instance->guard);
269 list_append(&batch->link, &instance->pending_batches);
270 batch_commit(batch);
271 switch (batch->ep->transfer_type) {
272 case USB_TRANSFER_CONTROL:
273 instance->registers->command_status |= CS_CLF;
274 break;
275 case USB_TRANSFER_BULK:
276 instance->registers->command_status |= CS_BLF;
277 break;
278 default:
279 break;
280 }
281
282 fibril_mutex_unlock(&instance->guard);
283 return EOK;
284}
285/*----------------------------------------------------------------------------*/
286void hc_interrupt(hc_t *instance, uint32_t status)
287{
288 assert(instance);
289 usb_log_debug("OHCI(%p) interrupt: %x.\n", instance, status);
290 if ((status & ~I_SF) == 0) /* ignore sof status */
291 return;
292 if (status & I_RHSC)
293 rh_interrupt(&instance->rh);
294
295 if (status & I_WDH) {
296 fibril_mutex_lock(&instance->guard);
297 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
298 instance->registers->hcca,
299 (void *) addr_to_phys(instance->hcca));
300 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
301 instance->registers->periodic_current);
302
303 link_t *current = instance->pending_batches.next;
304 while (current != &instance->pending_batches) {
305 link_t *next = current->next;
306 usb_transfer_batch_t *batch =
307 usb_transfer_batch_from_link(current);
308
309 if (batch_is_complete(batch)) {
310 list_remove(current);
311 usb_transfer_batch_finish(batch);
312 }
313 current = next;
314 }
315 fibril_mutex_unlock(&instance->guard);
316 }
317
318 if (status & I_UE) {
319 hc_start_hw(instance);
320 }
321
322}
323/*----------------------------------------------------------------------------*/
324int interrupt_emulator(hc_t *instance)
325{
326 assert(instance);
327 usb_log_info("Started interrupt emulator.\n");
328 while (1) {
329 const uint32_t status = instance->registers->interrupt_status;
330 instance->registers->interrupt_status = status;
331 hc_interrupt(instance, status);
332 async_usleep(50000);
333 }
334 return EOK;
335}
336/*----------------------------------------------------------------------------*/
337void hc_gain_control(hc_t *instance)
338{
339 assert(instance);
340 usb_log_debug("Requesting OHCI control.\n");
341 /* Turn off legacy emulation */
342 volatile uint32_t *ohci_emulation_reg =
343 (uint32_t*)((char*)instance->registers + 0x100);
344 usb_log_debug("OHCI legacy register %p: %x.\n",
345 ohci_emulation_reg, *ohci_emulation_reg);
346 /* Do not change A20 state */
347 *ohci_emulation_reg &= 0x100;
348 usb_log_debug("OHCI legacy register %p: %x.\n",
349 ohci_emulation_reg, *ohci_emulation_reg);
350
351 /* Interrupt routing enabled => smm driver is active */
352 if (instance->registers->control & C_IR) {
353 usb_log_debug("SMM driver: request ownership change.\n");
354 instance->registers->command_status |= CS_OCR;
355 while (instance->registers->control & C_IR) {
356 async_usleep(1000);
357 }
358 usb_log_info("SMM driver: Ownership taken.\n");
359 instance->registers->control &= (C_HCFS_RESET << C_HCFS_SHIFT);
360 async_usleep(50000);
361 return;
362 }
363
364 const unsigned hc_status =
365 (instance->registers->control >> C_HCFS_SHIFT) & C_HCFS_MASK;
366 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
367 if (hc_status != C_HCFS_RESET) {
368 usb_log_debug("BIOS driver found.\n");
369 if (hc_status == C_HCFS_OPERATIONAL) {
370 usb_log_info("BIOS driver: HC operational.\n");
371 return;
372 }
373 /* HC is suspended assert resume for 20ms */
374 instance->registers->control &= (C_HCFS_RESUME << C_HCFS_SHIFT);
375 async_usleep(20000);
376 usb_log_info("BIOS driver: HC resumed.\n");
377 return;
378 }
379
380 /* HC is in reset (hw startup) => no other driver
381 * maintain reset for at least the time specified in USB spec (50 ms)*/
382 usb_log_info("HC found in reset.\n");
383 async_usleep(50000);
384}
385/*----------------------------------------------------------------------------*/
386void hc_start_hw(hc_t *instance)
387{
388 /* OHCI guide page 42 */
389 assert(instance);
390 usb_log_debug2("Started hc initialization routine.\n");
391
392 /* Save contents of fm_interval register */
393 const uint32_t fm_interval = instance->registers->fm_interval;
394 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
395
396 /* Reset hc */
397 usb_log_debug2("HC reset.\n");
398 size_t time = 0;
399 instance->registers->command_status = CS_HCR;
400 while (instance->registers->command_status & CS_HCR) {
401 async_usleep(10);
402 time += 10;
403 }
404 usb_log_debug2("HC reset complete in %zu us.\n", time);
405
406 /* Restore fm_interval */
407 instance->registers->fm_interval = fm_interval;
408 assert((instance->registers->command_status & CS_HCR) == 0);
409
410 /* hc is now in suspend state */
411 usb_log_debug2("HC should be in suspend state(%x).\n",
412 instance->registers->control);
413
414 /* Use HCCA */
415 instance->registers->hcca = addr_to_phys(instance->hcca);
416
417 /* Use queues */
418 instance->registers->bulk_head =
419 instance->lists[USB_TRANSFER_BULK].list_head_pa;
420 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
421 instance->lists[USB_TRANSFER_BULK].list_head,
422 instance->lists[USB_TRANSFER_BULK].list_head_pa);
423
424 instance->registers->control_head =
425 instance->lists[USB_TRANSFER_CONTROL].list_head_pa;
426 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
427 instance->lists[USB_TRANSFER_CONTROL].list_head,
428 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
429
430 /* Enable queues */
431 instance->registers->control |= (C_PLE | C_IE | C_CLE | C_BLE);
432 usb_log_debug2("All queues enabled(%x).\n",
433 instance->registers->control);
434
435 /* Enable interrupts */
436 instance->registers->interrupt_enable = OHCI_USED_INTERRUPTS;
437 usb_log_debug2("Enabled interrupts: %x.\n",
438 instance->registers->interrupt_enable);
439 instance->registers->interrupt_enable = I_MI;
440
441 /* Set periodic start to 90% */
442 uint32_t frame_length = ((fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK);
443 instance->registers->periodic_start = (frame_length / 10) * 9;
444 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
445 instance->registers->periodic_start,
446 instance->registers->periodic_start, frame_length);
447
448 instance->registers->control &= (C_HCFS_OPERATIONAL << C_HCFS_SHIFT);
449 usb_log_info("OHCI HC up and running(%x).\n",
450 instance->registers->control);
451}
452/*----------------------------------------------------------------------------*/
453int hc_init_transfer_lists(hc_t *instance)
454{
455 assert(instance);
456#define SETUP_ENDPOINT_LIST(type) \
457do { \
458 const char *name = usb_str_transfer_type(type); \
459 int ret = endpoint_list_init(&instance->lists[type], name); \
460 if (ret != EOK) { \
461 usb_log_error("Failed(%d) to setup %s endpoint list.\n", \
462 ret, name); \
463 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
464 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
465 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
466 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
467 } \
468} while (0)
469
470 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
471 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
472 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
473 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
474#undef SETUP_ENDPOINT_LIST
475 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
476 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
477
478 return EOK;
479}
480/*----------------------------------------------------------------------------*/
481int hc_init_memory(hc_t *instance)
482{
483 assert(instance);
484
485 bzero(&instance->rh, sizeof(instance->rh));
486 /* Init queues */
487 hc_init_transfer_lists(instance);
488
489 /*Init HCCA */
490 instance->hcca = malloc32(sizeof(hcca_t));
491 if (instance->hcca == NULL)
492 return ENOMEM;
493 bzero(instance->hcca, sizeof(hcca_t));
494 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
495
496 unsigned i = 0;
497 for (; i < 32; ++i) {
498 instance->hcca->int_ep[i] =
499 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa;
500 }
501 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
502 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
503 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
504
505 /* Init interrupt code */
506 instance->interrupt_code.cmds = instance->interrupt_commands;
507 {
508 /* Read status register */
509 instance->interrupt_commands[0].cmd = CMD_MEM_READ_32;
510 instance->interrupt_commands[0].dstarg = 1;
511 instance->interrupt_commands[0].addr =
512 (void*)&instance->registers->interrupt_status;
513
514 /* Test whether we are the interrupt cause */
515 instance->interrupt_commands[1].cmd = CMD_BTEST;
516 instance->interrupt_commands[1].value =
517 OHCI_USED_INTERRUPTS;
518 instance->interrupt_commands[1].srcarg = 1;
519 instance->interrupt_commands[1].dstarg = 2;
520
521 /* Predicate cleaning and accepting */
522 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
523 instance->interrupt_commands[2].value = 2;
524 instance->interrupt_commands[2].srcarg = 2;
525
526 /* Write clean status register */
527 instance->interrupt_commands[3].cmd = CMD_MEM_WRITE_A_32;
528 instance->interrupt_commands[3].srcarg = 1;
529 instance->interrupt_commands[3].addr =
530 (void*)&instance->registers->interrupt_status;
531
532 /* Accept interrupt */
533 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
534
535 instance->interrupt_code.cmdcount = OHCI_NEEDED_IRQ_COMMANDS;
536 }
537
538 return EOK;
539}
540/**
541 * @}
542 */
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