source: mainline/uspace/drv/ohci/hc.c@ 2ff7360

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2ff7360 was 2ff7360, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

Use better error handling in root hub registration routine
  • Property mode set to 100644
File size: 17.3 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohcihc
29 * @{
30 */
31/** @file
32 * @brief OHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42
43#include "hc.h"
44#include "hcd_endpoint.h"
45
46#define OHCI_USED_INTERRUPTS \
47 (I_SO | I_WDH | I_UE | I_RHSC)
48static int interrupt_emulator(hc_t *instance);
49static void hc_gain_control(hc_t *instance);
50static int hc_init_transfer_lists(hc_t *instance);
51static int hc_init_memory(hc_t *instance);
52/*----------------------------------------------------------------------------*/
53int hc_register_hub(hc_t *instance, ddf_fun_t *hub_fun)
54{
55 assert(instance);
56 assert(hub_fun);
57
58 const usb_address_t hub_address =
59 device_keeper_get_free_address(&instance->manager, USB_SPEED_FULL);
60 if (hub_address <= 0) {
61 usb_log_error("Failed(%d) to get OHCI root hub address.\n",
62 hub_address);
63 return hub_address;
64 }
65 instance->rh.address = hub_address;
66 usb_device_keeper_bind(
67 &instance->manager, hub_address, hub_fun->handle);
68
69#define CHECK_RET_RELEASE(ret, message...) \
70if (ret != EOK) { \
71 usb_log_error(message); \
72 hc_remove_endpoint(instance, hub_address, 0, USB_DIRECTION_BOTH); \
73 usb_device_keeper_release(&instance->manager, hub_address); \
74 return ret; \
75} else (void)0
76
77 int ret = hc_add_endpoint(instance, hub_address, 0, USB_SPEED_FULL,
78 USB_TRANSFER_CONTROL, USB_DIRECTION_BOTH, 64, 0, 0);
79 CHECK_RET_RELEASE(ret, "Failed(%d) to add OHCI rh endpoint 0.\n", ret);
80
81 char *match_str = NULL;
82 /* DDF needs heap allocated string */
83 ret = asprintf(&match_str, "usb&class=hub");
84 ret = ret > 0 ? 0 : ret;
85 CHECK_RET_RELEASE(ret, "Failed(%d) to create match-id string.\n", ret);
86
87 ret = ddf_fun_add_match_id(hub_fun, match_str, 100);
88 CHECK_RET_RELEASE(ret, "Failed(%d) add root hub match-id.\n", ret);
89
90 ret = ddf_fun_bind(hub_fun);
91 CHECK_RET_RELEASE(ret, "Failed(%d) to bind root hub function.\n", ret);
92
93 return EOK;
94#undef CHECK_RET_RELEASE
95}
96/*----------------------------------------------------------------------------*/
97int hc_init(hc_t *instance, uintptr_t regs, size_t reg_size, bool interrupts)
98{
99 assert(instance);
100 int ret = EOK;
101#define CHECK_RET_RETURN(ret, message...) \
102if (ret != EOK) { \
103 usb_log_error(message); \
104 return ret; \
105} else (void)0
106
107 ret = pio_enable((void*)regs, reg_size, (void**)&instance->registers);
108 CHECK_RET_RETURN(ret,
109 "Failed(%d) to gain access to device registers: %s.\n",
110 ret, str_error(ret));
111
112 list_initialize(&instance->pending_batches);
113 usb_device_keeper_init(&instance->manager);
114 ret = usb_endpoint_manager_init(&instance->ep_manager,
115 BANDWIDTH_AVAILABLE_USB11);
116 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
117 str_error(ret));
118
119 ret = hc_init_memory(instance);
120 CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
121 str_error(ret));
122#undef CHECK_RET_RETURN
123
124 fibril_mutex_initialize(&instance->guard);
125 hc_gain_control(instance);
126
127 rh_init(&instance->rh, instance->registers);
128
129 if (!interrupts) {
130 instance->interrupt_emulator =
131 fibril_create((int(*)(void*))interrupt_emulator, instance);
132 fibril_add_ready(instance->interrupt_emulator);
133 }
134
135 return EOK;
136}
137/*----------------------------------------------------------------------------*/
138int hc_add_endpoint(
139 hc_t *instance, usb_address_t address, usb_endpoint_t endpoint,
140 usb_speed_t speed, usb_transfer_type_t type, usb_direction_t direction,
141 size_t mps, size_t size, unsigned interval)
142{
143 endpoint_t *ep = malloc(sizeof(endpoint_t));
144 if (ep == NULL)
145 return ENOMEM;
146 int ret =
147 endpoint_init(ep, address, endpoint, direction, type, speed, mps);
148 if (ret != EOK) {
149 free(ep);
150 return ret;
151 }
152
153 hcd_endpoint_t *hcd_ep = hcd_endpoint_assign(ep);
154 if (hcd_ep == NULL) {
155 endpoint_destroy(ep);
156 return ENOMEM;
157 }
158
159 ret = usb_endpoint_manager_register_ep(&instance->ep_manager, ep, size);
160 if (ret != EOK) {
161 hcd_endpoint_clear(ep);
162 endpoint_destroy(ep);
163 return ret;
164 }
165
166 /* Enqueue hcd_ep */
167 switch (ep->transfer_type) {
168 case USB_TRANSFER_CONTROL:
169 instance->registers->control &= ~C_CLE;
170 endpoint_list_add_ep(
171 &instance->lists[ep->transfer_type], hcd_ep);
172 instance->registers->control_current = 0;
173 instance->registers->control |= C_CLE;
174 break;
175 case USB_TRANSFER_BULK:
176 instance->registers->control &= ~C_BLE;
177 endpoint_list_add_ep(
178 &instance->lists[ep->transfer_type], hcd_ep);
179 instance->registers->control |= C_BLE;
180 break;
181 case USB_TRANSFER_ISOCHRONOUS:
182 case USB_TRANSFER_INTERRUPT:
183 instance->registers->control &= (~C_PLE & ~C_IE);
184 endpoint_list_add_ep(
185 &instance->lists[ep->transfer_type], hcd_ep);
186 instance->registers->control |= C_PLE | C_IE;
187 break;
188 default:
189 break;
190 }
191
192 return EOK;
193}
194/*----------------------------------------------------------------------------*/
195int hc_remove_endpoint(hc_t *instance, usb_address_t address,
196 usb_endpoint_t endpoint, usb_direction_t direction)
197{
198 assert(instance);
199 fibril_mutex_lock(&instance->guard);
200 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
201 address, endpoint, direction, NULL);
202 if (ep == NULL) {
203 usb_log_error("Endpoint unregister failed: No such EP.\n");
204 fibril_mutex_unlock(&instance->guard);
205 return ENOENT;
206 }
207
208 hcd_endpoint_t *hcd_ep = hcd_endpoint_get(ep);
209 if (hcd_ep) {
210 /* Dequeue hcd_ep */
211 switch (ep->transfer_type) {
212 case USB_TRANSFER_CONTROL:
213 instance->registers->control &= ~C_CLE;
214 endpoint_list_remove_ep(
215 &instance->lists[ep->transfer_type], hcd_ep);
216 instance->registers->control_current = 0;
217 instance->registers->control |= C_CLE;
218 break;
219 case USB_TRANSFER_BULK:
220 instance->registers->control &= ~C_BLE;
221 endpoint_list_remove_ep(
222 &instance->lists[ep->transfer_type], hcd_ep);
223 instance->registers->control |= C_BLE;
224 break;
225 case USB_TRANSFER_ISOCHRONOUS:
226 case USB_TRANSFER_INTERRUPT:
227 instance->registers->control &= (~C_PLE & ~C_IE);
228 endpoint_list_remove_ep(
229 &instance->lists[ep->transfer_type], hcd_ep);
230 instance->registers->control |= C_PLE | C_IE;
231 break;
232 default:
233 break;
234 }
235 hcd_endpoint_clear(ep);
236 } else {
237 usb_log_warning("Endpoint without hcd equivalent structure.\n");
238 }
239 int ret = usb_endpoint_manager_unregister_ep(&instance->ep_manager,
240 address, endpoint, direction);
241 fibril_mutex_unlock(&instance->guard);
242 return ret;
243}
244/*----------------------------------------------------------------------------*/
245endpoint_t * hc_get_endpoint(hc_t *instance, usb_address_t address,
246 usb_endpoint_t endpoint, usb_direction_t direction, size_t *bw)
247{
248 assert(instance);
249 fibril_mutex_lock(&instance->guard);
250 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
251 address, endpoint, direction, bw);
252 fibril_mutex_unlock(&instance->guard);
253 return ep;
254}
255/*----------------------------------------------------------------------------*/
256int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
257{
258 assert(instance);
259 assert(batch);
260 assert(batch->ep);
261
262 /* check for root hub communication */
263 if (batch->ep->address == instance->rh.address) {
264 return rh_request(&instance->rh, batch);
265 }
266
267 fibril_mutex_lock(&instance->guard);
268 list_append(&batch->link, &instance->pending_batches);
269 batch_commit(batch);
270 switch (batch->ep->transfer_type) {
271 case USB_TRANSFER_CONTROL:
272 instance->registers->command_status |= CS_CLF;
273 break;
274 case USB_TRANSFER_BULK:
275 instance->registers->command_status |= CS_BLF;
276 break;
277 default:
278 break;
279 }
280
281 fibril_mutex_unlock(&instance->guard);
282 return EOK;
283}
284/*----------------------------------------------------------------------------*/
285void hc_interrupt(hc_t *instance, uint32_t status)
286{
287 assert(instance);
288 usb_log_debug("OHCI(%p) interrupt: %x.\n", instance, status);
289 if ((status & ~I_SF) == 0) /* ignore sof status */
290 return;
291 if (status & I_RHSC)
292 rh_interrupt(&instance->rh);
293
294 if (status & I_WDH) {
295 fibril_mutex_lock(&instance->guard);
296 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
297 instance->registers->hcca,
298 (void *) addr_to_phys(instance->hcca));
299 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
300 instance->registers->periodic_current);
301
302 link_t *current = instance->pending_batches.next;
303 while (current != &instance->pending_batches) {
304 link_t *next = current->next;
305 usb_transfer_batch_t *batch =
306 usb_transfer_batch_from_link(current);
307
308 if (batch_is_complete(batch)) {
309 list_remove(current);
310 usb_transfer_batch_finish(batch);
311 }
312 current = next;
313 }
314 fibril_mutex_unlock(&instance->guard);
315 }
316
317 if (status & I_UE) {
318 hc_start_hw(instance);
319 }
320
321}
322/*----------------------------------------------------------------------------*/
323int interrupt_emulator(hc_t *instance)
324{
325 assert(instance);
326 usb_log_info("Started interrupt emulator.\n");
327 while (1) {
328 const uint32_t status = instance->registers->interrupt_status;
329 instance->registers->interrupt_status = status;
330 hc_interrupt(instance, status);
331 async_usleep(50000);
332 }
333 return EOK;
334}
335/*----------------------------------------------------------------------------*/
336void hc_gain_control(hc_t *instance)
337{
338 assert(instance);
339 usb_log_debug("Requesting OHCI control.\n");
340 /* Turn off legacy emulation */
341 volatile uint32_t *ohci_emulation_reg =
342 (uint32_t*)((char*)instance->registers + 0x100);
343 usb_log_debug("OHCI legacy register %p: %x.\n",
344 ohci_emulation_reg, *ohci_emulation_reg);
345 /* Do not change A20 state */
346 *ohci_emulation_reg &= 0x100;
347 usb_log_debug("OHCI legacy register %p: %x.\n",
348 ohci_emulation_reg, *ohci_emulation_reg);
349
350 /* Interrupt routing enabled => smm driver is active */
351 if (instance->registers->control & C_IR) {
352 usb_log_debug("SMM driver: request ownership change.\n");
353 instance->registers->command_status |= CS_OCR;
354 while (instance->registers->control & C_IR) {
355 async_usleep(1000);
356 }
357 usb_log_info("SMM driver: Ownership taken.\n");
358 instance->registers->control &= (C_HCFS_RESET << C_HCFS_SHIFT);
359 async_usleep(50000);
360 return;
361 }
362
363 const unsigned hc_status =
364 (instance->registers->control >> C_HCFS_SHIFT) & C_HCFS_MASK;
365 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
366 if (hc_status != C_HCFS_RESET) {
367 usb_log_debug("BIOS driver found.\n");
368 if (hc_status == C_HCFS_OPERATIONAL) {
369 usb_log_info("BIOS driver: HC operational.\n");
370 return;
371 }
372 /* HC is suspended assert resume for 20ms */
373 instance->registers->control &= (C_HCFS_RESUME << C_HCFS_SHIFT);
374 async_usleep(20000);
375 usb_log_info("BIOS driver: HC resumed.\n");
376 return;
377 }
378
379 /* HC is in reset (hw startup) => no other driver
380 * maintain reset for at least the time specified in USB spec (50 ms)*/
381 usb_log_info("HC found in reset.\n");
382 async_usleep(50000);
383}
384/*----------------------------------------------------------------------------*/
385void hc_start_hw(hc_t *instance)
386{
387 /* OHCI guide page 42 */
388 assert(instance);
389 usb_log_debug2("Started hc initialization routine.\n");
390
391 /* Save contents of fm_interval register */
392 const uint32_t fm_interval = instance->registers->fm_interval;
393 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
394
395 /* Reset hc */
396 usb_log_debug2("HC reset.\n");
397 size_t time = 0;
398 instance->registers->command_status = CS_HCR;
399 while (instance->registers->command_status & CS_HCR) {
400 async_usleep(10);
401 time += 10;
402 }
403 usb_log_debug2("HC reset complete in %zu us.\n", time);
404
405 /* Restore fm_interval */
406 instance->registers->fm_interval = fm_interval;
407 assert((instance->registers->command_status & CS_HCR) == 0);
408
409 /* hc is now in suspend state */
410 usb_log_debug2("HC should be in suspend state(%x).\n",
411 instance->registers->control);
412
413 /* Use HCCA */
414 instance->registers->hcca = addr_to_phys(instance->hcca);
415
416 /* Use queues */
417 instance->registers->bulk_head =
418 instance->lists[USB_TRANSFER_BULK].list_head_pa;
419 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
420 instance->lists[USB_TRANSFER_BULK].list_head,
421 instance->lists[USB_TRANSFER_BULK].list_head_pa);
422
423 instance->registers->control_head =
424 instance->lists[USB_TRANSFER_CONTROL].list_head_pa;
425 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
426 instance->lists[USB_TRANSFER_CONTROL].list_head,
427 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
428
429 /* Enable queues */
430 instance->registers->control |= (C_PLE | C_IE | C_CLE | C_BLE);
431 usb_log_debug2("All queues enabled(%x).\n",
432 instance->registers->control);
433
434 /* Enable interrupts */
435 instance->registers->interrupt_enable = OHCI_USED_INTERRUPTS;
436 usb_log_debug2("Enabled interrupts: %x.\n",
437 instance->registers->interrupt_enable);
438 instance->registers->interrupt_enable = I_MI;
439
440 /* Set periodic start to 90% */
441 uint32_t frame_length = ((fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK);
442 instance->registers->periodic_start = (frame_length / 10) * 9;
443 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
444 instance->registers->periodic_start,
445 instance->registers->periodic_start, frame_length);
446
447 instance->registers->control &= (C_HCFS_OPERATIONAL << C_HCFS_SHIFT);
448 usb_log_info("OHCI HC up and running(%x).\n",
449 instance->registers->control);
450}
451/*----------------------------------------------------------------------------*/
452int hc_init_transfer_lists(hc_t *instance)
453{
454 assert(instance);
455#define SETUP_ENDPOINT_LIST(type) \
456do { \
457 const char *name = usb_str_transfer_type(type); \
458 int ret = endpoint_list_init(&instance->lists[type], name); \
459 if (ret != EOK) { \
460 usb_log_error("Failed(%d) to setup %s endpoint list.\n", \
461 ret, name); \
462 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
463 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
464 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
465 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
466 } \
467} while (0)
468
469 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
470 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
471 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
472 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
473#undef SETUP_ENDPOINT_LIST
474 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
475 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
476
477 return EOK;
478}
479/*----------------------------------------------------------------------------*/
480int hc_init_memory(hc_t *instance)
481{
482 assert(instance);
483
484 bzero(&instance->rh, sizeof(instance->rh));
485 /* Init queues */
486 hc_init_transfer_lists(instance);
487
488 /*Init HCCA */
489 instance->hcca = malloc32(sizeof(hcca_t));
490 if (instance->hcca == NULL)
491 return ENOMEM;
492 bzero(instance->hcca, sizeof(hcca_t));
493 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
494
495 unsigned i = 0;
496 for (; i < 32; ++i) {
497 instance->hcca->int_ep[i] =
498 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa;
499 }
500 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
501 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
502 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
503
504 /* Init interrupt code */
505 instance->interrupt_code.cmds = instance->interrupt_commands;
506 {
507 /* Read status register */
508 instance->interrupt_commands[0].cmd = CMD_MEM_READ_32;
509 instance->interrupt_commands[0].dstarg = 1;
510 instance->interrupt_commands[0].addr =
511 (void*)&instance->registers->interrupt_status;
512
513 /* Test whether we are the interrupt cause */
514 instance->interrupt_commands[1].cmd = CMD_BTEST;
515 instance->interrupt_commands[1].value =
516 OHCI_USED_INTERRUPTS;
517 instance->interrupt_commands[1].srcarg = 1;
518 instance->interrupt_commands[1].dstarg = 2;
519
520 /* Predicate cleaning and accepting */
521 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
522 instance->interrupt_commands[2].value = 2;
523 instance->interrupt_commands[2].srcarg = 2;
524
525 /* Write clean status register */
526 instance->interrupt_commands[3].cmd = CMD_MEM_WRITE_A_32;
527 instance->interrupt_commands[3].srcarg = 1;
528 instance->interrupt_commands[3].addr =
529 (void*)&instance->registers->interrupt_status;
530
531 /* Accept interrupt */
532 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
533
534 instance->interrupt_code.cmdcount = OHCI_NEEDED_IRQ_COMMANDS;
535 }
536
537 return EOK;
538}
539/**
540 * @}
541 */
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