source: mainline/uspace/drv/ohci/hc.c@ 7ab7c7f6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7ab7c7f6 was 5d07f54, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Reset OHCI root hub even if taking control from SMM driver

postpone root hub registration
  • Property mode set to 100644
File size: 17.1 KB
RevLine 
[41b96b4]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohcihc
29 * @{
30 */
31/** @file
32 * @brief OHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
[ff582d47]42#include <usb/usbdevice.h>
[41b96b4]43
[bab71635]44#include "hc.h"
[2759c52]45#include "hcd_endpoint.h"
[41b96b4]46
[561112f]47#define OHCI_USED_INTERRUPTS \
48 (I_SO | I_WDH | I_UE | I_RHSC)
[7d6a676]49static int interrupt_emulator(hc_t *instance);
[2c617b0]50static void hc_gain_control(hc_t *instance);
[6b6e3ed3]51static int hc_init_transfer_lists(hc_t *instance);
[344925c]52static int hc_init_memory(hc_t *instance);
[a6d1bc1]53/*----------------------------------------------------------------------------*/
[53f1c87]54int hc_register_hub(hc_t *instance, ddf_fun_t *hub_fun)
55{
56 assert(instance);
57 assert(hub_fun);
58
[8148ee3a]59 int ret;
60
[53f1c87]61 usb_address_t hub_address =
62 device_keeper_get_free_address(&instance->manager, USB_SPEED_FULL);
[8148ee3a]63 if (hub_address <= 0) {
64 usb_log_error("Failed to get OHCI root hub address.\n");
65 return hub_address;
66 }
[53f1c87]67 instance->rh.address = hub_address;
68 usb_device_keeper_bind(
69 &instance->manager, hub_address, hub_fun->handle);
70
[9a6fde4]71 ret = hc_add_endpoint(instance, hub_address, 0, USB_SPEED_FULL,
72 USB_TRANSFER_CONTROL, USB_DIRECTION_BOTH, 64, 0, 0);
[8148ee3a]73 if (ret != EOK) {
74 usb_log_error("Failed to add OHCI rh endpoint 0.\n");
75 usb_device_keeper_release(&instance->manager, hub_address);
76 return ret;
77 }
[6bec59b]78
[53f1c87]79 char *match_str = NULL;
[8148ee3a]80 /* DDF needs heap allocated string */
[6bec59b]81 ret = asprintf(&match_str, "usb&class=hub");
[53f1c87]82 if (ret < 0) {
[6bec59b]83 usb_log_error(
84 "Failed(%d) to create root hub match-id string.\n", ret);
[8148ee3a]85 usb_device_keeper_release(&instance->manager, hub_address);
[53f1c87]86 return ret;
87 }
88
89 ret = ddf_fun_add_match_id(hub_fun, match_str, 100);
90 if (ret != EOK) {
[8148ee3a]91 usb_log_error("Failed add root hub match-id.\n");
[53f1c87]92 }
[5d07f54]93 ret = ddf_fun_bind(hub_fun);
[53f1c87]94 return ret;
95}
96/*----------------------------------------------------------------------------*/
[a6d1bc1]97int hc_init(hc_t *instance, ddf_fun_t *fun, ddf_dev_t *dev,
[e7bc999]98 uintptr_t regs, size_t reg_size, bool interrupts)
[41b96b4]99{
100 assert(instance);
[ff582d47]101 int ret = EOK;
[c2be0e5]102#define CHECK_RET_RETURN(ret, message...) \
103if (ret != EOK) { \
104 usb_log_error(message); \
105 return ret; \
106} else (void)0
[ff582d47]107
108 ret = pio_enable((void*)regs, reg_size, (void**)&instance->registers);
[c2be0e5]109 CHECK_RET_RETURN(ret,
110 "Failed(%d) to gain access to device registers: %s.\n",
111 ret, str_error(ret));
112
[bba0dc20]113 list_initialize(&instance->pending_batches);
[68b5ed6e]114 usb_device_keeper_init(&instance->manager);
[5876d36]115 ret = usb_endpoint_manager_init(&instance->ep_manager,
116 BANDWIDTH_AVAILABLE_USB11);
117 CHECK_RET_RETURN(ret, "Failed to initialize endpoint manager: %s.\n",
[4125b7d]118 str_error(ret));
[e7bc999]119
[8790650]120 ret = hc_init_memory(instance);
[4125b7d]121 CHECK_RET_RETURN(ret, "Failed to create OHCI memory structures: %s.\n",
122 str_error(ret));
[bba0dc20]123#undef CHECK_RET_RETURN
124
125
[f1d16663]126// hc_init_hw(instance);
[bba0dc20]127 hc_gain_control(instance);
[aa9ccf7]128 fibril_mutex_initialize(&instance->guard);
[2c617b0]129
[8148ee3a]130 rh_init(&instance->rh, instance->registers);
[ff582d47]131
[ff0e354]132 if (!interrupts) {
133 instance->interrupt_emulator =
134 fibril_create((int(*)(void*))interrupt_emulator, instance);
135 fibril_add_ready(instance->interrupt_emulator);
136 }
[7013b14]137
[8627377]138 return EOK;
[a6d1bc1]139}
140/*----------------------------------------------------------------------------*/
[6bb0f43]141int hc_add_endpoint(
142 hc_t *instance, usb_address_t address, usb_endpoint_t endpoint,
143 usb_speed_t speed, usb_transfer_type_t type, usb_direction_t direction,
144 size_t mps, size_t size, unsigned interval)
145{
146 endpoint_t *ep = malloc(sizeof(endpoint_t));
147 if (ep == NULL)
148 return ENOMEM;
149 int ret =
150 endpoint_init(ep, address, endpoint, direction, type, speed, mps);
151 if (ret != EOK) {
152 free(ep);
153 return ret;
154 }
155
[2759c52]156 hcd_endpoint_t *hcd_ep = hcd_endpoint_assign(ep);
157 if (hcd_ep == NULL) {
[592369ae]158 endpoint_destroy(ep);
[2759c52]159 return ENOMEM;
160 }
161
[6bb0f43]162 ret = usb_endpoint_manager_register_ep(&instance->ep_manager, ep, size);
163 if (ret != EOK) {
[592369ae]164 hcd_endpoint_clear(ep);
[6bb0f43]165 endpoint_destroy(ep);
[5a2c42b]166 return ret;
167 }
168
169 /* Enqueue hcd_ep */
170 switch (ep->transfer_type) {
171 case USB_TRANSFER_CONTROL:
172 instance->registers->control &= ~C_CLE;
173 endpoint_list_add_ep(
174 &instance->lists[ep->transfer_type], hcd_ep);
175 instance->registers->control_current = 0;
176 instance->registers->control |= C_CLE;
177 break;
178 case USB_TRANSFER_BULK:
179 instance->registers->control &= ~C_BLE;
180 endpoint_list_add_ep(
181 &instance->lists[ep->transfer_type], hcd_ep);
182 instance->registers->control |= C_BLE;
183 break;
184 case USB_TRANSFER_ISOCHRONOUS:
185 case USB_TRANSFER_INTERRUPT:
186 instance->registers->control &= (~C_PLE & ~C_IE);
187 endpoint_list_add_ep(
188 &instance->lists[ep->transfer_type], hcd_ep);
189 instance->registers->control |= C_PLE | C_IE;
190 break;
191 default:
192 break;
[6bb0f43]193 }
[5a2c42b]194
[592369ae]195 return EOK;
[6bb0f43]196}
197/*----------------------------------------------------------------------------*/
198int hc_remove_endpoint(hc_t *instance, usb_address_t address,
199 usb_endpoint_t endpoint, usb_direction_t direction)
200{
[592369ae]201 assert(instance);
202 fibril_mutex_lock(&instance->guard);
[2759c52]203 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
204 address, endpoint, direction, NULL);
205 if (ep == NULL) {
[592369ae]206 usb_log_error("Endpoint unregister failed: No such EP.\n");
207 fibril_mutex_unlock(&instance->guard);
[2759c52]208 return ENOENT;
209 }
210
211 hcd_endpoint_t *hcd_ep = hcd_endpoint_get(ep);
212 if (hcd_ep) {
[5a2c42b]213 /* Dequeue hcd_ep */
214 switch (ep->transfer_type) {
215 case USB_TRANSFER_CONTROL:
216 instance->registers->control &= ~C_CLE;
217 endpoint_list_remove_ep(
218 &instance->lists[ep->transfer_type], hcd_ep);
219 instance->registers->control_current = 0;
220 instance->registers->control |= C_CLE;
221 break;
222 case USB_TRANSFER_BULK:
223 instance->registers->control &= ~C_BLE;
224 endpoint_list_remove_ep(
225 &instance->lists[ep->transfer_type], hcd_ep);
226 instance->registers->control |= C_BLE;
227 break;
228 case USB_TRANSFER_ISOCHRONOUS:
229 case USB_TRANSFER_INTERRUPT:
230 instance->registers->control &= (~C_PLE & ~C_IE);
231 endpoint_list_remove_ep(
232 &instance->lists[ep->transfer_type], hcd_ep);
233 instance->registers->control |= C_PLE | C_IE;
234 break;
235 default:
236 break;
237 }
[2759c52]238 hcd_endpoint_clear(ep);
239 } else {
240 usb_log_warning("Endpoint without hcd equivalent structure.\n");
241 }
[592369ae]242 int ret = usb_endpoint_manager_unregister_ep(&instance->ep_manager,
[6bb0f43]243 address, endpoint, direction);
[592369ae]244 fibril_mutex_unlock(&instance->guard);
245 return ret;
246}
247/*----------------------------------------------------------------------------*/
248endpoint_t * hc_get_endpoint(hc_t *instance, usb_address_t address,
249 usb_endpoint_t endpoint, usb_direction_t direction, size_t *bw)
250{
251 assert(instance);
252 fibril_mutex_lock(&instance->guard);
253 endpoint_t *ep = usb_endpoint_manager_get_ep(&instance->ep_manager,
254 address, endpoint, direction, bw);
255 fibril_mutex_unlock(&instance->guard);
256 return ep;
[6bb0f43]257}
258/*----------------------------------------------------------------------------*/
[1387692]259int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
[41b96b4]260{
261 assert(instance);
262 assert(batch);
[d017cea]263 assert(batch->ep);
[9ff5ff82]264
265 /* check for root hub communication */
[d017cea]266 if (batch->ep->address == instance->rh.address) {
[2bf8f8c]267 return rh_request(&instance->rh, batch);
[41b96b4]268 }
[7013b14]269
[aa9ccf7]270 fibril_mutex_lock(&instance->guard);
[7013b14]271 list_append(&batch->link, &instance->pending_batches);
272 batch_commit(batch);
[d017cea]273 switch (batch->ep->transfer_type) {
[9ff5ff82]274 case USB_TRANSFER_CONTROL:
275 instance->registers->command_status |= CS_CLF;
276 break;
277 case USB_TRANSFER_BULK:
278 instance->registers->command_status |= CS_BLF;
279 break;
280 default:
281 break;
282 }
[7013b14]283
[aa9ccf7]284 fibril_mutex_unlock(&instance->guard);
[4c28d17]285 return EOK;
[41b96b4]286}
287/*----------------------------------------------------------------------------*/
[7d6a676]288void hc_interrupt(hc_t *instance, uint32_t status)
[41b96b4]289{
290 assert(instance);
[5d07f54]291 usb_log_debug("OHCI(%p) interrupt: %x.\n", instance, status);
[561112f]292 if ((status & ~I_SF) == 0) /* ignore sof status */
[eaf1e3d]293 return;
[561112f]294 if (status & I_RHSC)
[7d6a676]295 rh_interrupt(&instance->rh);
296
[eaf1e3d]297
[561112f]298 if (status & I_WDH) {
[aa9ccf7]299 fibril_mutex_lock(&instance->guard);
[4125b7d]300 usb_log_debug2("HCCA: %p-%#" PRIx32 " (%p).\n", instance->hcca,
301 instance->registers->hcca,
302 (void *) addr_to_phys(instance->hcca));
303 usb_log_debug2("Periodic current: %#" PRIx32 ".\n",
[aa9ccf7]304 instance->registers->periodic_current);
[eaf1e3d]305
[7013b14]306 link_t *current = instance->pending_batches.next;
307 while (current != &instance->pending_batches) {
308 link_t *next = current->next;
[eaf1e3d]309 usb_transfer_batch_t *batch =
[7013b14]310 usb_transfer_batch_from_link(current);
311
312 if (batch_is_complete(batch)) {
[d6522dd]313 list_remove(current);
[7013b14]314 usb_transfer_batch_finish(batch);
315 }
316 current = next;
[eaf1e3d]317 }
[aa9ccf7]318 fibril_mutex_unlock(&instance->guard);
[4c28d17]319 }
[41b96b4]320}
[7d6a676]321/*----------------------------------------------------------------------------*/
[53f1c87]322int interrupt_emulator(hc_t *instance)
[7d6a676]323{
324 assert(instance);
325 usb_log_info("Started interrupt emulator.\n");
326 while (1) {
[2c617b0]327 const uint32_t status = instance->registers->interrupt_status;
[7d6a676]328 instance->registers->interrupt_status = status;
329 hc_interrupt(instance, status);
[aa9ccf7]330 async_usleep(50000);
[7d6a676]331 }
332 return EOK;
333}
[2c617b0]334/*----------------------------------------------------------------------------*/
335void hc_gain_control(hc_t *instance)
336{
337 assert(instance);
[c8eddf4]338 usb_log_debug("Requesting OHCI control.\n");
[112d159]339 /* Turn off legacy emulation */
340 volatile uint32_t *ohci_emulation_reg =
341 (uint32_t*)((char*)instance->registers + 0x100);
342 usb_log_debug("OHCI legacy register %p: %x.\n",
[bba0dc20]343 ohci_emulation_reg, *ohci_emulation_reg);
344 /* Do not change A20 state */
345 *ohci_emulation_reg &= 0x100;
346 usb_log_debug("OHCI legacy register %p: %x.\n",
347 ohci_emulation_reg, *ohci_emulation_reg);
[112d159]348
[2c617b0]349 /* Interrupt routing enabled => smm driver is active */
350 if (instance->registers->control & C_IR) {
[112d159]351 usb_log_debug("SMM driver: request ownership change.\n");
[2c617b0]352 instance->registers->command_status |= CS_OCR;
353 while (instance->registers->control & C_IR) {
354 async_usleep(1000);
355 }
[112d159]356 usb_log_info("SMM driver: Ownership taken.\n");
[5d07f54]357 instance->registers->control &= (C_HCFS_RESET << C_HCFS_SHIFT);
358 async_usleep(50000);
[2c617b0]359 return;
360 }
361
362 const unsigned hc_status =
363 (instance->registers->control >> C_HCFS_SHIFT) & C_HCFS_MASK;
364 /* Interrupt routing disabled && status != USB_RESET => BIOS active */
365 if (hc_status != C_HCFS_RESET) {
[112d159]366 usb_log_debug("BIOS driver found.\n");
[2c617b0]367 if (hc_status == C_HCFS_OPERATIONAL) {
[112d159]368 usb_log_info("BIOS driver: HC operational.\n");
[2c617b0]369 return;
370 }
371 /* HC is suspended assert resume for 20ms */
372 instance->registers->control &= (C_HCFS_RESUME << C_HCFS_SHIFT);
373 async_usleep(20000);
[112d159]374 usb_log_info("BIOS driver: HC resumed.\n");
[2c617b0]375 return;
376 }
377
378 /* HC is in reset (hw startup) => no other driver
379 * maintain reset for at least the time specified in USB spec (50 ms)*/
[112d159]380 usb_log_info("HC found in reset.\n");
[2c617b0]381 async_usleep(50000);
382}
383/*----------------------------------------------------------------------------*/
[f1d16663]384void hc_start_hw(hc_t *instance)
[2c617b0]385{
[112d159]386 /* OHCI guide page 42 */
[2c617b0]387 assert(instance);
[112d159]388 usb_log_debug2("Started hc initialization routine.\n");
389
390 /* Save contents of fm_interval register */
[2c617b0]391 const uint32_t fm_interval = instance->registers->fm_interval;
[112d159]392 usb_log_debug2("Old value of HcFmInterval: %x.\n", fm_interval);
[344925c]393
[112d159]394 /* Reset hc */
395 usb_log_debug2("HC reset.\n");
396 size_t time = 0;
[2c617b0]397 instance->registers->command_status = CS_HCR;
[112d159]398 while (instance->registers->command_status & CS_HCR) {
399 async_usleep(10);
400 time += 10;
401 }
402 usb_log_debug2("HC reset complete in %zu us.\n", time);
[344925c]403
[112d159]404 /* Restore fm_interval */
[2c617b0]405 instance->registers->fm_interval = fm_interval;
406 assert((instance->registers->command_status & CS_HCR) == 0);
[344925c]407
[2c617b0]408 /* hc is now in suspend state */
[112d159]409 usb_log_debug2("HC should be in suspend state(%x).\n",
410 instance->registers->control);
[344925c]411
[78d4e1f]412 /* Use HCCA */
413 instance->registers->hcca = addr_to_phys(instance->hcca);
414
415 /* Use queues */
[5a2c42b]416 instance->registers->bulk_head =
417 instance->lists[USB_TRANSFER_BULK].list_head_pa;
[4125b7d]418 usb_log_debug2("Bulk HEAD set to: %p (%#" PRIx32 ").\n",
[5a2c42b]419 instance->lists[USB_TRANSFER_BULK].list_head,
420 instance->lists[USB_TRANSFER_BULK].list_head_pa);
[78d4e1f]421
422 instance->registers->control_head =
[5a2c42b]423 instance->lists[USB_TRANSFER_CONTROL].list_head_pa;
[4125b7d]424 usb_log_debug2("Control HEAD set to: %p (%#" PRIx32 ").\n",
[5a2c42b]425 instance->lists[USB_TRANSFER_CONTROL].list_head,
426 instance->lists[USB_TRANSFER_CONTROL].list_head_pa);
[78d4e1f]427
[112d159]428 /* Enable queues */
[344925c]429 instance->registers->control |= (C_PLE | C_IE | C_CLE | C_BLE);
[112d159]430 usb_log_debug2("All queues enabled(%x).\n",
431 instance->registers->control);
432
[561112f]433 /* Enable interrupts */
434 instance->registers->interrupt_enable = OHCI_USED_INTERRUPTS;
[112d159]435 usb_log_debug2("Enabled interrupts: %x.\n",
436 instance->registers->interrupt_enable);
[561112f]437 instance->registers->interrupt_enable = I_MI;
[112d159]438
439 /* Set periodic start to 90% */
440 uint32_t frame_length = ((fm_interval >> FMI_FI_SHIFT) & FMI_FI_MASK);
441 instance->registers->periodic_start = (frame_length / 10) * 9;
442 usb_log_debug2("All periodic start set to: %x(%u - 90%% of %d).\n",
443 instance->registers->periodic_start,
444 instance->registers->periodic_start, frame_length);
[2c617b0]445
446 instance->registers->control &= (C_HCFS_OPERATIONAL << C_HCFS_SHIFT);
[112d159]447 usb_log_info("OHCI HC up and running(%x).\n",
448 instance->registers->control);
[2c617b0]449}
[6b6e3ed3]450/*----------------------------------------------------------------------------*/
451int hc_init_transfer_lists(hc_t *instance)
452{
453 assert(instance);
[344925c]454
[5a2c42b]455#define SETUP_ENDPOINT_LIST(type) \
[344925c]456do { \
[5a2c42b]457 const char *name = usb_str_transfer_type(type); \
458 int ret = endpoint_list_init(&instance->lists[type], name); \
[6b6e3ed3]459 if (ret != EOK) { \
[5a2c42b]460 usb_log_error("Failed(%d) to setup %s endpoint list.\n", \
[344925c]461 ret, name); \
[5a2c42b]462 endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]); \
463 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
464 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \
465 endpoint_list_fini(&instance->lists[USB_TRANSFER_BULK]); \
[344925c]466 } \
467} while (0)
[6b6e3ed3]468
[5a2c42b]469 SETUP_ENDPOINT_LIST(USB_TRANSFER_ISOCHRONOUS);
470 SETUP_ENDPOINT_LIST(USB_TRANSFER_INTERRUPT);
471 SETUP_ENDPOINT_LIST(USB_TRANSFER_CONTROL);
472 SETUP_ENDPOINT_LIST(USB_TRANSFER_BULK);
473#undef SETUP_ENDPOINT_LIST
474 endpoint_list_set_next(&instance->lists[USB_TRANSFER_INTERRUPT],
475 &instance->lists[USB_TRANSFER_ISOCHRONOUS]);
[6b6e3ed3]476
477 return EOK;
478}
[344925c]479/*----------------------------------------------------------------------------*/
480int hc_init_memory(hc_t *instance)
481{
482 assert(instance);
[5d07f54]483
484 bzero(&instance->rh, sizeof(instance->rh));
[8790650]485 /* Init queues */
[344925c]486 hc_init_transfer_lists(instance);
487
[8790650]488 /*Init HCCA */
[344925c]489 instance->hcca = malloc32(sizeof(hcca_t));
490 if (instance->hcca == NULL)
491 return ENOMEM;
492 bzero(instance->hcca, sizeof(hcca_t));
[78d4e1f]493 usb_log_debug2("OHCI HCCA initialized at %p.\n", instance->hcca);
[344925c]494
495 unsigned i = 0;
496 for (; i < 32; ++i) {
497 instance->hcca->int_ep[i] =
[5a2c42b]498 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa;
[344925c]499 }
[4125b7d]500 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
[5a2c42b]501 instance->lists[USB_TRANSFER_INTERRUPT].list_head,
502 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
[344925c]503
[561112f]504 /* Init interrupt code */
505 instance->interrupt_code.cmds = instance->interrupt_commands;
506 {
507 /* Read status register */
508 instance->interrupt_commands[0].cmd = CMD_MEM_READ_32;
509 instance->interrupt_commands[0].dstarg = 1;
[03cfda08]510 instance->interrupt_commands[0].addr =
511 (void*)&instance->registers->interrupt_status;
[561112f]512
513 /* Test whether we are the interrupt cause */
514 instance->interrupt_commands[1].cmd = CMD_BTEST;
515 instance->interrupt_commands[1].value =
516 OHCI_USED_INTERRUPTS;
517 instance->interrupt_commands[1].srcarg = 1;
518 instance->interrupt_commands[1].dstarg = 2;
519
520 /* Predicate cleaning and accepting */
521 instance->interrupt_commands[2].cmd = CMD_PREDICATE;
522 instance->interrupt_commands[2].value = 2;
523 instance->interrupt_commands[2].srcarg = 2;
524
525 /* Write clean status register */
[03cfda08]526 instance->interrupt_commands[3].cmd = CMD_MEM_WRITE_A_32;
[561112f]527 instance->interrupt_commands[3].srcarg = 1;
[03cfda08]528 instance->interrupt_commands[3].addr =
529 (void*)&instance->registers->interrupt_status;
[561112f]530
531 /* Accept interrupt */
532 instance->interrupt_commands[4].cmd = CMD_ACCEPT;
533
534 instance->interrupt_code.cmdcount = OHCI_NEEDED_IRQ_COMMANDS;
535 }
536
[344925c]537 return EOK;
538}
[41b96b4]539/**
540 * @}
541 */
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