| 1 | /*
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| 2 | * Copyright (c) 2014 Agnieszka Tabaka
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| 3 | * Copyright (c) 2011 Jiri Michalec
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @file rtl8169_defs.h
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| 31 | *
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| 32 | * Registers, bit positions and masks definition
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| 33 | * of the RTL8169 network family cards
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| 34 | */
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| 35 |
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| 36 | #ifndef RTL8169_DEFS_H_
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| 37 | #define RTL8169_DEFS_H_
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| 38 |
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| 39 | #include <sys/types.h>
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| 40 | #include <ddi.h>
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| 41 |
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| 42 | #define PCI_VID_REALTEK 0x10ec
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| 43 | #define PCI_VID_DLINK 0x1186
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| 44 |
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| 45 | /** Size of RTL8169 registers address space */
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| 46 | #define RTL8169_IO_SIZE 256
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| 47 |
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| 48 | #define RTL8169_FRAME_MAX_LENGTH 1518
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| 49 |
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| 50 | /** Registers of RTL8169 family card offsets from the memory address base */
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| 51 | enum rtl8169_registers {
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| 52 | IDR0 = 0x00, /**< First MAC address bit, 6 1b registres sequence */
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| 53 | MAC0 = IDR0, /**< Alias for IDR0 */
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| 54 | /* 0x06 - 0x07 reserved */
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| 55 | MAR0 = 0x08, /**< Multicast mask registers 8 1b registers sequence */
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| 56 | DTCCR = 0x10, /**< Dump Tally Counter Command Register */
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| 57 | TNPDS = 0x20, /**< Transmit Normal Priority Descriptors */
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| 58 | THPDS = 0x28, /**< Transmit High Priority Descriptors */
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| 59 | FLASH = 0x30, /**< Flash memory read/write register */
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| 60 | ERBCR = 0x34, /**< Early Receive Byte Count Register */
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| 61 | ERSR = 0x36, /**< Early Rx Status Register */
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| 62 | CR = 0x37, /**< Command register, 1b */
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| 63 | TPPOLL = 0x38, /**< Transmit Priority Polling Register */
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| 64 | CBA = 0x3a, /**< Current buffer address, 2b */
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| 65 | IMR = 0x3c, /**< Interrupt mask register, 2b */
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| 66 | ISR = 0x3e, /**< Interrupt status register, 2b */
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| 67 | TCR = 0x40, /**< Transmit (Tx) configuration register, 4b */
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| 68 | RCR = 0x44, /**< Receive (Rx) configuration register, 4b */
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| 69 | TCTR = 0x48, /**< Timer count register */
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| 70 | MPC = 0x4c, /**< Missed packet count */
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| 71 | CR9346 = 0x50, /**< 93C46 command register (locking of registers) */
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| 72 | CONFIG0 = 0x51, /**< Configuration register 0, 1b */
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| 73 | CONFIG1 = 0x52, /**< Configuration register 1, 1b */
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| 74 | CONFIG2 = 0x53, /**< Configuration register 2, 1b */
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| 75 | CONFIG3 = 0x54, /**< Configuration register 3, 1b */
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| 76 | CONFIG4 = 0x55, /**< Configuration register 4, 1b */
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| 77 | CONFIG5 = 0x56, /**< Configuration register 5, 1b */
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| 78 | /* 0x57 reserved */
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| 79 | TIMINT = 0x58, /**< Timer interrupt register, 4b */
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| 80 | MULINT = 0x58, /**< Multiple interrupt select, 4b */
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| 81 | /* 0x5e-0x5f reserved */
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| 82 | PHYAR = 0x60, /**< PHY Access Register, 4b */
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| 83 | TBICSR0 = 0x64, /**< TBI Control and Status Register, 4b */
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| 84 | TBI_ANAR = 0x58, /**< TBI Auto-Negotiation Advertisement Register, 2b */
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| 85 | TBI_LPAR = 0x6a, /**< TBI Auto-Negotiation Link Partner Ability Register, 2b */
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| 86 | PHYSTATUS = 0x6c, /**< PHY Status Register */
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| 87 | /* 0x6d-0x83 reserved */
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| 88 | WAKEUP0 = 0x84, /**< Power Management Wakeup frame0, 8b */
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| 89 | WAKEUP1 = 0x8c, /**< Power Management Wakeup frame1, 8b */
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| 90 | WAKEUP2LD = 0x94, /**< Power Management Wakeup frame2 low dword, 8b */
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| 91 | WAKEUP2HD = 0x9c, /**< Power Management Wakeup frame2 high dword, 8b */
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| 92 | WAKEUP3LD = 0xa4, /**< Power Management Wakeup frame3 low dword, 8b */
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| 93 | WAKEUP3HD = 0xac, /**< Power Management Wakeup frame3 high dword, 8b */
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| 94 | WAKEUP4LD = 0xb4, /**< Power Management Wakeup frame4 low dword, 8b */
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| 95 | WAKEUP4HD = 0xbc, /**< Power Management Wakeup frame4 high dword, 8b */
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| 96 | CRC0 = 0xc4, /**< 16-bit CRC of wakeup frame 0, 2b */
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| 97 | CRC1 = 0xc6, /**< 16-bit CRC of wakeup frame 1, 2b */
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| 98 | CRC2 = 0xc8, /**< 16-bit CRC of wakeup frame 2, 2b */
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| 99 | CRC3 = 0xca, /**< 16-bit CRC of wakeup frame 3, 2b */
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| 100 | CRC4 = 0xcc, /**< 16-bit CRC of wakeup frame 4, 2b */
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| 101 | /* 0xce - 0xd9 reserved */
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| 102 | RMS = 0xda, /**< Rx packet Maximum Size, 2b */
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| 103 | /* 0xdc - 0xdf reserved */
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| 104 | CCR = 0xe0, /**< C+ Command Register */
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| 105 | /* 0xe2 - 0xe3 reserved */
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| 106 | RDSAR = 0xe4, /**< Receive Descriptor Start Address Register, 8b */
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| 107 | ETTHR = 0xec, /**< Early Transmit Threshold Register, 1b */
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| 108 | /* 0xed - 0xef reserved */
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| 109 | FER = 0xf0, /**< Function Event Register, 4b */
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| 110 | FEMR = 0xf4, /**< Function Event Mask Register, 4b */
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| 111 | FPSR = 0xf8, /**< Function Preset State Register, 4b */
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| 112 | FFER = 0xfc, /**< Function Force Event Register, 4b */
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| 113 | };
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| 114 |
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| 115 | enum rtl8169_mii_registers {
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| 116 | MII_BMCR = 0x00,
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| 117 | MII_BMSR = 0x01,
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| 118 | MII_ANAR = 0x04,
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| 119 | };
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| 120 |
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| 121 | /** Command register bits */
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| 122 | enum rtl8169_cr {
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| 123 | CR_TE = (1 << 2), /**< Transmitter enable bit */
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| 124 | CR_RE = (1 << 3), /**< Receiver enable bit */
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| 125 | CR_RST = (1 << 4), /**< Reset - set to 1 to force software reset */
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| 126 | };
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| 127 |
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| 128 | /** Config1 register bits */
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| 129 | enum rtl8169_config1 {
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| 130 | CONFIG1_LEDS_SHIFT = 6, /**< Shift of CONFIG1_LEDS bits */
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| 131 | CONFIG1_LEDS_SIZE = 2, /**< Size of CONFIG1_LEDS bits */
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| 132 | CONFIG1_DVRLOAD = (1 << 5), /**< Driver load */
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| 133 | CONFIG1_LWACT = (1 << 4), /**< LWAKE active mode */
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| 134 | CONFIG1_MEMMAP = (1 << 3), /**< Memory mapping */
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| 135 | CONFIG1_IOMAP = (1 << 2), /**< I/O space mapping */
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| 136 | CONFIG1_VPD = (1 << 1), /**< Set to enable Vital Product Data */
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| 137 | CONFIG1_PMEn = (1 << 0) /**< Power management enabled */
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| 138 | };
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| 139 |
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| 140 | enum rtl8169_config2 {
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| 141 | CONFIG2_AUXSTATUS = (1 << 4), /**< Auxiliary Power Present Status */
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| 142 | CONFIG2_PCIBUSWIDTH = (1 << 3), /**< PCI Bus Width */
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| 143 | CONFIG2_PCICLKF_SHIFT = 0,
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| 144 | CONFIG2_PCICLKF_SIZE = 2
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| 145 | };
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| 146 |
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| 147 | enum rtl8169_config3 {
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| 148 | CONFIG3_GNT_SELECT = (1 << 7), /**< Gnt select */
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| 149 | CONFIG3_PARM_EN = (1 << 6), /**< Parameter enabled (100MBit mode) */
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| 150 | CONFIG3_MAGIC = (1 << 5), /**< WoL Magic frame enable */
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| 151 | CONFIG3_LINK_UP = (1 << 4), /**< Wakeup if link is reestablished */
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| 152 | CONFIG3_CLKRUN_EN = (1 << 2), /**< CLKRUN enabled */ /* TODO: check what does it mean */
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| 153 | CONFIG3_FBTBEN = (1 << 0), /**< Fast back to back enabled */
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| 154 | };
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| 155 |
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| 156 | enum rtl8169_config4 {
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| 157 | CONFIG4_RxFIFOAutoClr = (1 << 7), /**< Automatic RxFIFO owerflow clear */
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| 158 | CONFIG4_AnaOff = (1 << 6), /**< Analog poweroff */
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| 159 | CONFIG4_LongWF = (1 << 5), /**< Long wakeup frame */
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| 160 | CONFIG4_LWPME = (1 << 4), /**< LWAKE and PMEB assertion */
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| 161 | CONFIG4_LWPTN = (1 << 2), /**< LWake pattern */
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| 162 | CONFIG4_PBWakeup = (1 << 0), /**< Preboot wakeup */
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| 163 | };
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| 164 |
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| 165 | enum rtl8169_config5 {
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| 166 | CONFIG5_BROADCAST_WAKEUP = (1 << 6), /**< Broadcast wakeup frame enable */
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| 167 | CONFIG5_MULTICAST_WAKEUP = (1 << 5), /**< Multicast wakeup frame enable */
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| 168 | CONFIG5_UNICAST_WAKEUP = (1 << 4), /**< Unicast wakeup frame enable */
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| 169 | /* Bits 3-2 reserved */
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| 170 | CONFIG5_LAN_WAKE = (1 << 1), /**< LANWake signal enabled */
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| 171 | CONFIG5_PME_STATUS = (1 << 0), /**< PMEn change: 0 = SW, 1 = SW+PCI */
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| 172 | };
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| 173 |
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| 174 | /** Interrupt_masks
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| 175 | *
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| 176 | * The masks are the same for both IMR and ISR
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| 177 | */
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| 178 | enum rtl8169_interrupts {
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| 179 | INT_SERR = (1 << 15), /**< System error interrupt */
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| 180 | INT_TIME_OUT = (1 << 14), /**< Time out interrupt */
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| 181 | /* Bits 9 - 13 reserved */
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| 182 | INT_SW = (1 << 8), /**< Software Interrupt */
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| 183 | INT_TDU = (1 << 7), /**< Tx Descriptor Unvailable */
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| 184 | INT_FIFOOVW = (1 << 6), /**< Receiver FIFO overflow interrupt */
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| 185 | INT_PUN = (1 << 5), /**< Packet Underrun/Link Change Interrupt */
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| 186 | INT_RXOVW = (1 << 4), /**< Receiver buffer overflow */
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| 187 | INT_TER = (1 << 3), /**< Transmit error interrupt */
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| 188 | INT_TOK = (1 << 2), /**< Transmit OK interrupt */
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| 189 | INT_RER = (1 << 1), /**< Receive error interrupt */
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| 190 | INT_ROK = (1 << 0), /**< Receive OK interrupt */
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| 191 | INT_KNOWN = (INT_SERR | INT_TIME_OUT | INT_SW | INT_TDU \
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| 192 | | INT_FIFOOVW | INT_PUN | INT_RXOVW | INT_TER \
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| 193 | | INT_TOK| INT_RER | INT_ROK),
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| 194 | };
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| 195 |
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| 196 | /** Transmit status descriptor registers bits */
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| 197 | enum rtl8169_tsd {
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| 198 | TSD_CRS = (1 << 31), /**< Carrier Sense Lost */
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| 199 | TSD_TABT = (1 << 30), /**< Transmit Abort */
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| 200 | TSD_OWC = (1 << 29), /**< Out of Window Collision */
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| 201 | TSD_CDH = (1 << 28), /**< CD Heart Beat */
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| 202 | TSD_NCC_SHIFT = 24, /**< Collision Count - bit shift */
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| 203 | TSD_NCC_SIZE = 4, /**< Collision Count - bit size */
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| 204 | TSD_NCC_MASK = (1 << 4)-1, /**< Collision Count - bit size */
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| 205 | TSD_ERTXTH_SHIFT = 16, /**< Early Tx Threshold - bit shift */
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| 206 | TSD_ERTXTH_SIZE = 6, /**< Early Tx Treshold - bit size */
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| 207 | TSD_TOK = (1 << 15), /**< Transmit OK */
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| 208 | TSD_TUN = (1 << 14), /**< Transmit FIFO Underrun */
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| 209 | TSD_OWN = (1 << 13), /**< OWN */
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| 210 | TSD_SIZE_SHIFT = 0, /**< Size - bit shift */
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| 211 | TSD_SIZE_SIZE = 13, /**< Size - bit size */
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| 212 | TSD_SIZE_MASK = 0x1fff, /**< Size - bit mask */
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| 213 | };
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| 214 |
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| 215 | /** Receiver control register values */
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| 216 | enum rtl8169_rcr {
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| 217 | RCR_MulERINT = 1 << 24, /**< Multiple early interrupt select */
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| 218 | /* Bits 23-17 reserved */
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| 219 | RCR_RER8 = 1 << 16,
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| 220 | RCR_RXFTH_SHIFT = 13, /**< Rx FIFO treshold part shitf */
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| 221 | RCR_RXFTH_SIZE = 3, /**< Rx FIFO treshold part size */
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| 222 | /* Bits 12-11 reserved */
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| 223 | RCR_MXDMA_SHIFT = 8, /**< Max DMA Burst Size part shift */
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| 224 | RCR_MXDMA_SIZE = 3, /**< Max DMA Burst Size part size */
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| 225 | /* Bit 7 reserved */
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| 226 | RCR_ACCEPT_ERROR = 1 << 5, /**< Accept error frame */
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| 227 | RCR_ACCEPT_RUNT = 1 << 4, /**< Accept Runt (8-64 bytes) frames */
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| 228 | RCR_ACCEPT_BROADCAST = 1 << 3, /**< Accept broadcast */
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| 229 | RCR_ACCEPT_MULTICAST = 1 << 2, /**< Accept multicast */
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| 230 | RCR_ACCEPT_PHYS_MATCH = 1 << 1, /**< Accept device MAC address match */
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| 231 | RCR_ACCEPT_ALL_PHYS = 1 << 0, /**< Accept all frames with phys. desticnation */
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| 232 | RCR_ACCEPT_MASK = (1 << 6) - 1 /**< Mask of accept part */
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| 233 | };
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| 234 |
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| 235 | enum rtl8169_cr9346 {
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| 236 | CR9346EEM1_SHIFT = 6, /**< RTL8169 operating mode shift */
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| 237 | CR9346EEM1_SIZE = 2, /**< RTL8169 operating mode mask */
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| 238 | /* Bits 5-4 reserved */
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| 239 | EECS = (1 << 3), /**< EECS pin of 93C46 */
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| 240 | EESK = (1 << 2), /**< EESK pin of 93C46 */
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| 241 | EEDI = (1 << 1), /**< EEDI pin of 93C46 */
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| 242 | EEDO = (1 << 0), /**< EEDO pin of 93C46 */
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| 243 | };
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| 244 |
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| 245 | /** Auto-negotiation advertisement register */
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| 246 | enum rtl8169_anar {
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| 247 | ANAR_NEXT_PAGE = (1 << 15), /**< Next page bit, 0 - primary capability */
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| 248 | ANAR_ACK = (1 << 14), /**< Capability reception acknowledge */
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| 249 | ANAR_REMOTE_FAULT = (1 << 13), /**< Remote fault detection capability */
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| 250 | ANAR_PAUSE = (1 << 10), /**< Symetric pause frame capability */
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| 251 | ANAR_100T4 = (1 << 9), /**< T4, not supported by the device */
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| 252 | ANAR_100TX_FD = (1 << 8), /**< 100BASE_TX full duplex */
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| 253 | ANAR_100TX_HD = (1 << 7), /**< 100BASE_TX half duplex */
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| 254 | ANAR_10_FD = (1 << 6), /**< 10BASE_T full duplex */
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| 255 | ANAR_10_HD = (1 << 5), /**< 10BASE_T half duplex */
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| 256 | ANAR_SELECTOR = 0x1, /**< Selector */
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| 257 | };
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| 258 |
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| 259 | enum rtl8169_phystatus {
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| 260 | PHYSTATUS_TBIEN = (1 << 7), /**< TBI enabled */
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| 261 | PHYSTATUS_TXFLOW = (1 << 6), /**< TX flow control enabled */
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| 262 | PHYSTATUS_RXFLOW = (1 << 5), /**< RX flow control enabled */
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| 263 | PHYSTATUS_1000M = (1 << 4), /**< Link speed is 1000Mbit/s */
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| 264 | PHYSTATUS_100M = (1 << 3), /**< Link speed is 100Mbit/s */
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| 265 | PHYSTATUS_10M = (1 << 2), /**< Link speed is 10Mbit/s */
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| 266 | PHYSTATUS_LINK = (1 << 1), /**< Link up */
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| 267 | PHYSTATUS_FDX = (1 << 0), /**< Link is full duplex */
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| 268 | };
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| 269 |
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| 270 | enum rtl8169_tppoll {
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| 271 | TPPOLL_HPQ = (1 << 7), /**< Start transmit on high priority queue */
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| 272 | TPPOLL_NPQ = (1 << 6), /**< Start transmit on normal queue */
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| 273 | /* Bits 5-1 reserved */
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| 274 | TPPOLL_FSWINT = (1 << 0), /** < Generate software interrupt */
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| 275 | };
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| 276 |
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| 277 | enum rtl8169_phyar {
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| 278 | PHYAR_RW_SHIFT = 31, /**< Read (0) or write (1) command */
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| 279 | PHYAR_RW_READ = (0 << PHYAR_RW_SHIFT),
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| 280 | PHYAR_RW_WRITE = (1 << PHYAR_RW_SHIFT),
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| 281 | PHYAR_ADDR_SHIFT = 15,
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| 282 | PHYAR_ADDR_MASK = 0x1f,
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| 283 | PHYAR_DATA_MASK = 0xffff
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| 284 | };
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| 285 |
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| 286 | enum rtl8169_bmcr {
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| 287 | BMCR_RESET = (1 << 15), /**< Software reset */
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| 288 | BMCR_SPD_100 = (1 << 13), /**< 100 MBit mode set */
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| 289 | BMCR_AN_ENABLE = (1 << 12), /**< Autonegotion enable */
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| 290 | BMCR_AN_RESTART = (1 << 9), /**< Restart autonegotion */
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| 291 | BMCR_DUPLEX = (1 << 8), /**< Duplex mode: 1=full duplex */
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| 292 | BMCR_SPD_1000 = (1 << 6), /**< 1000 Mbit mode set */
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| 293 | };
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| 294 |
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| 295 | enum rtl8169_descr_control {
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| 296 | CONTROL_OWN = (1 << 31), /**< Descriptor ownership */
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| 297 | CONTROL_EOR = (1 << 30), /**< End Of Ring marker */
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| 298 | CONTROL_FS = (1 << 29), /**< First Segment marker */
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| 299 | CONTROL_LS = (1 << 28), /**< Last Segment marker */
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| 300 | CONTROL_LGSEN = (1 << 27), /**< Large send enable */
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| 301 | CONTROL_MSS_SHIFT = 16,
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| 302 | CONTROL_MSS_MASK = 10,
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| 303 | CONTROL_FRAMELEN_MASK = 0xffff
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| 304 | };
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| 305 |
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| 306 | enum rtl8169_descr_txstatus {
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| 307 | TXSTATUS_UNDERRUN = (1 << 25),
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| 308 | TXSTATUS_TXERRSUM = (1 << 23),
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| 309 | TXSTATUS_OWINCOL = (1 << 22),
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| 310 | TXSTATUS_LINKFAIL = (1 << 21),
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| 311 | TXSTATUS_EXCESSCOL = (1 << 20)
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| 312 | };
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| 313 |
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| 314 | enum rtl8169_descr_rxstatus {
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| 315 | RXSTATUS_MAR = (1 << 27),
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| 316 | RXSTATUS_PAM = (1 << 26),
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| 317 | RXSTATUS_BAR = (1 << 25),
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| 318 | RXSTATUS_BOVF = (1 << 24),
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| 319 | RXSTATUS_FOVF = (1 << 23),
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| 320 | RXSTATUS_RWT = (1 << 22),
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| 321 | RXSTATUS_RES = (1 << 21),
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| 322 | RXSTATUS_RUNT = (1 << 20),
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| 323 | RXSTATUS_CRC = (1 << 19),
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| 324 | RXSTATUS_PID1 = (1 << 18),
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| 325 | RXSTATUS_PID0 = (1 << 17),
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| 326 | RXSTATUS_IPF = (1 << 16),
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| 327 | RXSTATUS_UDPF = (1 << 15),
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| 328 | RXSTATUS_TCPF = (1 << 14)
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| 329 | };
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| 330 |
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| 331 | typedef struct rtl8169_descr {
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| 332 | uint32_t control;
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| 333 | uint32_t vlan;
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| 334 | uint32_t buf_low;
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| 335 | uint32_t buf_high;
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| 336 | } rtl8169_descr_t;
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| 337 |
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| 338 | #endif
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