source: mainline/uspace/drv/nic/ne2k/dp8390.h@ 0016674

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0016674 was d51838f, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Let leaf drivers enable/disable/clear interrupts via hw_res instead of directly using irc.
  • Property mode set to 100644
File size: 10.8 KB
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1/*
2 * Copyright (c) 2009 Lukas Mejdrech
3 * Copyright (c) 2011 Martin Decky
4 * Copyright (c) 2011 Radim Vansa
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * This code is based upon the NE2000 driver for MINIX,
33 * distributed according to a BSD-style license.
34 *
35 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
36 * Copyright (c) 1992, 1994 Philip Homburg
37 * Copyright (c) 1996 G. Falzoni
38 *
39 */
40
41/** @addtogroup drv_ne2k
42 * @{
43 */
44
45/** @file
46 * DP8390 network interface definitions.
47 */
48
49#ifndef __NET_NETIF_DP8390_H__
50#define __NET_NETIF_DP8390_H__
51
52#include <async.h>
53#include <ddf/driver.h>
54#include <fibril_synch.h>
55#include <nic.h>
56#include <ddf/interrupt.h>
57
58/** Input/output size */
59#define NE2K_IO_SIZE 0x0020
60
61/* NE2000 implementation. */
62
63/** NE2000 Data Register */
64#define NE2K_DATA 0x0010
65
66/** NE2000 Reset register */
67#define NE2K_RESET 0x001f
68
69/** NE2000 data start */
70#define NE2K_START 0x4000
71
72/** NE2000 data size */
73#define NE2K_SIZE 0x4000
74
75/** NE2000 retry count */
76#define NE2K_RETRY 0x1000
77
78/** NE2000 error messages rate limiting */
79#define NE2K_ERL 10
80
81/** Minimum Ethernet packet size in bytes */
82#define ETH_MIN_PACK_SIZE 60
83
84/** Maximum Ethernet packet size in bytes */
85#define ETH_MAX_PACK_SIZE_TAGGED 1518
86
87/* National Semiconductor DP8390 Network Interface Controller. */
88
89/** Page 0, for reading */
90#define DP_CR 0x00 /**< Command Register */
91#define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */
92#define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */
93#define DP_BNRY 0x03 /**< Boundary Pointer */
94#define DP_TSR 0x04 /**< Transmit Status Register */
95#define DP_NCR 0x05 /**< Number of Collisions Register */
96#define DP_FIFO 0x06 /**< FIFO */
97#define DP_ISR 0x07 /**< Interrupt Status Register */
98#define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */
99#define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */
100#define DP_RSR 0x0c /**< Receive Status Register */
101#define DP_CNTR0 0x0d /**< Tally Counter 0 */
102#define DP_CNTR1 0x0e /**< Tally Counter 1 */
103#define DP_CNTR2 0x0f /**< Tally Counter 2 */
104
105/** Page 0, for writing */
106#define DP_PSTART 0x01 /**< Page Start Register*/
107#define DP_PSTOP 0x02 /**< Page Stop Register */
108#define DP_TPSR 0x04 /**< Transmit Page Start Register */
109#define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */
110#define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */
111#define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */
112#define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */
113#define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */
114#define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */
115#define DP_RCR 0x0c /**< Receive Configuration Register */
116#define DP_TCR 0x0d /**< Transmit Configuration Register */
117#define DP_DCR 0x0e /**< Data Configuration Register */
118#define DP_IMR 0x0f /**< Interrupt Mask Register */
119
120/** Page 1, read/write */
121#define DP_PAR0 0x01 /**< Physical Address Register 0 */
122#define DP_PAR1 0x02 /**< Physical Address Register 1 */
123#define DP_PAR2 0x03 /**< Physical Address Register 2 */
124#define DP_PAR3 0x04 /**< Physical Address Register 3 */
125#define DP_PAR4 0x05 /**< Physical Address Register 4 */
126#define DP_PAR5 0x06 /**< Physical Address Register 5 */
127#define DP_CURR 0x07 /**< Current Page Register */
128#define DP_MAR0 0x08 /**< Multicast Address Register 0 */
129#define DP_MAR1 0x09 /**< Multicast Address Register 1 */
130#define DP_MAR2 0x0a /**< Multicast Address Register 2 */
131#define DP_MAR3 0x0b /**< Multicast Address Register 3 */
132#define DP_MAR4 0x0c /**< Multicast Address Register 4 */
133#define DP_MAR5 0x0d /**< Multicast Address Register 5 */
134#define DP_MAR6 0x0e /**< Multicast Address Register 6 */
135#define DP_MAR7 0x0f /**< Multicast Address Register 7 */
136
137/* Bits in Command Register */
138#define CR_STP 0x01 /**< Stop (software reset) */
139#define CR_STA 0x02 /**< Start (activate NIC) */
140#define CR_TXP 0x04 /**< Transmit Packet */
141#define CR_DMA 0x38 /**< Mask for DMA control */
142#define CR_DM_NOP 0x00 /**< DMA: No Operation */
143#define CR_DM_RR 0x08 /**< DMA: Remote Read */
144#define CR_DM_RW 0x10 /**< DMA: Remote Write */
145#define CR_DM_SP 0x18 /**< DMA: Send Packet */
146#define CR_DM_ABORT 0x20 /**< DMA: Abort Remote DMA Operation */
147#define CR_PS 0xc0 /**< Mask for Page Select */
148#define CR_PS_P0 0x00 /**< Register Page 0 */
149#define CR_PS_P1 0x40 /**< Register Page 1 */
150#define CR_PS_P2 0x80 /**< Register Page 2 */
151#define CR_PS_T1 0xc0 /**< Test Mode Register Map */
152
153/* Bits in Interrupt State Register */
154#define ISR_PRX 0x01 /**< Packet Received with no errors */
155#define ISR_PTX 0x02 /**< Packet Transmitted with no errors */
156#define ISR_RXE 0x04 /**< Receive Error */
157#define ISR_TXE 0x08 /**< Transmit Error */
158#define ISR_OVW 0x10 /**< Overwrite Warning */
159#define ISR_CNT 0x20 /**< Counter Overflow */
160#define ISR_RDC 0x40 /**< Remote DMA Complete */
161#define ISR_RST 0x80 /**< Reset Status */
162
163/* Bits in Interrupt Mask Register */
164#define IMR_PRXE 0x01 /**< Packet Received Interrupt Enable */
165#define IMR_PTXE 0x02 /**< Packet Transmitted Interrupt Enable */
166#define IMR_RXEE 0x04 /**< Receive Error Interrupt Enable */
167#define IMR_TXEE 0x08 /**< Transmit Error Interrupt Enable */
168#define IMR_OVWE 0x10 /**< Overwrite Warning Interrupt Enable */
169#define IMR_CNTE 0x20 /**< Counter Overflow Interrupt Enable */
170#define IMR_RDCE 0x40 /**< DMA Complete Interrupt Enable */
171
172/* Bits in Data Configuration Register */
173#define DCR_WTS 0x01 /**< Word Transfer Select */
174#define DCR_BYTEWIDE 0x00 /**< WTS: byte wide transfers */
175#define DCR_WORDWIDE 0x01 /**< WTS: word wide transfers */
176#define DCR_BOS 0x02 /**< Byte Order Select */
177#define DCR_LTLENDIAN 0x00 /**< BOS: Little Endian */
178#define DCR_BIGENDIAN 0x02 /**< BOS: Big Endian */
179#define DCR_LAS 0x04 /**< Long Address Select */
180#define DCR_BMS 0x08 /**< Burst Mode Select */
181#define DCR_AR 0x10 /**< Autoinitialize Remote */
182#define DCR_FTS 0x60 /**< Fifo Threshold Select */
183#define DCR_2BYTES 0x00 /**< 2 bytes */
184#define DCR_4BYTES 0x40 /**< 4 bytes */
185#define DCR_8BYTES 0x20 /**< 8 bytes */
186#define DCR_12BYTES 0x60 /**< 12 bytes */
187
188/* Bits in Transmit Configuration Register */
189#define TCR_CRC 0x01 /**< Inhibit CRC */
190#define TCR_ELC 0x06 /**< Encoded Loopback Control */
191#define TCR_NORMAL 0x00 /**< ELC: Normal Operation */
192#define TCR_INTERNAL 0x02 /**< ELC: Internal Loopback */
193#define TCR_0EXTERNAL 0x04 /**< ELC: External Loopback LPBK=0 */
194#define TCR_1EXTERNAL 0x06 /**< ELC: External Loopback LPBK=1 */
195#define TCR_ATD 0x08 /**< Auto Transmit Disable */
196#define TCR_OFST 0x10 /**< Collision Offset Enable (be nice) */
197
198/* Bits in Interrupt Status Register */
199#define TSR_PTX 0x01 /**< Packet Transmitted (without error) */
200#define TSR_DFR 0x02 /**< Transmit Deferred (reserved) */
201#define TSR_COL 0x04 /**< Transmit Collided */
202#define TSR_ABT 0x08 /**< Transmit Aborted */
203#define TSR_CRS 0x10 /**< Carrier Sense Lost */
204#define TSR_FU 0x20 /**< FIFO Underrun */
205#define TSR_CDH 0x40 /**< CD Heartbeat */
206#define TSR_OWC 0x80 /**< Out of Window Collision */
207
208/* Bits in Receive Configuration Register */
209#define RCR_SEP 0x01 /**< Save Errored Packets */
210#define RCR_AR 0x02 /**< Accept Runt Packets */
211#define RCR_AB 0x04 /**< Accept Broadcast */
212#define RCR_AM 0x08 /**< Accept Multicast */
213#define RCR_PRO 0x10 /**< Physical Promiscuous */
214#define RCR_MON 0x20 /**< Monitor Mode */
215
216/* Bits in Receive Status Register */
217#define RSR_PRX 0x01 /**< Packet Received Intact */
218#define RSR_CRC 0x02 /**< CRC Error */
219#define RSR_FAE 0x04 /**< Frame Alignment Error */
220#define RSR_FO 0x08 /**< FIFO Overrun */
221#define RSR_MPA 0x10 /**< Missed Packet */
222#define RSR_PHY 0x20 /**< Multicast Address Match */
223#define RSR_DIS 0x40 /**< Receiver Disabled */
224#define RSR_DFR 0x80 /**< In later manuals: Deferring */
225
226typedef struct {
227 /** DDF device */
228 ddf_dev_t *dev;
229 /** Parent session */
230 async_sess_t *parent_sess;
231 /* Device configuration */
232 void *base_port; /**< Port assigned from ISA configuration **/
233 void *port;
234 void *data_port;
235 int irq;
236 nic_address_t mac;
237
238 uint8_t start_page; /**< Ring buffer start page */
239 uint8_t stop_page; /**< Ring buffer stop page */
240
241 /* Send queue */
242 struct {
243 bool dirty; /**< Buffer contains a packet */
244 size_t size; /**< Packet size */
245 uint8_t page; /**< Starting page of the buffer */
246 } sq;
247 fibril_mutex_t sq_mutex;
248 fibril_condvar_t sq_cv;
249
250 /* Driver run-time variables */
251 bool probed;
252 bool up;
253
254 /* Irq code with assigned addresses for this device */
255 irq_code_t code;
256
257 /* Copy of the receive configuration register */
258 uint8_t receive_configuration;
259
260 /* Device statistics */
261 // TODO: shouldn't be these directly in device.h - nic_device_stats?
262 uint64_t misses; /**< Receive frame misses */
263 uint64_t underruns; /**< FIFO underruns */
264 uint64_t overruns; /**< FIFO overruns */
265} ne2k_t;
266
267extern int ne2k_probe(ne2k_t *);
268extern int ne2k_up(ne2k_t *);
269extern void ne2k_down(ne2k_t *);
270extern void ne2k_send(nic_t *, void *, size_t);
271extern void ne2k_interrupt(nic_t *, uint8_t, uint8_t);
272
273extern void ne2k_set_accept_mcast(ne2k_t *, int);
274extern void ne2k_set_accept_bcast(ne2k_t *, int);
275extern void ne2k_set_promisc_phys(ne2k_t *, int);
276extern void ne2k_set_mcast_hash(ne2k_t *, uint64_t);
277extern void ne2k_set_physical_address(ne2k_t *, const nic_address_t *address);
278
279#endif
280
281/** @}
282 */
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