| [80099c19] | 1 | /*
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| [1c7b0db7] | 2 | * Copyright (c) 2025 Jiri Svoboda
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| [80099c19] | 3 | * Copyright (c) 2009 Lukas Mejdrech
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| 4 | * Copyright (c) 2011 Martin Decky
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| 5 | * Copyright (c) 2011 Radim Vansa
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| 6 | * All rights reserved.
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| 7 | *
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| 8 | * Redistribution and use in source and binary forms, with or without
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| 9 | * modification, are permitted provided that the following conditions
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| 10 | * are met:
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| 11 | *
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| 12 | * - Redistributions of source code must retain the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer.
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| 14 | * - Redistributions in binary form must reproduce the above copyright
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| 15 | * notice, this list of conditions and the following disclaimer in the
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| 16 | * documentation and/or other materials provided with the distribution.
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| 17 | * - The name of the author may not be used to endorse or promote products
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| 18 | * derived from this software without specific prior written permission.
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| 19 | *
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| 20 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 21 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 22 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 23 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 26 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 27 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 30 | */
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| 31 |
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| 32 | /*
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| 33 | * This code is based upon the NE2000 driver for MINIX,
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| 34 | * distributed according to a BSD-style license.
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| 35 | *
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| 36 | * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
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| 37 | * Copyright (c) 1992, 1994 Philip Homburg
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| 38 | * Copyright (c) 1996 G. Falzoni
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| 39 | *
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| 40 | */
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| 41 |
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| 42 | /** @addtogroup drv_ne2k
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| 43 | * @{
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| 44 | */
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| 45 |
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| 46 | /** @file
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| 47 | * DP8390 network interface definitions.
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| 48 | */
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| 49 |
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| 50 | #ifndef __NET_NETIF_DP8390_H__
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| 51 | #define __NET_NETIF_DP8390_H__
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| 52 |
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| [d51838f] | 53 | #include <async.h>
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| 54 | #include <ddf/driver.h>
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| [80099c19] | 55 | #include <fibril_synch.h>
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| 56 | #include <nic.h>
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| 57 | #include <ddf/interrupt.h>
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| 58 |
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| 59 | /** Input/output size */
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| 60 | #define NE2K_IO_SIZE 0x0020
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| 61 |
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| 62 | /* NE2000 implementation. */
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| 63 |
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| 64 | /** NE2000 Data Register */
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| 65 | #define NE2K_DATA 0x0010
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| 66 |
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| 67 | /** NE2000 Reset register */
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| 68 | #define NE2K_RESET 0x001f
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| 69 |
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| 70 | /** NE2000 data start */
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| 71 | #define NE2K_START 0x4000
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| 72 |
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| 73 | /** NE2000 data size */
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| 74 | #define NE2K_SIZE 0x4000
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| 75 |
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| 76 | /** NE2000 retry count */
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| 77 | #define NE2K_RETRY 0x1000
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| 78 |
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| 79 | /** NE2000 error messages rate limiting */
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| 80 | #define NE2K_ERL 10
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| 81 |
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| 82 | /** Minimum Ethernet packet size in bytes */
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| 83 | #define ETH_MIN_PACK_SIZE 60
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| 84 |
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| 85 | /** Maximum Ethernet packet size in bytes */
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| 86 | #define ETH_MAX_PACK_SIZE_TAGGED 1518
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| 87 |
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| 88 | /* National Semiconductor DP8390 Network Interface Controller. */
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| 89 |
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| 90 | /** Page 0, for reading */
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| 91 | #define DP_CR 0x00 /**< Command Register */
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| 92 | #define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */
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| 93 | #define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */
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| 94 | #define DP_BNRY 0x03 /**< Boundary Pointer */
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| 95 | #define DP_TSR 0x04 /**< Transmit Status Register */
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| 96 | #define DP_NCR 0x05 /**< Number of Collisions Register */
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| 97 | #define DP_FIFO 0x06 /**< FIFO */
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| 98 | #define DP_ISR 0x07 /**< Interrupt Status Register */
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| 99 | #define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */
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| 100 | #define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */
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| 101 | #define DP_RSR 0x0c /**< Receive Status Register */
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| 102 | #define DP_CNTR0 0x0d /**< Tally Counter 0 */
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| 103 | #define DP_CNTR1 0x0e /**< Tally Counter 1 */
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| 104 | #define DP_CNTR2 0x0f /**< Tally Counter 2 */
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| 105 |
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| 106 | /** Page 0, for writing */
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| 107 | #define DP_PSTART 0x01 /**< Page Start Register*/
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| 108 | #define DP_PSTOP 0x02 /**< Page Stop Register */
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| 109 | #define DP_TPSR 0x04 /**< Transmit Page Start Register */
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| 110 | #define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */
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| 111 | #define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */
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| 112 | #define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */
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| 113 | #define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */
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| 114 | #define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */
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| 115 | #define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */
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| 116 | #define DP_RCR 0x0c /**< Receive Configuration Register */
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| 117 | #define DP_TCR 0x0d /**< Transmit Configuration Register */
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| 118 | #define DP_DCR 0x0e /**< Data Configuration Register */
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| 119 | #define DP_IMR 0x0f /**< Interrupt Mask Register */
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| 120 |
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| 121 | /** Page 1, read/write */
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| 122 | #define DP_PAR0 0x01 /**< Physical Address Register 0 */
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| 123 | #define DP_PAR1 0x02 /**< Physical Address Register 1 */
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| 124 | #define DP_PAR2 0x03 /**< Physical Address Register 2 */
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| 125 | #define DP_PAR3 0x04 /**< Physical Address Register 3 */
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| 126 | #define DP_PAR4 0x05 /**< Physical Address Register 4 */
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| 127 | #define DP_PAR5 0x06 /**< Physical Address Register 5 */
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| 128 | #define DP_CURR 0x07 /**< Current Page Register */
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| 129 | #define DP_MAR0 0x08 /**< Multicast Address Register 0 */
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| 130 | #define DP_MAR1 0x09 /**< Multicast Address Register 1 */
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| 131 | #define DP_MAR2 0x0a /**< Multicast Address Register 2 */
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| 132 | #define DP_MAR3 0x0b /**< Multicast Address Register 3 */
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| 133 | #define DP_MAR4 0x0c /**< Multicast Address Register 4 */
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| 134 | #define DP_MAR5 0x0d /**< Multicast Address Register 5 */
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| 135 | #define DP_MAR6 0x0e /**< Multicast Address Register 6 */
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| 136 | #define DP_MAR7 0x0f /**< Multicast Address Register 7 */
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| 137 |
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| 138 | /* Bits in Command Register */
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| 139 | #define CR_STP 0x01 /**< Stop (software reset) */
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| 140 | #define CR_STA 0x02 /**< Start (activate NIC) */
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| 141 | #define CR_TXP 0x04 /**< Transmit Packet */
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| 142 | #define CR_DMA 0x38 /**< Mask for DMA control */
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| 143 | #define CR_DM_NOP 0x00 /**< DMA: No Operation */
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| 144 | #define CR_DM_RR 0x08 /**< DMA: Remote Read */
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| 145 | #define CR_DM_RW 0x10 /**< DMA: Remote Write */
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| 146 | #define CR_DM_SP 0x18 /**< DMA: Send Packet */
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| 147 | #define CR_DM_ABORT 0x20 /**< DMA: Abort Remote DMA Operation */
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| 148 | #define CR_PS 0xc0 /**< Mask for Page Select */
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| 149 | #define CR_PS_P0 0x00 /**< Register Page 0 */
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| 150 | #define CR_PS_P1 0x40 /**< Register Page 1 */
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| 151 | #define CR_PS_P2 0x80 /**< Register Page 2 */
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| 152 | #define CR_PS_T1 0xc0 /**< Test Mode Register Map */
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| 153 |
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| 154 | /* Bits in Interrupt State Register */
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| 155 | #define ISR_PRX 0x01 /**< Packet Received with no errors */
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| 156 | #define ISR_PTX 0x02 /**< Packet Transmitted with no errors */
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| 157 | #define ISR_RXE 0x04 /**< Receive Error */
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| 158 | #define ISR_TXE 0x08 /**< Transmit Error */
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| 159 | #define ISR_OVW 0x10 /**< Overwrite Warning */
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| 160 | #define ISR_CNT 0x20 /**< Counter Overflow */
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| 161 | #define ISR_RDC 0x40 /**< Remote DMA Complete */
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| 162 | #define ISR_RST 0x80 /**< Reset Status */
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| 163 |
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| 164 | /* Bits in Interrupt Mask Register */
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| 165 | #define IMR_PRXE 0x01 /**< Packet Received Interrupt Enable */
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| 166 | #define IMR_PTXE 0x02 /**< Packet Transmitted Interrupt Enable */
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| 167 | #define IMR_RXEE 0x04 /**< Receive Error Interrupt Enable */
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| 168 | #define IMR_TXEE 0x08 /**< Transmit Error Interrupt Enable */
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| 169 | #define IMR_OVWE 0x10 /**< Overwrite Warning Interrupt Enable */
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| 170 | #define IMR_CNTE 0x20 /**< Counter Overflow Interrupt Enable */
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| 171 | #define IMR_RDCE 0x40 /**< DMA Complete Interrupt Enable */
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| 172 |
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| 173 | /* Bits in Data Configuration Register */
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| 174 | #define DCR_WTS 0x01 /**< Word Transfer Select */
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| 175 | #define DCR_BYTEWIDE 0x00 /**< WTS: byte wide transfers */
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| 176 | #define DCR_WORDWIDE 0x01 /**< WTS: word wide transfers */
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| 177 | #define DCR_BOS 0x02 /**< Byte Order Select */
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| 178 | #define DCR_LTLENDIAN 0x00 /**< BOS: Little Endian */
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| 179 | #define DCR_BIGENDIAN 0x02 /**< BOS: Big Endian */
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| 180 | #define DCR_LAS 0x04 /**< Long Address Select */
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| 181 | #define DCR_BMS 0x08 /**< Burst Mode Select */
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| 182 | #define DCR_AR 0x10 /**< Autoinitialize Remote */
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| 183 | #define DCR_FTS 0x60 /**< Fifo Threshold Select */
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| 184 | #define DCR_2BYTES 0x00 /**< 2 bytes */
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| 185 | #define DCR_4BYTES 0x40 /**< 4 bytes */
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| 186 | #define DCR_8BYTES 0x20 /**< 8 bytes */
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| 187 | #define DCR_12BYTES 0x60 /**< 12 bytes */
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| 188 |
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| 189 | /* Bits in Transmit Configuration Register */
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| 190 | #define TCR_CRC 0x01 /**< Inhibit CRC */
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| 191 | #define TCR_ELC 0x06 /**< Encoded Loopback Control */
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| 192 | #define TCR_NORMAL 0x00 /**< ELC: Normal Operation */
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| 193 | #define TCR_INTERNAL 0x02 /**< ELC: Internal Loopback */
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| 194 | #define TCR_0EXTERNAL 0x04 /**< ELC: External Loopback LPBK=0 */
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| 195 | #define TCR_1EXTERNAL 0x06 /**< ELC: External Loopback LPBK=1 */
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| 196 | #define TCR_ATD 0x08 /**< Auto Transmit Disable */
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| 197 | #define TCR_OFST 0x10 /**< Collision Offset Enable (be nice) */
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| 198 |
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| 199 | /* Bits in Interrupt Status Register */
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| 200 | #define TSR_PTX 0x01 /**< Packet Transmitted (without error) */
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| 201 | #define TSR_DFR 0x02 /**< Transmit Deferred (reserved) */
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| 202 | #define TSR_COL 0x04 /**< Transmit Collided */
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| 203 | #define TSR_ABT 0x08 /**< Transmit Aborted */
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| 204 | #define TSR_CRS 0x10 /**< Carrier Sense Lost */
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| 205 | #define TSR_FU 0x20 /**< FIFO Underrun */
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| 206 | #define TSR_CDH 0x40 /**< CD Heartbeat */
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| 207 | #define TSR_OWC 0x80 /**< Out of Window Collision */
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| 208 |
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| 209 | /* Bits in Receive Configuration Register */
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| 210 | #define RCR_SEP 0x01 /**< Save Errored Packets */
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| 211 | #define RCR_AR 0x02 /**< Accept Runt Packets */
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| 212 | #define RCR_AB 0x04 /**< Accept Broadcast */
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| 213 | #define RCR_AM 0x08 /**< Accept Multicast */
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| 214 | #define RCR_PRO 0x10 /**< Physical Promiscuous */
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| 215 | #define RCR_MON 0x20 /**< Monitor Mode */
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| 216 |
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| 217 | /* Bits in Receive Status Register */
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| 218 | #define RSR_PRX 0x01 /**< Packet Received Intact */
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| 219 | #define RSR_CRC 0x02 /**< CRC Error */
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| 220 | #define RSR_FAE 0x04 /**< Frame Alignment Error */
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| 221 | #define RSR_FO 0x08 /**< FIFO Overrun */
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| 222 | #define RSR_MPA 0x10 /**< Missed Packet */
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| 223 | #define RSR_PHY 0x20 /**< Multicast Address Match */
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| 224 | #define RSR_DIS 0x40 /**< Receiver Disabled */
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| 225 | #define RSR_DFR 0x80 /**< In later manuals: Deferring */
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| 226 |
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| 227 | typedef struct {
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| [d51838f] | 228 | /** DDF device */
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| 229 | ddf_dev_t *dev;
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| 230 | /** Parent session */
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| 231 | async_sess_t *parent_sess;
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| [80099c19] | 232 | /* Device configuration */
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| [d1582b50] | 233 | void *base_port; /**< Port assigned from ISA configuration */
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| [80099c19] | 234 | void *port;
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| 235 | void *data_port;
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| 236 | int irq;
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| 237 | nic_address_t mac;
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| [a35b458] | 238 |
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| [80099c19] | 239 | uint8_t start_page; /**< Ring buffer start page */
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| 240 | uint8_t stop_page; /**< Ring buffer stop page */
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| [a35b458] | 241 |
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| [80099c19] | 242 | /* Send queue */
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| 243 | struct {
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| 244 | bool dirty; /**< Buffer contains a packet */
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| 245 | size_t size; /**< Packet size */
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| 246 | uint8_t page; /**< Starting page of the buffer */
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| 247 | } sq;
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| 248 | fibril_mutex_t sq_mutex;
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| 249 | fibril_condvar_t sq_cv;
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| [a35b458] | 250 |
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| [80099c19] | 251 | /* Driver run-time variables */
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| 252 | bool probed;
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| 253 | bool up;
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| 254 |
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| 255 | /* Irq code with assigned addresses for this device */
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| 256 | irq_code_t code;
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| 257 |
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| 258 | /* Copy of the receive configuration register */
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| 259 | uint8_t receive_configuration;
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| 260 |
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| 261 | /* Device statistics */
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| 262 | // TODO: shouldn't be these directly in device.h - nic_device_stats?
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| 263 | uint64_t misses; /**< Receive frame misses */
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| 264 | uint64_t underruns; /**< FIFO underruns */
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| 265 | uint64_t overruns; /**< FIFO overruns */
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| 266 | } ne2k_t;
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| 267 |
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| [b7fd2a0] | 268 | extern errno_t ne2k_probe(ne2k_t *);
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| 269 | extern errno_t ne2k_up(ne2k_t *);
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| [1c7b0db7] | 270 | extern void ne2k_quiesce(ne2k_t *);
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| [80099c19] | 271 | extern void ne2k_down(ne2k_t *);
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| [6d8455d] | 272 | extern void ne2k_send(nic_t *, void *, size_t);
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| [80099c19] | 273 | extern void ne2k_interrupt(nic_t *, uint8_t, uint8_t);
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| 274 |
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| 275 | extern void ne2k_set_accept_mcast(ne2k_t *, int);
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| 276 | extern void ne2k_set_accept_bcast(ne2k_t *, int);
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| 277 | extern void ne2k_set_promisc_phys(ne2k_t *, int);
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| 278 | extern void ne2k_set_mcast_hash(ne2k_t *, uint64_t);
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| 279 | extern void ne2k_set_physical_address(ne2k_t *, const nic_address_t *address);
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| 280 |
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| 281 | #endif
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| 282 |
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| 283 | /** @}
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| 284 | */
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