source: mainline/uspace/drv/nic/ne2k/dp8390.c@ f991b6b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f991b6b was c8c43cae, checked in by Jiri Svoboda <jiri@…>, 14 years ago

Merge TCP rewrite.
  • Property mode set to 100644
File size: 18.4 KB
Line 
1/*
2 * Copyright (c) 2009 Lukas Mejdrech
3 * Copyright (c) 2011 Martin Decky
4 * Copyright (c) 2011 Radim Vansa
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * This code is based upon the NE2000 driver for MINIX,
33 * distributed according to a BSD-style license.
34 *
35 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
36 * Copyright (c) 1992, 1994 Philip Homburg
37 * Copyright (c) 1996 G. Falzoni
38 *
39 */
40
41/**
42 * @addtogroup drv_ne2k
43 * @{
44 */
45
46/**
47 * @file
48 * @brief NE2000 driver core
49 *
50 * NE2000 (based on DP8390) network interface core implementation.
51 * Only the basic NE2000 PIO (ISA) interface is supported, remote
52 * DMA is completely absent from this code for simplicity.
53 *
54 */
55
56#include <assert.h>
57#include <byteorder.h>
58#include <errno.h>
59#include <stdio.h>
60#include <libarch/ddi.h>
61#include <net/packet.h>
62#include <packet_client.h>
63#include "dp8390.h"
64
65/** Page size */
66#define DP_PAGE 256
67
68/** 6 * DP_PAGE >= 1514 bytes */
69#define SQ_PAGES 6
70
71/** Type definition of the receive header
72 *
73 */
74typedef struct {
75 /** Copy of RSR */
76 uint8_t status;
77
78 /** Pointer to next packet */
79 uint8_t next;
80
81 /** Receive Byte Count Low */
82 uint8_t rbcl;
83
84 /** Receive Byte Count High */
85 uint8_t rbch;
86} recv_header_t;
87
88/** Read a memory block word by word.
89 *
90 * @param[in] port Source address.
91 * @param[out] buf Destination buffer.
92 * @param[in] size Memory block size in bytes.
93 *
94 */
95static void pio_read_buf_16(void *port, void *buf, size_t size)
96{
97 size_t i;
98
99 for (i = 0; (i << 1) < size; i++)
100 *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port));
101}
102
103/** Write a memory block word by word.
104 *
105 * @param[in] port Destination address.
106 * @param[in] buf Source buffer.
107 * @param[in] size Memory block size in bytes.
108 *
109 */
110static void pio_write_buf_16(void *port, void *buf, size_t size)
111{
112 size_t i;
113
114 for (i = 0; (i << 1) < size; i++)
115 pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i));
116}
117
118static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
119{
120 size_t esize = size & ~1;
121
122 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
123 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
124 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
125 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
126 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
127
128 if (esize != 0) {
129 pio_read_buf_16(ne2k->data_port, buf, esize);
130 size -= esize;
131 buf += esize;
132 }
133
134 if (size) {
135 assert(size == 1);
136
137 uint16_t word = pio_read_16(ne2k->data_port);
138 memcpy(buf, &word, 1);
139 }
140}
141
142static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
143{
144 size_t esize_ru = (size + 1) & ~1;
145 size_t esize = size & ~1;
146
147 pio_write_8(ne2k->port + DP_RBCR0, esize_ru & 0xff);
148 pio_write_8(ne2k->port + DP_RBCR1, (esize_ru >> 8) & 0xff);
149 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
150 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
151 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
152
153 if (esize != 0) {
154 pio_write_buf_16(ne2k->data_port, buf, esize);
155 size -= esize;
156 buf += esize;
157 }
158
159 if (size) {
160 assert(size == 1);
161
162 uint16_t word = 0;
163
164 memcpy(&word, buf, 1);
165 pio_write_16(ne2k->data_port, word);
166 }
167}
168
169static void ne2k_init(ne2k_t *ne2k)
170{
171 unsigned int i;
172
173 /* Reset the ethernet card */
174 uint8_t val = pio_read_8(ne2k->port + NE2K_RESET);
175 usleep(2000);
176 pio_write_8(ne2k->port + NE2K_RESET, val);
177 usleep(2000);
178
179 /* Reset the DP8390 */
180 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
181 for (i = 0; i < NE2K_RETRY; i++) {
182 if (pio_read_8(ne2k->port + DP_ISR) != 0)
183 break;
184 }
185}
186
187/** Probe and initialize the network interface.
188 *
189 * @param[in,out] ne2k Network interface structure.
190 * @param[in] port Device address.
191 * @param[in] irq Device interrupt vector.
192 *
193 * @return EOK on success.
194 * @return EXDEV if the network interface was not recognized.
195 *
196 */
197int ne2k_probe(ne2k_t *ne2k)
198{
199 unsigned int i;
200
201 ne2k_init(ne2k);
202
203 /* Check if the DP8390 is really there */
204 uint8_t val = pio_read_8(ne2k->port + DP_CR);
205 if ((val & (CR_STP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT))
206 return EXDEV;
207
208 /* Disable the receiver and init TCR and DCR */
209 pio_write_8(ne2k->port + DP_RCR, RCR_MON);
210 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
211 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
212
213 /* Setup a transfer to get the MAC address */
214 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
215 pio_write_8(ne2k->port + DP_RBCR1, 0);
216 pio_write_8(ne2k->port + DP_RSAR0, 0);
217 pio_write_8(ne2k->port + DP_RSAR1, 0);
218 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
219
220 for (i = 0; i < ETH_ADDR; i++)
221 ne2k->mac.address[i] = pio_read_16(ne2k->data_port);
222
223 return EOK;
224}
225
226void ne2k_set_physical_address(ne2k_t *ne2k, const nic_address_t *address)
227{
228 memcpy(&ne2k->mac, address, sizeof(nic_address_t));
229
230 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STP);
231
232 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
233 pio_write_8(ne2k->port + DP_RBCR1, 0);
234 pio_write_8(ne2k->port + DP_RSAR0, 0);
235 pio_write_8(ne2k->port + DP_RSAR1, 0);
236 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
237
238 size_t i;
239 for (i = 0; i < ETH_ADDR; i++)
240 pio_write_16(ne2k->data_port, ne2k->mac.address[i]);
241
242 //pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
243}
244
245/** Start the network interface.
246 *
247 * @param[in,out] ne2k Network interface structure.
248 *
249 * @return EOK on success.
250 * @return EXDEV if the network interface is disabled.
251 *
252 */
253int ne2k_up(ne2k_t *ne2k)
254{
255 if (!ne2k->probed)
256 return EXDEV;
257
258 ne2k_init(ne2k);
259
260 /*
261 * Setup send queue. Use the first
262 * SQ_PAGES of NE2000 memory for the send
263 * buffer.
264 */
265 ne2k->sq.dirty = false;
266 ne2k->sq.page = NE2K_START / DP_PAGE;
267 fibril_mutex_initialize(&ne2k->sq_mutex);
268 fibril_condvar_initialize(&ne2k->sq_cv);
269
270 /*
271 * Setup receive ring buffer. Use all the rest
272 * of the NE2000 memory (except the first SQ_PAGES
273 * reserved for the send buffer) for the receive
274 * ring buffer.
275 */
276 ne2k->start_page = ne2k->sq.page + SQ_PAGES;
277 ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE;
278
279 /*
280 * Initialization of the DP8390 following the mandatory procedure
281 * in reference manual ("DP8390D/NS32490D NIC Network Interface
282 * Controller", National Semiconductor, July 1995, Page 29).
283 */
284
285 /* Step 1: */
286 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
287
288 /* Step 2: */
289 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
290
291 /* Step 3: */
292 pio_write_8(ne2k->port + DP_RBCR0, 0);
293 pio_write_8(ne2k->port + DP_RBCR1, 0);
294
295 /* Step 4: */
296 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
297
298 /* Step 5: */
299 pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL);
300
301 /* Step 6: */
302 pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page);
303 pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page);
304 pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page);
305
306 /* Step 7: */
307 pio_write_8(ne2k->port + DP_ISR, 0xff);
308
309 /* Step 8: */
310 pio_write_8(ne2k->port + DP_IMR,
311 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
312
313 /* Step 9: */
314 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
315
316 pio_write_8(ne2k->port + DP_PAR0, ne2k->mac.address[0]);
317 pio_write_8(ne2k->port + DP_PAR1, ne2k->mac.address[1]);
318 pio_write_8(ne2k->port + DP_PAR2, ne2k->mac.address[2]);
319 pio_write_8(ne2k->port + DP_PAR3, ne2k->mac.address[3]);
320 pio_write_8(ne2k->port + DP_PAR4, ne2k->mac.address[4]);
321 pio_write_8(ne2k->port + DP_PAR5, ne2k->mac.address[5]);
322
323 pio_write_8(ne2k->port + DP_MAR0, 0);
324 pio_write_8(ne2k->port + DP_MAR1, 0);
325 pio_write_8(ne2k->port + DP_MAR2, 0);
326 pio_write_8(ne2k->port + DP_MAR3, 0);
327 pio_write_8(ne2k->port + DP_MAR4, 0);
328 pio_write_8(ne2k->port + DP_MAR5, 0);
329 pio_write_8(ne2k->port + DP_MAR6, 0);
330 pio_write_8(ne2k->port + DP_MAR7, 0);
331
332 pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1);
333
334 /* Step 10: */
335 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
336
337 /* Step 11: */
338 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
339
340 /* Reset counters by reading */
341 pio_read_8(ne2k->port + DP_CNTR0);
342 pio_read_8(ne2k->port + DP_CNTR1);
343 pio_read_8(ne2k->port + DP_CNTR2);
344
345 /* Finish the initialization */
346 ne2k->up = true;
347 return EOK;
348}
349
350/** Stop the network interface.
351 *
352 * @param[in,out] ne2k Network interface structure.
353 *
354 */
355void ne2k_down(ne2k_t *ne2k)
356{
357 if ((ne2k->probed) && (ne2k->up)) {
358 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
359 ne2k_init(ne2k);
360 ne2k->up = false;
361 }
362}
363
364static void ne2k_reset(ne2k_t *ne2k)
365{
366 unsigned int i;
367
368 fibril_mutex_lock(&ne2k->sq_mutex);
369
370 /* Stop the chip */
371 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
372 pio_write_8(ne2k->port + DP_RBCR0, 0);
373 pio_write_8(ne2k->port + DP_RBCR1, 0);
374
375 for (i = 0; i < NE2K_RETRY; i++) {
376 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0)
377 break;
378 }
379
380 pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST);
381 pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT);
382 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
383
384 /* Acknowledge the ISR_RDC (remote DMA) interrupt */
385 for (i = 0; i < NE2K_RETRY; i++) {
386 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0)
387 break;
388 }
389
390 uint8_t val = pio_read_8(ne2k->port + DP_ISR);
391 pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC);
392
393 /*
394 * Reset the transmit ring. If we were transmitting a frame,
395 * we pretend that the packet is processed. Higher layers will
396 * retransmit if the packet wasn't actually sent.
397 */
398 ne2k->sq.dirty = false;
399
400 fibril_mutex_unlock(&ne2k->sq_mutex);
401}
402
403/** Send a frame.
404 *
405 * @param[in,out] ne2k Network interface structure.
406 * @param[in] packet Frame to be sent.
407 *
408 */
409void ne2k_send(nic_t *nic_data, packet_t *packet)
410{
411 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
412
413 assert(ne2k->probed);
414 assert(ne2k->up);
415
416 fibril_mutex_lock(&ne2k->sq_mutex);
417
418 while (ne2k->sq.dirty) {
419 fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex);
420 }
421 void *buf = packet_get_data(packet);
422 size_t size = packet_get_data_length(packet);
423
424 if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) {
425 fibril_mutex_unlock(&ne2k->sq_mutex);
426 return;
427 }
428
429 /* Upload the frame to the ethernet card */
430 ne2k_upload(ne2k, buf, ne2k->sq.page * DP_PAGE, size);
431 ne2k->sq.dirty = true;
432 ne2k->sq.size = size;
433
434 /* Initialize the transfer */
435 pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page);
436 pio_write_8(ne2k->port + DP_TBCR0, size & 0xff);
437 pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff);
438 pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA);
439 fibril_mutex_unlock(&ne2k->sq_mutex);
440
441 /* Relase packet */
442 nic_release_packet(nic_data, packet);
443}
444
445static nic_frame_t *ne2k_receive_frame(nic_t *nic_data, uint8_t page,
446 size_t length)
447{
448 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
449
450 nic_frame_t *frame = nic_alloc_frame(nic_data, length);
451 if (frame == NULL)
452 return NULL;
453
454 void *buf = packet_suffix(frame->packet, length);
455 bzero(buf, length);
456 uint8_t last = page + length / DP_PAGE;
457
458 if (last >= ne2k->stop_page) {
459 size_t left = (ne2k->stop_page - page) * DP_PAGE
460 - sizeof(recv_header_t);
461 ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
462 left);
463 ne2k_download(ne2k, buf + left, ne2k->start_page * DP_PAGE,
464 length - left);
465 } else {
466 ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
467 length);
468 }
469 return frame;
470}
471
472static void ne2k_receive(nic_t *nic_data)
473{
474 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
475 /*
476 * Allocate memory for the list of received frames.
477 * If the allocation fails here we still receive the
478 * frames from the network, but they will be lost.
479 */
480 nic_frame_list_t *frames = nic_alloc_frame_list();
481 size_t frames_count = 0;
482
483 /* We may block sending in this loop - after so many received frames there
484 * must be some interrupt pending (for the frames not yet downloaded) and
485 * we will continue in its handler. */
486 while (frames_count < 16) {
487 //TODO: isn't some locking necessary here?
488 uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1;
489
490 if (boundary == ne2k->stop_page)
491 boundary = ne2k->start_page;
492
493 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA);
494 uint8_t current = pio_read_8(ne2k->port + DP_CURR);
495 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA);
496 if (current == boundary)
497 /* No more frames to process */
498 break;
499
500 recv_header_t header;
501 size_t size = sizeof(header);
502 size_t offset = boundary * DP_PAGE;
503
504 /* Get the frame header */
505 pio_write_8(ne2k->port + DP_RBCR0, size & 0xff);
506 pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff);
507 pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff);
508 pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff);
509 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
510
511 pio_read_buf_16(ne2k->data_port, (void *) &header, size);
512
513 size_t length =
514 (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size;
515 uint8_t next = header.next;
516
517 if ((length < ETH_MIN_PACK_SIZE)
518 || (length > ETH_MAX_PACK_SIZE_TAGGED)) {
519 next = current;
520 } else if ((header.next < ne2k->start_page)
521 || (header.next > ne2k->stop_page)) {
522 next = current;
523 } else if (header.status & RSR_FO) {
524 /*
525 * This is very serious, so we issue a warning and
526 * reset the buffers.
527 */
528 ne2k->overruns++;
529 next = current;
530 } else if ((header.status & RSR_PRX) && (ne2k->up)) {
531 if (frames != NULL) {
532 nic_frame_t *frame =
533 ne2k_receive_frame(nic_data, boundary, length);
534 if (frame != NULL) {
535 nic_frame_list_append(frames, frame);
536 frames_count++;
537 } else {
538 break;
539 }
540 } else
541 break;
542 }
543
544 /*
545 * Update the boundary pointer
546 * to the value of the page
547 * prior to the next packet to
548 * be processed.
549 */
550 if (next == ne2k->start_page)
551 next = ne2k->stop_page - 1;
552 else
553 next--;
554 pio_write_8(ne2k->port + DP_BNRY, next);
555 }
556 nic_received_frame_list(nic_data, frames);
557}
558
559void ne2k_interrupt(nic_t *nic_data, uint8_t isr, uint8_t tsr)
560{
561 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
562
563 if (isr & (ISR_PTX | ISR_TXE)) {
564 if (tsr & TSR_COL) {
565 nic_report_collisions(nic_data,
566 pio_read_8(ne2k->port + DP_NCR) & 15);
567 }
568
569 if (tsr & TSR_PTX) {
570 // TODO: fix number of sent bytes (but how?)
571 nic_report_send_ok(nic_data, 1, 0);
572 } else if (tsr & TSR_ABT) {
573 nic_report_send_error(nic_data, NIC_SEC_ABORTED, 1);
574 } else if (tsr & TSR_CRS) {
575 nic_report_send_error(nic_data, NIC_SEC_CARRIER_LOST, 1);
576 } else if (tsr & TSR_FU) {
577 ne2k->underruns++;
578 // if (ne2k->underruns < NE2K_ERL) {
579 // }
580 } else if (tsr & TSR_CDH) {
581 nic_report_send_error(nic_data, NIC_SEC_HEARTBEAT, 1);
582 // if (nic_data->stats.send_heartbeat_errors < NE2K_ERL) {
583 // }
584 } else if (tsr & TSR_OWC) {
585 nic_report_send_error(nic_data, NIC_SEC_WINDOW_ERROR, 1);
586 }
587
588 fibril_mutex_lock(&ne2k->sq_mutex);
589 if (ne2k->sq.dirty) {
590 /* Prepare the buffer for next packet */
591 ne2k->sq.dirty = false;
592 ne2k->sq.size = 0;
593
594 /* Signal a next frame to be sent */
595 fibril_condvar_broadcast(&ne2k->sq_cv);
596 } else {
597 ne2k->misses++;
598 // if (ne2k->misses < NE2K_ERL) {
599 // }
600 }
601 fibril_mutex_unlock(&ne2k->sq_mutex);
602 }
603
604 if (isr & ISR_CNT) {
605 unsigned int errors;
606 for (errors = pio_read_8(ne2k->port + DP_CNTR0); errors > 0; --errors)
607 nic_report_receive_error(nic_data, NIC_REC_CRC, 1);
608 for (errors = pio_read_8(ne2k->port + DP_CNTR1); errors > 0; --errors)
609 nic_report_receive_error(nic_data, NIC_REC_FRAME_ALIGNMENT, 1);
610 for (errors = pio_read_8(ne2k->port + DP_CNTR2); errors > 0; --errors)
611 nic_report_receive_error(nic_data, NIC_REC_MISSED, 1);
612 }
613 if (isr & ISR_PRX) {
614 ne2k_receive(nic_data);
615 }
616 if (isr & ISR_RST) {
617 /*
618 * The chip is stopped, and all arrived
619 * frames are delivered.
620 */
621 ne2k_reset(ne2k);
622 }
623
624 /* Unmask interrupts to be processed in the next round */
625 pio_write_8(ne2k->port + DP_IMR,
626 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
627}
628
629void ne2k_set_accept_bcast(ne2k_t *ne2k, int accept)
630{
631 if (accept)
632 ne2k->receive_configuration |= RCR_AB;
633 else
634 ne2k->receive_configuration &= ~RCR_AB;
635
636 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
637}
638
639void ne2k_set_accept_mcast(ne2k_t *ne2k, int accept)
640{
641 if (accept)
642 ne2k->receive_configuration |= RCR_AM;
643 else
644 ne2k->receive_configuration &= ~RCR_AM;
645
646 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
647}
648
649void ne2k_set_promisc_phys(ne2k_t *ne2k, int promisc)
650{
651 if (promisc)
652 ne2k->receive_configuration |= RCR_PRO;
653 else
654 ne2k->receive_configuration &= ~RCR_PRO;
655
656 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
657}
658
659void ne2k_set_mcast_hash(ne2k_t *ne2k, uint64_t hash)
660{
661 /* Select Page 1 and stop all transfers */
662 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
663
664 pio_write_8(ne2k->port + DP_MAR0, (uint8_t) hash);
665 pio_write_8(ne2k->port + DP_MAR1, (uint8_t) (hash >> 8));
666 pio_write_8(ne2k->port + DP_MAR2, (uint8_t) (hash >> 16));
667 pio_write_8(ne2k->port + DP_MAR3, (uint8_t) (hash >> 24));
668 pio_write_8(ne2k->port + DP_MAR4, (uint8_t) (hash >> 32));
669 pio_write_8(ne2k->port + DP_MAR5, (uint8_t) (hash >> 40));
670 pio_write_8(ne2k->port + DP_MAR6, (uint8_t) (hash >> 48));
671 pio_write_8(ne2k->port + DP_MAR7, (uint8_t) (hash >> 56));
672
673 /* Select Page 0 and resume transfers */
674 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
675}
676
677/** @}
678 */
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