source: mainline/uspace/drv/nic/ne2k/dp8390.c@ 80099c19

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 80099c19 was 80099c19, checked in by Martin Decky <martin@…>, 14 years ago

cherrypick a sanitized NE2K driver from lp:~helenos-nicf/helenos/nicf
currently not used yet
  • Property mode set to 100644
File size: 18.4 KB
Line 
1/*
2 * Copyright (c) 2009 Lukas Mejdrech
3 * Copyright (c) 2011 Martin Decky
4 * Copyright (c) 2011 Radim Vansa
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * This code is based upon the NE2000 driver for MINIX,
33 * distributed according to a BSD-style license.
34 *
35 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
36 * Copyright (c) 1992, 1994 Philip Homburg
37 * Copyright (c) 1996 G. Falzoni
38 *
39 */
40
41/**
42 * @addtogroup drv_ne2k
43 * @{
44 */
45
46/**
47 * @file
48 * @brief NE2000 driver core
49 *
50 * NE2000 (based on DP8390) network interface core implementation.
51 * Only the basic NE2000 PIO (ISA) interface is supported, remote
52 * DMA is completely absent from this code for simplicity.
53 *
54 */
55
56#include <assert.h>
57#include <byteorder.h>
58#include <errno.h>
59#include <stdio.h>
60#include <libarch/ddi.h>
61#include <net/packet.h>
62#include <packet_client.h>
63#include "dp8390.h"
64
65/** Page size */
66#define DP_PAGE 256
67
68/** 6 * DP_PAGE >= 1514 bytes */
69#define SQ_PAGES 6
70
71/** Type definition of the receive header
72 *
73 */
74typedef struct {
75 /** Copy of RSR */
76 uint8_t status;
77
78 /** Pointer to next packet */
79 uint8_t next;
80
81 /** Receive Byte Count Low */
82 uint8_t rbcl;
83
84 /** Receive Byte Count High */
85 uint8_t rbch;
86} recv_header_t;
87
88/** Read a memory block word by word.
89 *
90 * @param[in] port Source address.
91 * @param[out] buf Destination buffer.
92 * @param[in] size Memory block size in bytes.
93 *
94 */
95static void pio_read_buf_16(void *port, void *buf, size_t size)
96{
97 size_t i;
98
99 for (i = 0; (i << 1) < size; i++)
100 *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port));
101}
102
103/** Write a memory block word by word.
104 *
105 * @param[in] port Destination address.
106 * @param[in] buf Source buffer.
107 * @param[in] size Memory block size in bytes.
108 *
109 */
110static void pio_write_buf_16(void *port, void *buf, size_t size)
111{
112 size_t i;
113
114 for (i = 0; (i << 1) < size; i++)
115 pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i));
116}
117
118static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
119{
120 size_t esize = size & ~1;
121
122 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
123 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
124 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
125 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
126 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
127
128 if (esize != 0) {
129 pio_read_buf_16(ne2k->data_port, buf, esize);
130 size -= esize;
131 buf += esize;
132 }
133
134 if (size) {
135 assert(size == 1);
136
137 uint16_t word = pio_read_16(ne2k->data_port);
138 memcpy(buf, &word, 1);
139 }
140}
141
142static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
143{
144 size_t esize = size & ~1;
145
146 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
147 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
148 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
149 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
150 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
151
152 if (esize != 0) {
153 pio_write_buf_16(ne2k->data_port, buf, esize);
154 size -= esize;
155 buf += esize;
156 }
157
158 if (size) {
159 assert(size == 1);
160
161 uint16_t word = 0;
162
163 memcpy(&word, buf, 1);
164 pio_write_16(ne2k->data_port, word);
165 }
166}
167
168static void ne2k_init(ne2k_t *ne2k)
169{
170 unsigned int i;
171
172 /* Reset the ethernet card */
173 uint8_t val = pio_read_8(ne2k->port + NE2K_RESET);
174 usleep(2000);
175 pio_write_8(ne2k->port + NE2K_RESET, val);
176 usleep(2000);
177
178 /* Reset the DP8390 */
179 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
180 for (i = 0; i < NE2K_RETRY; i++) {
181 if (pio_read_8(ne2k->port + DP_ISR) != 0)
182 break;
183 }
184}
185
186/** Probe and initialize the network interface.
187 *
188 * @param[in,out] ne2k Network interface structure.
189 * @param[in] port Device address.
190 * @param[in] irq Device interrupt vector.
191 *
192 * @return EOK on success.
193 * @return EXDEV if the network interface was not recognized.
194 *
195 */
196int ne2k_probe(ne2k_t *ne2k)
197{
198 unsigned int i;
199
200 ne2k_init(ne2k);
201
202 /* Check if the DP8390 is really there */
203 uint8_t val = pio_read_8(ne2k->port + DP_CR);
204 if ((val & (CR_STP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT))
205 return EXDEV;
206
207 /* Disable the receiver and init TCR and DCR */
208 pio_write_8(ne2k->port + DP_RCR, RCR_MON);
209 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
210 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
211
212 /* Setup a transfer to get the MAC address */
213 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
214 pio_write_8(ne2k->port + DP_RBCR1, 0);
215 pio_write_8(ne2k->port + DP_RSAR0, 0);
216 pio_write_8(ne2k->port + DP_RSAR1, 0);
217 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
218
219 for (i = 0; i < ETH_ADDR; i++)
220 ne2k->mac.address[i] = pio_read_16(ne2k->data_port);
221
222 return EOK;
223}
224
225void ne2k_set_physical_address(ne2k_t *ne2k, const nic_address_t *address)
226{
227 memcpy(&ne2k->mac, address, sizeof(nic_address_t));
228
229 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STP);
230
231 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
232 pio_write_8(ne2k->port + DP_RBCR1, 0);
233 pio_write_8(ne2k->port + DP_RSAR0, 0);
234 pio_write_8(ne2k->port + DP_RSAR1, 0);
235 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
236
237 size_t i;
238 for (i = 0; i < ETH_ADDR; i++)
239 pio_write_16(ne2k->data_port, ne2k->mac.address[i]);
240
241 //pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
242}
243
244/** Start the network interface.
245 *
246 * @param[in,out] ne2k Network interface structure.
247 *
248 * @return EOK on success.
249 * @return EXDEV if the network interface is disabled.
250 *
251 */
252int ne2k_up(ne2k_t *ne2k)
253{
254 if (!ne2k->probed)
255 return EXDEV;
256
257 ne2k_init(ne2k);
258
259 /*
260 * Setup send queue. Use the first
261 * SQ_PAGES of NE2000 memory for the send
262 * buffer.
263 */
264 ne2k->sq.dirty = false;
265 ne2k->sq.page = NE2K_START / DP_PAGE;
266 fibril_mutex_initialize(&ne2k->sq_mutex);
267 fibril_condvar_initialize(&ne2k->sq_cv);
268
269 /*
270 * Setup receive ring buffer. Use all the rest
271 * of the NE2000 memory (except the first SQ_PAGES
272 * reserved for the send buffer) for the receive
273 * ring buffer.
274 */
275 ne2k->start_page = ne2k->sq.page + SQ_PAGES;
276 ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE;
277
278 /*
279 * Initialization of the DP8390 following the mandatory procedure
280 * in reference manual ("DP8390D/NS32490D NIC Network Interface
281 * Controller", National Semiconductor, July 1995, Page 29).
282 */
283
284 /* Step 1: */
285 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
286
287 /* Step 2: */
288 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
289
290 /* Step 3: */
291 pio_write_8(ne2k->port + DP_RBCR0, 0);
292 pio_write_8(ne2k->port + DP_RBCR1, 0);
293
294 /* Step 4: */
295 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
296
297 /* Step 5: */
298 pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL);
299
300 /* Step 6: */
301 pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page);
302 pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page);
303 pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page);
304
305 /* Step 7: */
306 pio_write_8(ne2k->port + DP_ISR, 0xff);
307
308 /* Step 8: */
309 pio_write_8(ne2k->port + DP_IMR,
310 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
311
312 /* Step 9: */
313 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
314
315 pio_write_8(ne2k->port + DP_PAR0, ne2k->mac.address[0]);
316 pio_write_8(ne2k->port + DP_PAR1, ne2k->mac.address[1]);
317 pio_write_8(ne2k->port + DP_PAR2, ne2k->mac.address[2]);
318 pio_write_8(ne2k->port + DP_PAR3, ne2k->mac.address[3]);
319 pio_write_8(ne2k->port + DP_PAR4, ne2k->mac.address[4]);
320 pio_write_8(ne2k->port + DP_PAR5, ne2k->mac.address[5]);
321
322 pio_write_8(ne2k->port + DP_MAR0, 0);
323 pio_write_8(ne2k->port + DP_MAR1, 0);
324 pio_write_8(ne2k->port + DP_MAR2, 0);
325 pio_write_8(ne2k->port + DP_MAR3, 0);
326 pio_write_8(ne2k->port + DP_MAR4, 0);
327 pio_write_8(ne2k->port + DP_MAR5, 0);
328 pio_write_8(ne2k->port + DP_MAR6, 0);
329 pio_write_8(ne2k->port + DP_MAR7, 0);
330
331 pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1);
332
333 /* Step 10: */
334 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
335
336 /* Step 11: */
337 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
338
339 /* Reset counters by reading */
340 pio_read_8(ne2k->port + DP_CNTR0);
341 pio_read_8(ne2k->port + DP_CNTR1);
342 pio_read_8(ne2k->port + DP_CNTR2);
343
344 /* Finish the initialization */
345 ne2k->up = true;
346 return EOK;
347}
348
349/** Stop the network interface.
350 *
351 * @param[in,out] ne2k Network interface structure.
352 *
353 */
354void ne2k_down(ne2k_t *ne2k)
355{
356 if ((ne2k->probed) && (ne2k->up)) {
357 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
358 ne2k_init(ne2k);
359 ne2k->up = false;
360 }
361}
362
363static void ne2k_reset(ne2k_t *ne2k)
364{
365 unsigned int i;
366
367 fibril_mutex_lock(&ne2k->sq_mutex);
368
369 /* Stop the chip */
370 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
371 pio_write_8(ne2k->port + DP_RBCR0, 0);
372 pio_write_8(ne2k->port + DP_RBCR1, 0);
373
374 for (i = 0; i < NE2K_RETRY; i++) {
375 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0)
376 break;
377 }
378
379 pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST);
380 pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT);
381 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
382
383 /* Acknowledge the ISR_RDC (remote DMA) interrupt */
384 for (i = 0; i < NE2K_RETRY; i++) {
385 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0)
386 break;
387 }
388
389 uint8_t val = pio_read_8(ne2k->port + DP_ISR);
390 pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC);
391
392 /*
393 * Reset the transmit ring. If we were transmitting a frame,
394 * we pretend that the packet is processed. Higher layers will
395 * retransmit if the packet wasn't actually sent.
396 */
397 ne2k->sq.dirty = false;
398
399 fibril_mutex_unlock(&ne2k->sq_mutex);
400}
401
402/** Send a frame.
403 *
404 * @param[in,out] ne2k Network interface structure.
405 * @param[in] packet Frame to be sent.
406 *
407 */
408void ne2k_send(nic_t *nic_data, packet_t *packet)
409{
410 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
411
412 assert(ne2k->probed);
413 assert(ne2k->up);
414
415 fibril_mutex_lock(&ne2k->sq_mutex);
416
417 while (ne2k->sq.dirty) {
418 fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex);
419 }
420 void *buf = packet_get_data(packet);
421 size_t size = packet_get_data_length(packet);
422
423 if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) {
424 fibril_mutex_unlock(&ne2k->sq_mutex);
425 return;
426 }
427
428 /* Upload the frame to the ethernet card */
429 ne2k_upload(ne2k, buf, ne2k->sq.page * DP_PAGE, size);
430 ne2k->sq.dirty = true;
431 ne2k->sq.size = size;
432
433 /* Initialize the transfer */
434 pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page);
435 pio_write_8(ne2k->port + DP_TBCR0, size & 0xff);
436 pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff);
437 pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA);
438 fibril_mutex_unlock(&ne2k->sq_mutex);
439
440 /* Relase packet */
441 nic_release_packet(nic_data, packet);
442}
443
444static nic_frame_t *ne2k_receive_frame(nic_t *nic_data, uint8_t page,
445 size_t length)
446{
447 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
448
449 nic_frame_t *frame = nic_alloc_frame(nic_data, length);
450 if (frame == NULL)
451 return NULL;
452
453 void *buf = packet_suffix(frame->packet, length);
454 bzero(buf, length);
455 uint8_t last = page + length / DP_PAGE;
456
457 if (last >= ne2k->stop_page) {
458 size_t left = (ne2k->stop_page - page) * DP_PAGE
459 - sizeof(recv_header_t);
460 ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
461 left);
462 ne2k_download(ne2k, buf + left, ne2k->start_page * DP_PAGE,
463 length - left);
464 } else {
465 ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
466 length);
467 }
468 return frame;
469}
470
471static void ne2k_receive(nic_t *nic_data)
472{
473 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
474 /*
475 * Allocate memory for the list of received frames.
476 * If the allocation fails here we still receive the
477 * frames from the network, but they will be lost.
478 */
479 nic_frame_list_t *frames = nic_alloc_frame_list();
480 size_t frames_count = 0;
481
482 /* We may block sending in this loop - after so many received frames there
483 * must be some interrupt pending (for the frames not yet downloaded) and
484 * we will continue in its handler. */
485 while (frames_count < 16) {
486 //TODO: isn't some locking necessary here?
487 uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1;
488
489 if (boundary == ne2k->stop_page)
490 boundary = ne2k->start_page;
491
492 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA);
493 uint8_t current = pio_read_8(ne2k->port + DP_CURR);
494 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA);
495 if (current == boundary)
496 /* No more frames to process */
497 break;
498
499 recv_header_t header;
500 size_t size = sizeof(header);
501 size_t offset = boundary * DP_PAGE;
502
503 /* Get the frame header */
504 pio_write_8(ne2k->port + DP_RBCR0, size & 0xff);
505 pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff);
506 pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff);
507 pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff);
508 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
509
510 pio_read_buf_16(ne2k->data_port, (void *) &header, size);
511
512 size_t length =
513 (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size;
514 uint8_t next = header.next;
515
516 if ((length < ETH_MIN_PACK_SIZE)
517 || (length > ETH_MAX_PACK_SIZE_TAGGED)) {
518 next = current;
519 } else if ((header.next < ne2k->start_page)
520 || (header.next > ne2k->stop_page)) {
521 next = current;
522 } else if (header.status & RSR_FO) {
523 /*
524 * This is very serious, so we issue a warning and
525 * reset the buffers.
526 */
527 ne2k->overruns++;
528 next = current;
529 } else if ((header.status & RSR_PRX) && (ne2k->up)) {
530 if (frames != NULL) {
531 nic_frame_t *frame =
532 ne2k_receive_frame(nic_data, boundary, length);
533 if (frame != NULL) {
534 nic_frame_list_append(frames, frame);
535 frames_count++;
536 } else {
537 break;
538 }
539 } else
540 break;
541 }
542
543 /*
544 * Update the boundary pointer
545 * to the value of the page
546 * prior to the next packet to
547 * be processed.
548 */
549 if (next == ne2k->start_page)
550 next = ne2k->stop_page - 1;
551 else
552 next--;
553 pio_write_8(ne2k->port + DP_BNRY, next);
554 }
555 nic_received_frame_list(nic_data, frames);
556}
557
558void ne2k_interrupt(nic_t *nic_data, uint8_t isr, uint8_t tsr)
559{
560 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
561
562 if (isr & (ISR_PTX | ISR_TXE)) {
563 if (tsr & TSR_COL) {
564 nic_report_collisions(nic_data,
565 pio_read_8(ne2k->port + DP_NCR) & 15);
566 }
567
568 if (tsr & TSR_PTX) {
569 // TODO: fix number of sent bytes (but how?)
570 nic_report_send_ok(nic_data, 1, 0);
571 } else if (tsr & TSR_ABT) {
572 nic_report_send_error(nic_data, NIC_SEC_ABORTED, 1);
573 } else if (tsr & TSR_CRS) {
574 nic_report_send_error(nic_data, NIC_SEC_CARRIER_LOST, 1);
575 } else if (tsr & TSR_FU) {
576 ne2k->underruns++;
577 // if (ne2k->underruns < NE2K_ERL) {
578 // }
579 } else if (tsr & TSR_CDH) {
580 nic_report_send_error(nic_data, NIC_SEC_HEARTBEAT, 1);
581 // if (nic_data->stats.send_heartbeat_errors < NE2K_ERL) {
582 // }
583 } else if (tsr & TSR_OWC) {
584 nic_report_send_error(nic_data, NIC_SEC_WINDOW_ERROR, 1);
585 }
586
587 fibril_mutex_lock(&ne2k->sq_mutex);
588 if (ne2k->sq.dirty) {
589 /* Prepare the buffer for next packet */
590 ne2k->sq.dirty = false;
591 ne2k->sq.size = 0;
592
593 /* Signal a next frame to be sent */
594 fibril_condvar_broadcast(&ne2k->sq_cv);
595 } else {
596 ne2k->misses++;
597 // if (ne2k->misses < NE2K_ERL) {
598 // }
599 }
600 fibril_mutex_unlock(&ne2k->sq_mutex);
601 }
602
603 if (isr & ISR_CNT) {
604 unsigned int errors;
605 for (errors = pio_read_8(ne2k->port + DP_CNTR0); errors > 0; --errors)
606 nic_report_receive_error(nic_data, NIC_REC_CRC, 1);
607 for (errors = pio_read_8(ne2k->port + DP_CNTR1); errors > 0; --errors)
608 nic_report_receive_error(nic_data, NIC_REC_FRAME_ALIGNMENT, 1);
609 for (errors = pio_read_8(ne2k->port + DP_CNTR2); errors > 0; --errors)
610 nic_report_receive_error(nic_data, NIC_REC_MISSED, 1);
611 }
612 if (isr & ISR_PRX) {
613 ne2k_receive(nic_data);
614 }
615 if (isr & ISR_RST) {
616 /*
617 * The chip is stopped, and all arrived
618 * frames are delivered.
619 */
620 ne2k_reset(ne2k);
621 }
622
623 /* Unmask interrupts to be processed in the next round */
624 pio_write_8(ne2k->port + DP_IMR,
625 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
626}
627
628void ne2k_set_accept_bcast(ne2k_t *ne2k, int accept)
629{
630 if (accept)
631 ne2k->receive_configuration |= RCR_AB;
632 else
633 ne2k->receive_configuration &= ~RCR_AB;
634
635 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
636}
637
638void ne2k_set_accept_mcast(ne2k_t *ne2k, int accept)
639{
640 if (accept)
641 ne2k->receive_configuration |= RCR_AM;
642 else
643 ne2k->receive_configuration &= ~RCR_AM;
644
645 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
646}
647
648void ne2k_set_promisc_phys(ne2k_t *ne2k, int promisc)
649{
650 if (promisc)
651 ne2k->receive_configuration |= RCR_PRO;
652 else
653 ne2k->receive_configuration &= ~RCR_PRO;
654
655 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
656}
657
658void ne2k_set_mcast_hash(ne2k_t *ne2k, uint64_t hash)
659{
660 /* Select Page 1 and stop all transfers */
661 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
662
663 pio_write_8(ne2k->port + DP_MAR0, (uint8_t) hash);
664 pio_write_8(ne2k->port + DP_MAR1, (uint8_t) (hash >> 8));
665 pio_write_8(ne2k->port + DP_MAR2, (uint8_t) (hash >> 16));
666 pio_write_8(ne2k->port + DP_MAR3, (uint8_t) (hash >> 24));
667 pio_write_8(ne2k->port + DP_MAR4, (uint8_t) (hash >> 32));
668 pio_write_8(ne2k->port + DP_MAR5, (uint8_t) (hash >> 40));
669 pio_write_8(ne2k->port + DP_MAR6, (uint8_t) (hash >> 48));
670 pio_write_8(ne2k->port + DP_MAR7, (uint8_t) (hash >> 56));
671
672 /* Select Page 0 and resume transfers */
673 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
674}
675
676/** @}
677 */
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