source: mainline/uspace/drv/nic/ne2k/dp8390.c@ cbcb34c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cbcb34c was 904b1bc, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix remaining ccheck issues.
  • Property mode set to 100644
File size: 18.3 KB
RevLine 
[80099c19]1/*
2 * Copyright (c) 2009 Lukas Mejdrech
3 * Copyright (c) 2011 Martin Decky
4 * Copyright (c) 2011 Radim Vansa
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * This code is based upon the NE2000 driver for MINIX,
33 * distributed according to a BSD-style license.
34 *
35 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
36 * Copyright (c) 1992, 1994 Philip Homburg
37 * Copyright (c) 1996 G. Falzoni
38 *
39 */
40
41/**
42 * @addtogroup drv_ne2k
43 * @{
44 */
45
46/**
47 * @file
48 * @brief NE2000 driver core
49 *
50 * NE2000 (based on DP8390) network interface core implementation.
51 * Only the basic NE2000 PIO (ISA) interface is supported, remote
52 * DMA is completely absent from this code for simplicity.
53 *
54 */
55
56#include <assert.h>
[f300523]57#include <async.h>
[80099c19]58#include <byteorder.h>
59#include <errno.h>
60#include <stdio.h>
[1ae74c6]61#include <ddi.h>
[80099c19]62#include "dp8390.h"
63
64/** Page size */
65#define DP_PAGE 256
66
67/** 6 * DP_PAGE >= 1514 bytes */
68#define SQ_PAGES 6
69
70/** Type definition of the receive header
71 *
72 */
73typedef struct {
74 /** Copy of RSR */
75 uint8_t status;
[a35b458]76
[1bc35b5]77 /** Pointer to next frame */
[80099c19]78 uint8_t next;
[a35b458]79
[80099c19]80 /** Receive Byte Count Low */
81 uint8_t rbcl;
[a35b458]82
[80099c19]83 /** Receive Byte Count High */
84 uint8_t rbch;
85} recv_header_t;
86
87/** Read a memory block word by word.
88 *
89 * @param[in] port Source address.
90 * @param[out] buf Destination buffer.
91 * @param[in] size Memory block size in bytes.
92 *
93 */
94static void pio_read_buf_16(void *port, void *buf, size_t size)
95{
96 size_t i;
[a35b458]97
[80099c19]98 for (i = 0; (i << 1) < size; i++)
99 *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port));
100}
101
102/** Write a memory block word by word.
103 *
104 * @param[in] port Destination address.
105 * @param[in] buf Source buffer.
106 * @param[in] size Memory block size in bytes.
107 *
108 */
109static void pio_write_buf_16(void *port, void *buf, size_t size)
110{
111 size_t i;
[a35b458]112
[80099c19]113 for (i = 0; (i << 1) < size; i++)
114 pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i));
115}
116
117static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
118{
119 size_t esize = size & ~1;
[a35b458]120
[80099c19]121 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
122 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
123 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
124 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
125 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
[a35b458]126
[80099c19]127 if (esize != 0) {
128 pio_read_buf_16(ne2k->data_port, buf, esize);
129 size -= esize;
130 buf += esize;
131 }
[a35b458]132
[80099c19]133 if (size) {
134 assert(size == 1);
[a35b458]135
[80099c19]136 uint16_t word = pio_read_16(ne2k->data_port);
137 memcpy(buf, &word, 1);
138 }
139}
140
141static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
142{
[cd79391]143 size_t esize_ru = (size + 1) & ~1;
[80099c19]144 size_t esize = size & ~1;
[a35b458]145
[cd79391]146 pio_write_8(ne2k->port + DP_RBCR0, esize_ru & 0xff);
147 pio_write_8(ne2k->port + DP_RBCR1, (esize_ru >> 8) & 0xff);
[80099c19]148 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
149 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
150 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
[a35b458]151
[80099c19]152 if (esize != 0) {
153 pio_write_buf_16(ne2k->data_port, buf, esize);
154 size -= esize;
155 buf += esize;
156 }
[a35b458]157
[80099c19]158 if (size) {
159 assert(size == 1);
[a35b458]160
[80099c19]161 uint16_t word = 0;
[a35b458]162
[80099c19]163 memcpy(&word, buf, 1);
164 pio_write_16(ne2k->data_port, word);
165 }
166}
167
168static void ne2k_init(ne2k_t *ne2k)
169{
170 unsigned int i;
[a35b458]171
[80099c19]172 /* Reset the ethernet card */
173 uint8_t val = pio_read_8(ne2k->port + NE2K_RESET);
[f300523]174 async_usleep(2000);
[80099c19]175 pio_write_8(ne2k->port + NE2K_RESET, val);
[f300523]176 async_usleep(2000);
[a35b458]177
[80099c19]178 /* Reset the DP8390 */
179 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
180 for (i = 0; i < NE2K_RETRY; i++) {
181 if (pio_read_8(ne2k->port + DP_ISR) != 0)
182 break;
183 }
184}
185
186/** Probe and initialize the network interface.
187 *
188 * @param[in,out] ne2k Network interface structure.
189 * @param[in] port Device address.
190 * @param[in] irq Device interrupt vector.
191 *
192 * @return EOK on success.
193 * @return EXDEV if the network interface was not recognized.
194 *
195 */
[b7fd2a0]196errno_t ne2k_probe(ne2k_t *ne2k)
[80099c19]197{
198 unsigned int i;
[a35b458]199
[80099c19]200 ne2k_init(ne2k);
[a35b458]201
[80099c19]202 /* Check if the DP8390 is really there */
203 uint8_t val = pio_read_8(ne2k->port + DP_CR);
[7030bc9]204 if ((val & (CR_STP | CR_TXP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT))
[80099c19]205 return EXDEV;
[a35b458]206
[80099c19]207 /* Disable the receiver and init TCR and DCR */
208 pio_write_8(ne2k->port + DP_RCR, RCR_MON);
209 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
210 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
[a35b458]211
[80099c19]212 /* Setup a transfer to get the MAC address */
213 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
214 pio_write_8(ne2k->port + DP_RBCR1, 0);
215 pio_write_8(ne2k->port + DP_RSAR0, 0);
216 pio_write_8(ne2k->port + DP_RSAR1, 0);
217 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
[a35b458]218
[80099c19]219 for (i = 0; i < ETH_ADDR; i++)
220 ne2k->mac.address[i] = pio_read_16(ne2k->data_port);
[a35b458]221
[80099c19]222 return EOK;
223}
224
225void ne2k_set_physical_address(ne2k_t *ne2k, const nic_address_t *address)
226{
227 memcpy(&ne2k->mac, address, sizeof(nic_address_t));
[a35b458]228
[80099c19]229 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STP);
[a35b458]230
[80099c19]231 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
232 pio_write_8(ne2k->port + DP_RBCR1, 0);
233 pio_write_8(ne2k->port + DP_RSAR0, 0);
234 pio_write_8(ne2k->port + DP_RSAR1, 0);
235 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
236
237 size_t i;
238 for (i = 0; i < ETH_ADDR; i++)
239 pio_write_16(ne2k->data_port, ne2k->mac.address[i]);
240
241 //pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
242}
243
244/** Start the network interface.
245 *
246 * @param[in,out] ne2k Network interface structure.
247 *
248 * @return EOK on success.
249 * @return EXDEV if the network interface is disabled.
250 *
251 */
[b7fd2a0]252errno_t ne2k_up(ne2k_t *ne2k)
[80099c19]253{
254 if (!ne2k->probed)
255 return EXDEV;
[a35b458]256
[80099c19]257 ne2k_init(ne2k);
[a35b458]258
[80099c19]259 /*
260 * Setup send queue. Use the first
261 * SQ_PAGES of NE2000 memory for the send
262 * buffer.
263 */
264 ne2k->sq.dirty = false;
265 ne2k->sq.page = NE2K_START / DP_PAGE;
266 fibril_mutex_initialize(&ne2k->sq_mutex);
267 fibril_condvar_initialize(&ne2k->sq_cv);
[a35b458]268
[80099c19]269 /*
270 * Setup receive ring buffer. Use all the rest
271 * of the NE2000 memory (except the first SQ_PAGES
272 * reserved for the send buffer) for the receive
273 * ring buffer.
274 */
275 ne2k->start_page = ne2k->sq.page + SQ_PAGES;
276 ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE;
[a35b458]277
[80099c19]278 /*
279 * Initialization of the DP8390 following the mandatory procedure
280 * in reference manual ("DP8390D/NS32490D NIC Network Interface
281 * Controller", National Semiconductor, July 1995, Page 29).
282 */
[a35b458]283
[80099c19]284 /* Step 1: */
285 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
[a35b458]286
[80099c19]287 /* Step 2: */
288 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
[a35b458]289
[80099c19]290 /* Step 3: */
291 pio_write_8(ne2k->port + DP_RBCR0, 0);
292 pio_write_8(ne2k->port + DP_RBCR1, 0);
[a35b458]293
[80099c19]294 /* Step 4: */
295 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
[a35b458]296
[80099c19]297 /* Step 5: */
298 pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL);
[a35b458]299
[80099c19]300 /* Step 6: */
301 pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page);
302 pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page);
303 pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page);
[a35b458]304
[80099c19]305 /* Step 7: */
306 pio_write_8(ne2k->port + DP_ISR, 0xff);
[a35b458]307
[80099c19]308 /* Step 8: */
309 pio_write_8(ne2k->port + DP_IMR,
310 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
[a35b458]311
[80099c19]312 /* Step 9: */
313 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
[a35b458]314
[80099c19]315 pio_write_8(ne2k->port + DP_PAR0, ne2k->mac.address[0]);
316 pio_write_8(ne2k->port + DP_PAR1, ne2k->mac.address[1]);
317 pio_write_8(ne2k->port + DP_PAR2, ne2k->mac.address[2]);
318 pio_write_8(ne2k->port + DP_PAR3, ne2k->mac.address[3]);
319 pio_write_8(ne2k->port + DP_PAR4, ne2k->mac.address[4]);
320 pio_write_8(ne2k->port + DP_PAR5, ne2k->mac.address[5]);
[a35b458]321
[80099c19]322 pio_write_8(ne2k->port + DP_MAR0, 0);
323 pio_write_8(ne2k->port + DP_MAR1, 0);
324 pio_write_8(ne2k->port + DP_MAR2, 0);
325 pio_write_8(ne2k->port + DP_MAR3, 0);
326 pio_write_8(ne2k->port + DP_MAR4, 0);
327 pio_write_8(ne2k->port + DP_MAR5, 0);
328 pio_write_8(ne2k->port + DP_MAR6, 0);
329 pio_write_8(ne2k->port + DP_MAR7, 0);
[a35b458]330
[80099c19]331 pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1);
[a35b458]332
[80099c19]333 /* Step 10: */
334 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
[a35b458]335
[80099c19]336 /* Step 11: */
337 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
[a35b458]338
[80099c19]339 /* Reset counters by reading */
340 pio_read_8(ne2k->port + DP_CNTR0);
341 pio_read_8(ne2k->port + DP_CNTR1);
342 pio_read_8(ne2k->port + DP_CNTR2);
[a35b458]343
[80099c19]344 /* Finish the initialization */
345 ne2k->up = true;
346 return EOK;
347}
348
349/** Stop the network interface.
350 *
351 * @param[in,out] ne2k Network interface structure.
352 *
353 */
354void ne2k_down(ne2k_t *ne2k)
355{
356 if ((ne2k->probed) && (ne2k->up)) {
357 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
358 ne2k_init(ne2k);
359 ne2k->up = false;
360 }
361}
362
363static void ne2k_reset(ne2k_t *ne2k)
364{
365 unsigned int i;
366
367 fibril_mutex_lock(&ne2k->sq_mutex);
368
369 /* Stop the chip */
370 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
371 pio_write_8(ne2k->port + DP_RBCR0, 0);
372 pio_write_8(ne2k->port + DP_RBCR1, 0);
373
374 for (i = 0; i < NE2K_RETRY; i++) {
375 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0)
376 break;
377 }
378
379 pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST);
380 pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT);
381 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
382
383 /* Acknowledge the ISR_RDC (remote DMA) interrupt */
384 for (i = 0; i < NE2K_RETRY; i++) {
385 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0)
386 break;
387 }
388
389 uint8_t val = pio_read_8(ne2k->port + DP_ISR);
390 pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC);
391
392 /*
393 * Reset the transmit ring. If we were transmitting a frame,
[1bc35b5]394 * we pretend that the frame is processed. Higher layers will
395 * retransmit if the frame wasn't actually sent.
[80099c19]396 */
397 ne2k->sq.dirty = false;
398
399 fibril_mutex_unlock(&ne2k->sq_mutex);
400}
401
402/** Send a frame.
403 *
404 * @param[in,out] ne2k Network interface structure.
[6d8455d]405 * @param[in] data Pointer to frame data
406 * @param[in] size Frame size in bytes
[80099c19]407 *
408 */
[6d8455d]409void ne2k_send(nic_t *nic_data, void *data, size_t size)
[80099c19]410{
411 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
412
413 assert(ne2k->probed);
414 assert(ne2k->up);
415
416 fibril_mutex_lock(&ne2k->sq_mutex);
[a35b458]417
[80099c19]418 while (ne2k->sq.dirty) {
419 fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex);
420 }
[a35b458]421
[80099c19]422 if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) {
423 fibril_mutex_unlock(&ne2k->sq_mutex);
424 return;
425 }
426
427 /* Upload the frame to the ethernet card */
[6d8455d]428 ne2k_upload(ne2k, data, ne2k->sq.page * DP_PAGE, size);
[80099c19]429 ne2k->sq.dirty = true;
430 ne2k->sq.size = size;
431
432 /* Initialize the transfer */
433 pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page);
434 pio_write_8(ne2k->port + DP_TBCR0, size & 0xff);
435 pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff);
436 pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA);
437 fibril_mutex_unlock(&ne2k->sq_mutex);
438}
439
440static nic_frame_t *ne2k_receive_frame(nic_t *nic_data, uint8_t page,
[3bacee1]441 size_t length)
[80099c19]442{
443 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
444
445 nic_frame_t *frame = nic_alloc_frame(nic_data, length);
446 if (frame == NULL)
447 return NULL;
[a35b458]448
[acdb5bac]449 memset(frame->data, 0, length);
[80099c19]450 uint8_t last = page + length / DP_PAGE;
[a35b458]451
[80099c19]452 if (last >= ne2k->stop_page) {
[3bacee1]453 size_t left = (ne2k->stop_page - page) * DP_PAGE -
454 sizeof(recv_header_t);
[1bc35b5]455 ne2k_download(ne2k, frame->data, page * DP_PAGE + sizeof(recv_header_t),
[80099c19]456 left);
[1bc35b5]457 ne2k_download(ne2k, frame->data + left, ne2k->start_page * DP_PAGE,
[80099c19]458 length - left);
459 } else {
[1bc35b5]460 ne2k_download(ne2k, frame->data, page * DP_PAGE + sizeof(recv_header_t),
[80099c19]461 length);
462 }
463 return frame;
464}
465
466static void ne2k_receive(nic_t *nic_data)
467{
468 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
469 /*
470 * Allocate memory for the list of received frames.
471 * If the allocation fails here we still receive the
472 * frames from the network, but they will be lost.
473 */
474 nic_frame_list_t *frames = nic_alloc_frame_list();
475 size_t frames_count = 0;
476
[904b1bc]477 /*
478 * We may block sending in this loop - after so many received frames there
[80099c19]479 * must be some interrupt pending (for the frames not yet downloaded) and
[904b1bc]480 * we will continue in its handler.
481 */
[80099c19]482 while (frames_count < 16) {
483 //TODO: isn't some locking necessary here?
484 uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1;
[a35b458]485
[80099c19]486 if (boundary == ne2k->stop_page)
487 boundary = ne2k->start_page;
[a35b458]488
[80099c19]489 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA);
490 uint8_t current = pio_read_8(ne2k->port + DP_CURR);
491 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA);
492 if (current == boundary)
493 /* No more frames to process */
494 break;
[a35b458]495
[80099c19]496 recv_header_t header;
497 size_t size = sizeof(header);
498 size_t offset = boundary * DP_PAGE;
[a35b458]499
[80099c19]500 /* Get the frame header */
501 pio_write_8(ne2k->port + DP_RBCR0, size & 0xff);
502 pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff);
503 pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff);
504 pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff);
505 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
[a35b458]506
[80099c19]507 pio_read_buf_16(ne2k->data_port, (void *) &header, size);
508
509 size_t length =
510 (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size;
511 uint8_t next = header.next;
[a35b458]512
[3bacee1]513 if ((length < ETH_MIN_PACK_SIZE) ||
514 (length > ETH_MAX_PACK_SIZE_TAGGED)) {
[80099c19]515 next = current;
[3bacee1]516 } else if ((header.next < ne2k->start_page) ||
517 (header.next > ne2k->stop_page)) {
[80099c19]518 next = current;
519 } else if (header.status & RSR_FO) {
520 /*
521 * This is very serious, so we issue a warning and
522 * reset the buffers.
523 */
524 ne2k->overruns++;
525 next = current;
526 } else if ((header.status & RSR_PRX) && (ne2k->up)) {
527 if (frames != NULL) {
528 nic_frame_t *frame =
[3bacee1]529 ne2k_receive_frame(nic_data, boundary, length);
[80099c19]530 if (frame != NULL) {
531 nic_frame_list_append(frames, frame);
532 frames_count++;
533 } else {
534 break;
535 }
536 } else
537 break;
538 }
[a35b458]539
[80099c19]540 /*
541 * Update the boundary pointer
542 * to the value of the page
[1bc35b5]543 * prior to the next frame to
[80099c19]544 * be processed.
545 */
546 if (next == ne2k->start_page)
547 next = ne2k->stop_page - 1;
548 else
549 next--;
550 pio_write_8(ne2k->port + DP_BNRY, next);
551 }
552 nic_received_frame_list(nic_data, frames);
553}
554
555void ne2k_interrupt(nic_t *nic_data, uint8_t isr, uint8_t tsr)
556{
557 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
558
559 if (isr & (ISR_PTX | ISR_TXE)) {
560 if (tsr & TSR_COL) {
561 nic_report_collisions(nic_data,
[3bacee1]562 pio_read_8(ne2k->port + DP_NCR) & 15);
[80099c19]563 }
564
565 if (tsr & TSR_PTX) {
566 // TODO: fix number of sent bytes (but how?)
567 nic_report_send_ok(nic_data, 1, 0);
568 } else if (tsr & TSR_ABT) {
569 nic_report_send_error(nic_data, NIC_SEC_ABORTED, 1);
570 } else if (tsr & TSR_CRS) {
571 nic_report_send_error(nic_data, NIC_SEC_CARRIER_LOST, 1);
572 } else if (tsr & TSR_FU) {
573 ne2k->underruns++;
574 // if (ne2k->underruns < NE2K_ERL) {
575 // }
576 } else if (tsr & TSR_CDH) {
577 nic_report_send_error(nic_data, NIC_SEC_HEARTBEAT, 1);
578 // if (nic_data->stats.send_heartbeat_errors < NE2K_ERL) {
579 // }
580 } else if (tsr & TSR_OWC) {
581 nic_report_send_error(nic_data, NIC_SEC_WINDOW_ERROR, 1);
582 }
583
584 fibril_mutex_lock(&ne2k->sq_mutex);
585 if (ne2k->sq.dirty) {
[1bc35b5]586 /* Prepare the buffer for next frame */
[80099c19]587 ne2k->sq.dirty = false;
588 ne2k->sq.size = 0;
[a35b458]589
[80099c19]590 /* Signal a next frame to be sent */
591 fibril_condvar_broadcast(&ne2k->sq_cv);
592 } else {
593 ne2k->misses++;
594 // if (ne2k->misses < NE2K_ERL) {
595 // }
596 }
597 fibril_mutex_unlock(&ne2k->sq_mutex);
598 }
599
600 if (isr & ISR_CNT) {
601 unsigned int errors;
602 for (errors = pio_read_8(ne2k->port + DP_CNTR0); errors > 0; --errors)
603 nic_report_receive_error(nic_data, NIC_REC_CRC, 1);
604 for (errors = pio_read_8(ne2k->port + DP_CNTR1); errors > 0; --errors)
605 nic_report_receive_error(nic_data, NIC_REC_FRAME_ALIGNMENT, 1);
606 for (errors = pio_read_8(ne2k->port + DP_CNTR2); errors > 0; --errors)
607 nic_report_receive_error(nic_data, NIC_REC_MISSED, 1);
608 }
609 if (isr & ISR_PRX) {
610 ne2k_receive(nic_data);
611 }
612 if (isr & ISR_RST) {
613 /*
614 * The chip is stopped, and all arrived
615 * frames are delivered.
616 */
617 ne2k_reset(ne2k);
618 }
[a35b458]619
[80099c19]620 /* Unmask interrupts to be processed in the next round */
621 pio_write_8(ne2k->port + DP_IMR,
622 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
623}
624
625void ne2k_set_accept_bcast(ne2k_t *ne2k, int accept)
626{
627 if (accept)
628 ne2k->receive_configuration |= RCR_AB;
629 else
630 ne2k->receive_configuration &= ~RCR_AB;
[a35b458]631
[80099c19]632 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
633}
634
635void ne2k_set_accept_mcast(ne2k_t *ne2k, int accept)
636{
637 if (accept)
638 ne2k->receive_configuration |= RCR_AM;
639 else
640 ne2k->receive_configuration &= ~RCR_AM;
[a35b458]641
[80099c19]642 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
643}
644
645void ne2k_set_promisc_phys(ne2k_t *ne2k, int promisc)
646{
647 if (promisc)
648 ne2k->receive_configuration |= RCR_PRO;
649 else
650 ne2k->receive_configuration &= ~RCR_PRO;
[a35b458]651
[80099c19]652 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
653}
654
655void ne2k_set_mcast_hash(ne2k_t *ne2k, uint64_t hash)
656{
657 /* Select Page 1 and stop all transfers */
658 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
[a35b458]659
[80099c19]660 pio_write_8(ne2k->port + DP_MAR0, (uint8_t) hash);
661 pio_write_8(ne2k->port + DP_MAR1, (uint8_t) (hash >> 8));
662 pio_write_8(ne2k->port + DP_MAR2, (uint8_t) (hash >> 16));
663 pio_write_8(ne2k->port + DP_MAR3, (uint8_t) (hash >> 24));
664 pio_write_8(ne2k->port + DP_MAR4, (uint8_t) (hash >> 32));
665 pio_write_8(ne2k->port + DP_MAR5, (uint8_t) (hash >> 40));
666 pio_write_8(ne2k->port + DP_MAR6, (uint8_t) (hash >> 48));
667 pio_write_8(ne2k->port + DP_MAR7, (uint8_t) (hash >> 56));
[a35b458]668
[80099c19]669 /* Select Page 0 and resume transfers */
670 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
671}
672
673/** @}
674 */
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