source: mainline/uspace/drv/nic/ne2k/dp8390.c

Last change on this file was 1c7b0db7, checked in by Jiri Svoboda <jiri@…>, 5 months ago

Implement quiesce in NE2k, RTL8139 and RTL8169.
  • Property mode set to 100644
File size: 18.4 KB
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[80099c19]1/*
[1c7b0db7]2 * Copyright (c) 2025 Jiri Svoboda
[80099c19]3 * Copyright (c) 2009 Lukas Mejdrech
4 * Copyright (c) 2011 Martin Decky
5 * Copyright (c) 2011 Radim Vansa
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * - Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * - Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * - The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * This code is based upon the NE2000 driver for MINIX,
34 * distributed according to a BSD-style license.
35 *
36 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
37 * Copyright (c) 1992, 1994 Philip Homburg
38 * Copyright (c) 1996 G. Falzoni
39 *
40 */
41
42/**
43 * @addtogroup drv_ne2k
44 * @{
45 */
46
47/**
48 * @file
49 * @brief NE2000 driver core
50 *
51 * NE2000 (based on DP8390) network interface core implementation.
52 * Only the basic NE2000 PIO (ISA) interface is supported, remote
53 * DMA is completely absent from this code for simplicity.
54 *
55 */
56
57#include <assert.h>
[f300523]58#include <async.h>
[80099c19]59#include <byteorder.h>
60#include <errno.h>
61#include <stdio.h>
[1ae74c6]62#include <ddi.h>
[80099c19]63#include "dp8390.h"
64
65/** Page size */
66#define DP_PAGE 256
67
68/** 6 * DP_PAGE >= 1514 bytes */
69#define SQ_PAGES 6
70
71/** Type definition of the receive header
72 *
73 */
74typedef struct {
75 /** Copy of RSR */
76 uint8_t status;
[a35b458]77
[1bc35b5]78 /** Pointer to next frame */
[80099c19]79 uint8_t next;
[a35b458]80
[80099c19]81 /** Receive Byte Count Low */
82 uint8_t rbcl;
[a35b458]83
[80099c19]84 /** Receive Byte Count High */
85 uint8_t rbch;
86} recv_header_t;
87
88/** Read a memory block word by word.
89 *
90 * @param[in] port Source address.
91 * @param[out] buf Destination buffer.
92 * @param[in] size Memory block size in bytes.
93 *
94 */
95static void pio_read_buf_16(void *port, void *buf, size_t size)
96{
97 size_t i;
[a35b458]98
[80099c19]99 for (i = 0; (i << 1) < size; i++)
100 *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port));
101}
102
103/** Write a memory block word by word.
104 *
105 * @param[in] port Destination address.
106 * @param[in] buf Source buffer.
107 * @param[in] size Memory block size in bytes.
108 *
109 */
110static void pio_write_buf_16(void *port, void *buf, size_t size)
111{
112 size_t i;
[a35b458]113
[80099c19]114 for (i = 0; (i << 1) < size; i++)
115 pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i));
116}
117
118static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
119{
120 size_t esize = size & ~1;
[a35b458]121
[80099c19]122 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
123 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
124 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
125 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
126 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
[a35b458]127
[80099c19]128 if (esize != 0) {
129 pio_read_buf_16(ne2k->data_port, buf, esize);
130 size -= esize;
131 buf += esize;
132 }
[a35b458]133
[80099c19]134 if (size) {
135 assert(size == 1);
[a35b458]136
[80099c19]137 uint16_t word = pio_read_16(ne2k->data_port);
138 memcpy(buf, &word, 1);
139 }
140}
141
142static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
143{
[cd79391]144 size_t esize_ru = (size + 1) & ~1;
[80099c19]145 size_t esize = size & ~1;
[a35b458]146
[cd79391]147 pio_write_8(ne2k->port + DP_RBCR0, esize_ru & 0xff);
148 pio_write_8(ne2k->port + DP_RBCR1, (esize_ru >> 8) & 0xff);
[80099c19]149 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
150 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
151 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
[a35b458]152
[80099c19]153 if (esize != 0) {
154 pio_write_buf_16(ne2k->data_port, buf, esize);
155 size -= esize;
156 buf += esize;
157 }
[a35b458]158
[80099c19]159 if (size) {
160 assert(size == 1);
[a35b458]161
[80099c19]162 uint16_t word = 0;
[a35b458]163
[80099c19]164 memcpy(&word, buf, 1);
165 pio_write_16(ne2k->data_port, word);
166 }
167}
168
169static void ne2k_init(ne2k_t *ne2k)
170{
171 unsigned int i;
[a35b458]172
[80099c19]173 /* Reset the ethernet card */
174 uint8_t val = pio_read_8(ne2k->port + NE2K_RESET);
[5f97ef44]175 fibril_usleep(2000);
[80099c19]176 pio_write_8(ne2k->port + NE2K_RESET, val);
[5f97ef44]177 fibril_usleep(2000);
[a35b458]178
[80099c19]179 /* Reset the DP8390 */
180 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
181 for (i = 0; i < NE2K_RETRY; i++) {
182 if (pio_read_8(ne2k->port + DP_ISR) != 0)
183 break;
184 }
185}
186
[1c7b0db7]187/** Quiesce NE2000.
188 *
189 * @param ne2k NE2000
190 */
191void ne2k_quiesce(ne2k_t *ne2k)
192{
193 ne2k_init(ne2k);
194}
195
[80099c19]196/** Probe and initialize the network interface.
197 *
198 * @param[in,out] ne2k Network interface structure.
199 * @param[in] port Device address.
200 * @param[in] irq Device interrupt vector.
201 *
202 * @return EOK on success.
203 * @return EXDEV if the network interface was not recognized.
204 *
205 */
[b7fd2a0]206errno_t ne2k_probe(ne2k_t *ne2k)
[80099c19]207{
208 unsigned int i;
[a35b458]209
[80099c19]210 ne2k_init(ne2k);
[a35b458]211
[80099c19]212 /* Check if the DP8390 is really there */
213 uint8_t val = pio_read_8(ne2k->port + DP_CR);
[7030bc9]214 if ((val & (CR_STP | CR_TXP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT))
[80099c19]215 return EXDEV;
[a35b458]216
[80099c19]217 /* Disable the receiver and init TCR and DCR */
218 pio_write_8(ne2k->port + DP_RCR, RCR_MON);
219 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
220 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
[a35b458]221
[80099c19]222 /* Setup a transfer to get the MAC address */
223 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
224 pio_write_8(ne2k->port + DP_RBCR1, 0);
225 pio_write_8(ne2k->port + DP_RSAR0, 0);
226 pio_write_8(ne2k->port + DP_RSAR1, 0);
227 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
[a35b458]228
[80099c19]229 for (i = 0; i < ETH_ADDR; i++)
230 ne2k->mac.address[i] = pio_read_16(ne2k->data_port);
[a35b458]231
[80099c19]232 return EOK;
233}
234
235void ne2k_set_physical_address(ne2k_t *ne2k, const nic_address_t *address)
236{
237 memcpy(&ne2k->mac, address, sizeof(nic_address_t));
[a35b458]238
[80099c19]239 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STP);
[a35b458]240
[80099c19]241 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
242 pio_write_8(ne2k->port + DP_RBCR1, 0);
243 pio_write_8(ne2k->port + DP_RSAR0, 0);
244 pio_write_8(ne2k->port + DP_RSAR1, 0);
245 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
246
247 size_t i;
248 for (i = 0; i < ETH_ADDR; i++)
249 pio_write_16(ne2k->data_port, ne2k->mac.address[i]);
250
251 //pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
252}
253
254/** Start the network interface.
255 *
256 * @param[in,out] ne2k Network interface structure.
257 *
258 * @return EOK on success.
259 * @return EXDEV if the network interface is disabled.
260 *
261 */
[b7fd2a0]262errno_t ne2k_up(ne2k_t *ne2k)
[80099c19]263{
264 if (!ne2k->probed)
265 return EXDEV;
[a35b458]266
[80099c19]267 ne2k_init(ne2k);
[a35b458]268
[80099c19]269 /*
270 * Setup send queue. Use the first
271 * SQ_PAGES of NE2000 memory for the send
272 * buffer.
273 */
274 ne2k->sq.dirty = false;
275 ne2k->sq.page = NE2K_START / DP_PAGE;
276 fibril_mutex_initialize(&ne2k->sq_mutex);
277 fibril_condvar_initialize(&ne2k->sq_cv);
[a35b458]278
[80099c19]279 /*
280 * Setup receive ring buffer. Use all the rest
281 * of the NE2000 memory (except the first SQ_PAGES
282 * reserved for the send buffer) for the receive
283 * ring buffer.
284 */
285 ne2k->start_page = ne2k->sq.page + SQ_PAGES;
286 ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE;
[a35b458]287
[80099c19]288 /*
289 * Initialization of the DP8390 following the mandatory procedure
290 * in reference manual ("DP8390D/NS32490D NIC Network Interface
291 * Controller", National Semiconductor, July 1995, Page 29).
292 */
[a35b458]293
[80099c19]294 /* Step 1: */
295 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
[a35b458]296
[80099c19]297 /* Step 2: */
298 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
[a35b458]299
[80099c19]300 /* Step 3: */
301 pio_write_8(ne2k->port + DP_RBCR0, 0);
302 pio_write_8(ne2k->port + DP_RBCR1, 0);
[a35b458]303
[80099c19]304 /* Step 4: */
305 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
[a35b458]306
[80099c19]307 /* Step 5: */
308 pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL);
[a35b458]309
[80099c19]310 /* Step 6: */
311 pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page);
312 pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page);
313 pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page);
[a35b458]314
[80099c19]315 /* Step 7: */
316 pio_write_8(ne2k->port + DP_ISR, 0xff);
[a35b458]317
[80099c19]318 /* Step 8: */
319 pio_write_8(ne2k->port + DP_IMR,
320 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
[a35b458]321
[80099c19]322 /* Step 9: */
323 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
[a35b458]324
[80099c19]325 pio_write_8(ne2k->port + DP_PAR0, ne2k->mac.address[0]);
326 pio_write_8(ne2k->port + DP_PAR1, ne2k->mac.address[1]);
327 pio_write_8(ne2k->port + DP_PAR2, ne2k->mac.address[2]);
328 pio_write_8(ne2k->port + DP_PAR3, ne2k->mac.address[3]);
329 pio_write_8(ne2k->port + DP_PAR4, ne2k->mac.address[4]);
330 pio_write_8(ne2k->port + DP_PAR5, ne2k->mac.address[5]);
[a35b458]331
[80099c19]332 pio_write_8(ne2k->port + DP_MAR0, 0);
333 pio_write_8(ne2k->port + DP_MAR1, 0);
334 pio_write_8(ne2k->port + DP_MAR2, 0);
335 pio_write_8(ne2k->port + DP_MAR3, 0);
336 pio_write_8(ne2k->port + DP_MAR4, 0);
337 pio_write_8(ne2k->port + DP_MAR5, 0);
338 pio_write_8(ne2k->port + DP_MAR6, 0);
339 pio_write_8(ne2k->port + DP_MAR7, 0);
[a35b458]340
[80099c19]341 pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1);
[a35b458]342
[80099c19]343 /* Step 10: */
344 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
[a35b458]345
[80099c19]346 /* Step 11: */
347 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
[a35b458]348
[80099c19]349 /* Reset counters by reading */
350 pio_read_8(ne2k->port + DP_CNTR0);
351 pio_read_8(ne2k->port + DP_CNTR1);
352 pio_read_8(ne2k->port + DP_CNTR2);
[a35b458]353
[80099c19]354 /* Finish the initialization */
355 ne2k->up = true;
356 return EOK;
357}
358
359/** Stop the network interface.
360 *
361 * @param[in,out] ne2k Network interface structure.
362 *
363 */
364void ne2k_down(ne2k_t *ne2k)
365{
366 if ((ne2k->probed) && (ne2k->up)) {
367 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
368 ne2k_init(ne2k);
369 ne2k->up = false;
370 }
371}
372
373static void ne2k_reset(ne2k_t *ne2k)
374{
375 unsigned int i;
376
377 fibril_mutex_lock(&ne2k->sq_mutex);
378
379 /* Stop the chip */
380 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
381 pio_write_8(ne2k->port + DP_RBCR0, 0);
382 pio_write_8(ne2k->port + DP_RBCR1, 0);
383
384 for (i = 0; i < NE2K_RETRY; i++) {
385 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0)
386 break;
387 }
388
389 pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST);
390 pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT);
391 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
392
393 /* Acknowledge the ISR_RDC (remote DMA) interrupt */
394 for (i = 0; i < NE2K_RETRY; i++) {
395 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0)
396 break;
397 }
398
399 uint8_t val = pio_read_8(ne2k->port + DP_ISR);
400 pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC);
401
402 /*
403 * Reset the transmit ring. If we were transmitting a frame,
[1bc35b5]404 * we pretend that the frame is processed. Higher layers will
405 * retransmit if the frame wasn't actually sent.
[80099c19]406 */
407 ne2k->sq.dirty = false;
408
409 fibril_mutex_unlock(&ne2k->sq_mutex);
410}
411
412/** Send a frame.
413 *
414 * @param[in,out] ne2k Network interface structure.
[6d8455d]415 * @param[in] data Pointer to frame data
416 * @param[in] size Frame size in bytes
[80099c19]417 *
418 */
[6d8455d]419void ne2k_send(nic_t *nic_data, void *data, size_t size)
[80099c19]420{
421 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
422
423 assert(ne2k->probed);
424 assert(ne2k->up);
425
426 fibril_mutex_lock(&ne2k->sq_mutex);
[a35b458]427
[80099c19]428 while (ne2k->sq.dirty) {
429 fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex);
430 }
[a35b458]431
[80099c19]432 if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) {
433 fibril_mutex_unlock(&ne2k->sq_mutex);
434 return;
435 }
436
437 /* Upload the frame to the ethernet card */
[6d8455d]438 ne2k_upload(ne2k, data, ne2k->sq.page * DP_PAGE, size);
[80099c19]439 ne2k->sq.dirty = true;
440 ne2k->sq.size = size;
441
442 /* Initialize the transfer */
443 pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page);
444 pio_write_8(ne2k->port + DP_TBCR0, size & 0xff);
445 pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff);
446 pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA);
447 fibril_mutex_unlock(&ne2k->sq_mutex);
448}
449
450static nic_frame_t *ne2k_receive_frame(nic_t *nic_data, uint8_t page,
[3bacee1]451 size_t length)
[80099c19]452{
453 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
454
455 nic_frame_t *frame = nic_alloc_frame(nic_data, length);
456 if (frame == NULL)
457 return NULL;
[a35b458]458
[acdb5bac]459 memset(frame->data, 0, length);
[80099c19]460 uint8_t last = page + length / DP_PAGE;
[a35b458]461
[80099c19]462 if (last >= ne2k->stop_page) {
[3bacee1]463 size_t left = (ne2k->stop_page - page) * DP_PAGE -
464 sizeof(recv_header_t);
[1bc35b5]465 ne2k_download(ne2k, frame->data, page * DP_PAGE + sizeof(recv_header_t),
[80099c19]466 left);
[1bc35b5]467 ne2k_download(ne2k, frame->data + left, ne2k->start_page * DP_PAGE,
[80099c19]468 length - left);
469 } else {
[1bc35b5]470 ne2k_download(ne2k, frame->data, page * DP_PAGE + sizeof(recv_header_t),
[80099c19]471 length);
472 }
473 return frame;
474}
475
476static void ne2k_receive(nic_t *nic_data)
477{
478 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
479 /*
480 * Allocate memory for the list of received frames.
481 * If the allocation fails here we still receive the
482 * frames from the network, but they will be lost.
483 */
484 nic_frame_list_t *frames = nic_alloc_frame_list();
485 size_t frames_count = 0;
486
[904b1bc]487 /*
488 * We may block sending in this loop - after so many received frames there
[80099c19]489 * must be some interrupt pending (for the frames not yet downloaded) and
[904b1bc]490 * we will continue in its handler.
491 */
[80099c19]492 while (frames_count < 16) {
493 //TODO: isn't some locking necessary here?
494 uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1;
[a35b458]495
[80099c19]496 if (boundary == ne2k->stop_page)
497 boundary = ne2k->start_page;
[a35b458]498
[80099c19]499 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA);
500 uint8_t current = pio_read_8(ne2k->port + DP_CURR);
501 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA);
502 if (current == boundary)
503 /* No more frames to process */
504 break;
[a35b458]505
[80099c19]506 recv_header_t header;
507 size_t size = sizeof(header);
508 size_t offset = boundary * DP_PAGE;
[a35b458]509
[80099c19]510 /* Get the frame header */
511 pio_write_8(ne2k->port + DP_RBCR0, size & 0xff);
512 pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff);
513 pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff);
514 pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff);
515 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
[a35b458]516
[80099c19]517 pio_read_buf_16(ne2k->data_port, (void *) &header, size);
518
519 size_t length =
520 (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size;
521 uint8_t next = header.next;
[a35b458]522
[3bacee1]523 if ((length < ETH_MIN_PACK_SIZE) ||
524 (length > ETH_MAX_PACK_SIZE_TAGGED)) {
[80099c19]525 next = current;
[3bacee1]526 } else if ((header.next < ne2k->start_page) ||
527 (header.next > ne2k->stop_page)) {
[80099c19]528 next = current;
529 } else if (header.status & RSR_FO) {
530 /*
531 * This is very serious, so we issue a warning and
532 * reset the buffers.
533 */
534 ne2k->overruns++;
535 next = current;
536 } else if ((header.status & RSR_PRX) && (ne2k->up)) {
537 if (frames != NULL) {
538 nic_frame_t *frame =
[3bacee1]539 ne2k_receive_frame(nic_data, boundary, length);
[80099c19]540 if (frame != NULL) {
541 nic_frame_list_append(frames, frame);
542 frames_count++;
543 } else {
544 break;
545 }
546 } else
547 break;
548 }
[a35b458]549
[80099c19]550 /*
551 * Update the boundary pointer
552 * to the value of the page
[1bc35b5]553 * prior to the next frame to
[80099c19]554 * be processed.
555 */
556 if (next == ne2k->start_page)
557 next = ne2k->stop_page - 1;
558 else
559 next--;
560 pio_write_8(ne2k->port + DP_BNRY, next);
561 }
562 nic_received_frame_list(nic_data, frames);
563}
564
565void ne2k_interrupt(nic_t *nic_data, uint8_t isr, uint8_t tsr)
566{
567 ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data);
568
569 if (isr & (ISR_PTX | ISR_TXE)) {
570 if (tsr & TSR_COL) {
571 nic_report_collisions(nic_data,
[3bacee1]572 pio_read_8(ne2k->port + DP_NCR) & 15);
[80099c19]573 }
574
575 if (tsr & TSR_PTX) {
576 // TODO: fix number of sent bytes (but how?)
577 nic_report_send_ok(nic_data, 1, 0);
578 } else if (tsr & TSR_ABT) {
579 nic_report_send_error(nic_data, NIC_SEC_ABORTED, 1);
580 } else if (tsr & TSR_CRS) {
581 nic_report_send_error(nic_data, NIC_SEC_CARRIER_LOST, 1);
582 } else if (tsr & TSR_FU) {
583 ne2k->underruns++;
584 // if (ne2k->underruns < NE2K_ERL) {
585 // }
586 } else if (tsr & TSR_CDH) {
587 nic_report_send_error(nic_data, NIC_SEC_HEARTBEAT, 1);
588 // if (nic_data->stats.send_heartbeat_errors < NE2K_ERL) {
589 // }
590 } else if (tsr & TSR_OWC) {
591 nic_report_send_error(nic_data, NIC_SEC_WINDOW_ERROR, 1);
592 }
593
594 fibril_mutex_lock(&ne2k->sq_mutex);
595 if (ne2k->sq.dirty) {
[1bc35b5]596 /* Prepare the buffer for next frame */
[80099c19]597 ne2k->sq.dirty = false;
598 ne2k->sq.size = 0;
[a35b458]599
[80099c19]600 /* Signal a next frame to be sent */
601 fibril_condvar_broadcast(&ne2k->sq_cv);
602 } else {
603 ne2k->misses++;
604 // if (ne2k->misses < NE2K_ERL) {
605 // }
606 }
607 fibril_mutex_unlock(&ne2k->sq_mutex);
608 }
609
610 if (isr & ISR_CNT) {
611 unsigned int errors;
612 for (errors = pio_read_8(ne2k->port + DP_CNTR0); errors > 0; --errors)
613 nic_report_receive_error(nic_data, NIC_REC_CRC, 1);
614 for (errors = pio_read_8(ne2k->port + DP_CNTR1); errors > 0; --errors)
615 nic_report_receive_error(nic_data, NIC_REC_FRAME_ALIGNMENT, 1);
616 for (errors = pio_read_8(ne2k->port + DP_CNTR2); errors > 0; --errors)
617 nic_report_receive_error(nic_data, NIC_REC_MISSED, 1);
618 }
619 if (isr & ISR_PRX) {
620 ne2k_receive(nic_data);
621 }
622 if (isr & ISR_RST) {
623 /*
624 * The chip is stopped, and all arrived
625 * frames are delivered.
626 */
627 ne2k_reset(ne2k);
628 }
[a35b458]629
[80099c19]630 /* Unmask interrupts to be processed in the next round */
631 pio_write_8(ne2k->port + DP_IMR,
632 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
633}
634
635void ne2k_set_accept_bcast(ne2k_t *ne2k, int accept)
636{
637 if (accept)
638 ne2k->receive_configuration |= RCR_AB;
639 else
640 ne2k->receive_configuration &= ~RCR_AB;
[a35b458]641
[80099c19]642 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
643}
644
645void ne2k_set_accept_mcast(ne2k_t *ne2k, int accept)
646{
647 if (accept)
648 ne2k->receive_configuration |= RCR_AM;
649 else
650 ne2k->receive_configuration &= ~RCR_AM;
[a35b458]651
[80099c19]652 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
653}
654
655void ne2k_set_promisc_phys(ne2k_t *ne2k, int promisc)
656{
657 if (promisc)
658 ne2k->receive_configuration |= RCR_PRO;
659 else
660 ne2k->receive_configuration &= ~RCR_PRO;
[a35b458]661
[80099c19]662 pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration);
663}
664
665void ne2k_set_mcast_hash(ne2k_t *ne2k, uint64_t hash)
666{
667 /* Select Page 1 and stop all transfers */
668 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
[a35b458]669
[80099c19]670 pio_write_8(ne2k->port + DP_MAR0, (uint8_t) hash);
671 pio_write_8(ne2k->port + DP_MAR1, (uint8_t) (hash >> 8));
672 pio_write_8(ne2k->port + DP_MAR2, (uint8_t) (hash >> 16));
673 pio_write_8(ne2k->port + DP_MAR3, (uint8_t) (hash >> 24));
674 pio_write_8(ne2k->port + DP_MAR4, (uint8_t) (hash >> 32));
675 pio_write_8(ne2k->port + DP_MAR5, (uint8_t) (hash >> 40));
676 pio_write_8(ne2k->port + DP_MAR6, (uint8_t) (hash >> 48));
677 pio_write_8(ne2k->port + DP_MAR7, (uint8_t) (hash >> 56));
[a35b458]678
[80099c19]679 /* Select Page 0 and resume transfers */
680 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
681}
682
683/** @}
684 */
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