source: mainline/uspace/drv/nic/e1k/e1k.c@ cfb79747

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cfb79747 was cfb79747, checked in by Jakub Jermar <jakub@…>, 14 years ago

Merge mainline changes.
  • Property mode set to 100644
File size: 55.7 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <byteorder.h>
41#include <sysinfo.h>
42#include <ipc/irc.h>
43#include <ipc/ns.h>
44#include <libarch/ddi.h>
45#include <as.h>
46#include <ddf/log.h>
47#include <ddf/interrupt.h>
48#include <devman.h>
49#include <device/hw_res_parsed.h>
50#include <device/pci.h>
51#include <nic.h>
52#include <nil_remote.h>
53#include <ops/nic.h>
54#include "e1k.h"
55
56#define NAME "e1k"
57
58#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
59
60/* Must be power of 8 */
61#define E1000_RX_FRAME_COUNT 128
62#define E1000_TX_FRAME_COUNT 128
63
64#define E1000_RECEIVE_ADDRESS 16
65
66/** Maximum sending frame size */
67#define E1000_MAX_SEND_FRAME_SIZE 2048
68/** Maximum receiving frame size */
69#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
70
71/** nic_driver_data_t* -> e1000_t* cast */
72#define DRIVER_DATA_NIC(nic) \
73 ((e1000_t *) nic_get_specific(nic))
74
75/** device_t* -> nic_driver_data_t* cast */
76#define NIC_DATA_DEV(dev) \
77 ((nic_t *) ((dev)->driver_data))
78
79/** device_t* -> e1000_t* cast */
80#define DRIVER_DATA_DEV(dev) \
81 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
82
83/** Cast pointer to uint64_t
84 *
85 * @param ptr Pointer to cast
86 *
87 * @return The uint64_t pointer representation.
88 *
89 */
90#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
91
92/** Cast the memaddr part to the void*
93 *
94 * @param memaddr The memaddr value
95 *
96 */
97#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
98
99#define E1000_REG_BASE(e1000) \
100 ((e1000)->reg_base_virt)
101
102#define E1000_REG_ADDR(e1000, reg) \
103 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
104
105#define E1000_REG_READ(e1000, reg) \
106 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
107
108#define E1000_REG_WRITE(e1000, reg, value) \
109 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
110
111/** E1000 device data */
112typedef struct {
113 /** Device configuration */
114 e1000_info_t info;
115
116 /** Physical registers base address */
117 void *reg_base_phys;
118 /** Virtual registers base address */
119 void *reg_base_virt;
120
121 /** Physical tx ring address */
122 void *tx_ring_phys;
123 /** Virtual tx ring address */
124 void *tx_ring_virt;
125
126 /** Ring of TX frames, physical address */
127 void **tx_frame_phys;
128 /** Ring of TX frames, virtual address */
129 void **tx_frame_virt;
130
131 /** Physical rx ring address */
132 void *rx_ring_phys;
133 /** Virtual rx ring address */
134 void *rx_ring_virt;
135
136 /** Ring of RX frames, physical address */
137 void **rx_frame_phys;
138 /** Ring of RX frames, virtual address */
139 void **rx_frame_virt;
140
141 /** VLAN tag */
142 uint16_t vlan_tag;
143
144 /** Add VLAN tag to frame */
145 bool vlan_tag_add;
146
147 /** Used unicast Receive Address count */
148 unsigned int unicast_ra_count;
149
150 /** Used milticast Receive addrress count */
151 unsigned int multicast_ra_count;
152
153 /** The irq assigned */
154 int irq;
155
156 /** Lock for CTRL register */
157 fibril_mutex_t ctrl_lock;
158
159 /** Lock for receiver */
160 fibril_mutex_t rx_lock;
161
162 /** Lock for transmitter */
163 fibril_mutex_t tx_lock;
164
165 /** Lock for EEPROM access */
166 fibril_mutex_t eeprom_lock;
167} e1000_t;
168
169/** Global mutex for work with shared irq structure */
170FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
171
172static int e1000_get_address(e1000_t *, nic_address_t *);
173static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
174static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
175
176static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
177static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
178
179static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
180static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
181static int e1000_get_operation_mode(ddf_fun_t *, int *,
182 nic_channel_mode_t *, nic_role_t *);
183static int e1000_set_operation_mode(ddf_fun_t *, int,
184 nic_channel_mode_t, nic_role_t);
185static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
186static int e1000_autoneg_disable(ddf_fun_t *);
187static int e1000_autoneg_restart(ddf_fun_t *);
188
189static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
190
191/** Network interface options for E1000 card driver */
192static nic_iface_t e1000_nic_iface;
193
194/** Network interface options for E1000 card driver */
195static nic_iface_t e1000_nic_iface = {
196 .set_address = &e1000_set_addr,
197 .get_device_info = &e1000_get_device_info,
198 .get_cable_state = &e1000_get_cable_state,
199 .get_operation_mode = &e1000_get_operation_mode,
200 .set_operation_mode = &e1000_set_operation_mode,
201 .autoneg_enable = &e1000_autoneg_enable,
202 .autoneg_disable = &e1000_autoneg_disable,
203 .autoneg_restart = &e1000_autoneg_restart,
204 .vlan_set_tag = &e1000_vlan_set_tag,
205 .defective_get_mode = &e1000_defective_get_mode,
206 .defective_set_mode = &e1000_defective_set_mode,
207};
208
209/** Basic device operations for E1000 driver */
210static ddf_dev_ops_t e1000_dev_ops;
211
212static int e1000_dev_add(ddf_dev_t *);
213
214/** Basic driver operations for E1000 driver */
215static driver_ops_t e1000_driver_ops = {
216 .dev_add = e1000_dev_add
217};
218
219/** Driver structure for E1000 driver */
220static driver_t e1000_driver = {
221 .name = NAME,
222 .driver_ops = &e1000_driver_ops
223};
224
225/* The default implementation callbacks */
226static int e1000_on_activating(nic_t *);
227static int e1000_on_stopping(nic_t *);
228static void e1000_send_frame(nic_t *, void *, size_t);
229
230/** PIO ranges used in the IRQ code. */
231irq_pio_range_t e1000_irq_pio_ranges[] = {
232 {
233 .base = 0,
234 .size = PAGE_SIZE, /* XXX */
235 }
236};
237
238/** Commands to deal with interrupt
239 *
240 */
241irq_cmd_t e1000_irq_commands[] = {
242 {
243 /* Get the interrupt status */
244 .cmd = CMD_PIO_READ_32,
245 .addr = NULL,
246 .dstarg = 2
247 },
248 {
249 .cmd = CMD_PREDICATE,
250 .value = 2,
251 .srcarg = 2
252 },
253 {
254 /* Disable interrupts until interrupt routine is finished */
255 .cmd = CMD_PIO_WRITE_32,
256 .addr = NULL,
257 .value = 0xffffffff
258 },
259 {
260 .cmd = CMD_ACCEPT
261 }
262};
263
264/** Interrupt code definition */
265irq_code_t e1000_irq_code = {
266 .rangecount = sizeof(e1000_irq_pio_ranges) /
267 sizeof(irq_pio_range_t),
268 .ranges = e1000_irq_pio_ranges,
269 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
270 .cmds = e1000_irq_commands
271};
272
273/** Get the device information
274 *
275 * @param dev NIC device
276 * @param info Information to fill
277 *
278 * @return EOK
279 *
280 */
281static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
282{
283 assert(dev);
284 assert(info);
285
286 bzero(info, sizeof(nic_device_info_t));
287
288 info->vendor_id = 0x8086;
289 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
290 "Intel Corporation");
291 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
292 "Intel Pro");
293
294 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
295 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
296 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
297
298 return EOK;
299}
300
301/** Check the cable state
302 *
303 * @param[in] dev device
304 * @param[out] state state to fill
305 *
306 * @return EOK
307 *
308 */
309static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
310{
311 assert(dev);
312 assert(DRIVER_DATA_DEV(dev));
313 assert(state);
314
315 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
316 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
317 *state = NIC_CS_PLUGGED;
318 else
319 *state = NIC_CS_UNPLUGGED;
320
321 return EOK;
322}
323
324static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
325{
326 return useconds * 4;
327}
328
329/** Get operation mode of the device
330 *
331 */
332static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
333 nic_channel_mode_t *duplex, nic_role_t *role)
334{
335 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
336 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
337
338 if (status & STATUS_FD)
339 *duplex = NIC_CM_FULL_DUPLEX;
340 else
341 *duplex = NIC_CM_HALF_DUPLEX;
342
343 uint32_t speed_bits =
344 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
345
346 if (speed_bits == STATUS_SPEED_10)
347 *speed = 10;
348 else if (speed_bits == STATUS_SPEED_100)
349 *speed = 100;
350 else if ((speed_bits == STATUS_SPEED_1000A) ||
351 (speed_bits == STATUS_SPEED_1000B))
352 *speed = 1000;
353
354 *role = NIC_ROLE_UNKNOWN;
355 return EOK;
356}
357
358static void e1000_link_restart(e1000_t *e1000)
359{
360 fibril_mutex_lock(&e1000->ctrl_lock);
361
362 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
363
364 if (ctrl & CTRL_SLU) {
365 ctrl &= ~(CTRL_SLU);
366 fibril_mutex_unlock(&e1000->ctrl_lock);
367 usleep(10);
368 fibril_mutex_lock(&e1000->ctrl_lock);
369 ctrl |= CTRL_SLU;
370 }
371
372 fibril_mutex_unlock(&e1000->ctrl_lock);
373
374 e1000_link_restart(e1000);
375}
376
377/** Set operation mode of the device
378 *
379 */
380static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
381 nic_channel_mode_t duplex, nic_role_t role)
382{
383 if ((speed != 10) && (speed != 100) && (speed != 1000))
384 return EINVAL;
385
386 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
387 return EINVAL;
388
389 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
390
391 fibril_mutex_lock(&e1000->ctrl_lock);
392 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
393
394 ctrl |= CTRL_FRCSPD;
395 ctrl |= CTRL_FRCDPLX;
396 ctrl &= ~(CTRL_ASDE);
397
398 if (duplex == NIC_CM_FULL_DUPLEX)
399 ctrl |= CTRL_FD;
400 else
401 ctrl &= ~(CTRL_FD);
402
403 ctrl &= ~(CTRL_SPEED_MASK);
404 if (speed == 1000)
405 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
406 else if (speed == 100)
407 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
408 else
409 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
410
411 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
412
413 fibril_mutex_unlock(&e1000->ctrl_lock);
414
415 e1000_link_restart(e1000);
416
417 return EOK;
418}
419
420/** Enable auto-negotiation
421 *
422 * @param dev Device to update
423 * @param advertisement Ignored on E1000
424 *
425 * @return EOK if advertisement mode set successfully
426 *
427 */
428static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
429{
430 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
431
432 fibril_mutex_lock(&e1000->ctrl_lock);
433
434 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
435
436 ctrl &= ~(CTRL_FRCSPD);
437 ctrl &= ~(CTRL_FRCDPLX);
438 ctrl |= CTRL_ASDE;
439
440 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
441
442 fibril_mutex_unlock(&e1000->ctrl_lock);
443
444 e1000_link_restart(e1000);
445
446 return EOK;
447}
448
449/** Disable auto-negotiation
450 *
451 * @param dev Device to update
452 *
453 * @return EOK
454 *
455 */
456static int e1000_autoneg_disable(ddf_fun_t *dev)
457{
458 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
459
460 fibril_mutex_lock(&e1000->ctrl_lock);
461
462 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
463
464 ctrl |= CTRL_FRCSPD;
465 ctrl |= CTRL_FRCDPLX;
466 ctrl &= ~(CTRL_ASDE);
467
468 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
469
470 fibril_mutex_unlock(&e1000->ctrl_lock);
471
472 e1000_link_restart(e1000);
473
474 return EOK;
475}
476
477/** Restart auto-negotiation
478 *
479 * @param dev Device to update
480 *
481 * @return EOK if advertisement mode set successfully
482 *
483 */
484static int e1000_autoneg_restart(ddf_fun_t *dev)
485{
486 return e1000_autoneg_enable(dev, 0);
487}
488
489/** Get state of acceptance of weird frames
490 *
491 * @param device Device to check
492 * @param[out] mode Current mode
493 *
494 */
495static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
496{
497 e1000_t *e1000 = DRIVER_DATA_DEV(device);
498
499 *mode = 0;
500 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
501 if (rctl & RCTL_SBP)
502 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
503
504 return EOK;
505};
506
507/** Set acceptance of weird frames
508 *
509 * @param device Device to update
510 * @param mode Mode to set
511 *
512 * @return ENOTSUP if the mode is not supported
513 * @return EOK of mode was set
514 *
515 */
516static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
517{
518 e1000_t *e1000 = DRIVER_DATA_DEV(device);
519 int rc = EOK;
520
521 fibril_mutex_lock(&e1000->rx_lock);
522
523 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
524 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
525 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
526
527 if (short_mode && bad_mode)
528 rctl |= RCTL_SBP;
529 else if ((!short_mode) && (!bad_mode))
530 rctl &= ~RCTL_SBP;
531 else
532 rc = ENOTSUP;
533
534 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
535
536 fibril_mutex_unlock(&e1000->rx_lock);
537 return rc;
538};
539
540/** Write receive address to RA registr
541 *
542 * @param e1000 E1000 data structure
543 * @param position RA register position
544 * @param address Ethernet address
545 * @param set_av_bit Set the Addtess Valid bit
546 *
547 */
548static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
549 const nic_address_t * address, bool set_av_bit)
550{
551 uint8_t *mac0 = (uint8_t *) address->address;
552 uint8_t *mac1 = (uint8_t *) address->address + 1;
553 uint8_t *mac2 = (uint8_t *) address->address + 2;
554 uint8_t *mac3 = (uint8_t *) address->address + 3;
555 uint8_t *mac4 = (uint8_t *) address->address + 4;
556 uint8_t *mac5 = (uint8_t *) address->address + 5;
557
558 uint32_t rah;
559 uint32_t ral;
560
561 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
562 rah = ((*mac5) << 8) | ((*mac4));
563
564 if (set_av_bit)
565 rah |= RAH_AV;
566 else
567 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
568
569 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
570 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
571}
572
573/** Disable receive address in RA registr
574 *
575 * Clear Address Valid bit
576 *
577 * @param e1000 E1000 data structure
578 * @param position RA register position
579 *
580 */
581static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
582{
583 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
584 rah = rah & ~RAH_AV;
585 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
586}
587
588/** Clear all unicast addresses from RA registers
589 *
590 * @param e1000 E1000 data structure
591 *
592 */
593static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
594{
595 for (unsigned int ra_num = 1;
596 ra_num <= e1000->unicast_ra_count;
597 ra_num++)
598 e1000_disable_receive_address(e1000, ra_num);
599
600 e1000->unicast_ra_count = 0;
601}
602
603/** Clear all multicast addresses from RA registers
604 *
605 * @param e1000 E1000 data structure
606 *
607 */
608static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
609{
610 unsigned int first_multicast_ra_num =
611 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
612
613 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
614 ra_num >= first_multicast_ra_num;
615 ra_num--)
616 e1000_disable_receive_address(e1000, ra_num);
617
618 e1000->multicast_ra_count = 0;
619}
620
621/** Return receive address filter positions count usable for unicast
622 *
623 * @param e1000 E1000 data structure
624 *
625 * @return receive address filter positions count usable for unicast
626 *
627 */
628static unsigned int get_free_unicast_address_count(e1000_t *e1000)
629{
630 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
631}
632
633/** Return receive address filter positions count usable for multicast
634 *
635 * @param e1000 E1000 data structure
636 *
637 * @return receive address filter positions count usable for multicast
638 *
639 */
640static unsigned int get_free_multicast_address_count(e1000_t *e1000)
641{
642 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
643}
644
645/** Write unicast receive addresses to receive address filter registers
646 *
647 * @param e1000 E1000 data structure
648 * @param addr Pointer to address array
649 * @param addr_cnt Address array count
650 *
651 */
652static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
653 const nic_address_t *addr, size_t addr_cnt)
654{
655 assert(addr_cnt <= get_free_unicast_address_count(e1000));
656
657 nic_address_t *addr_iterator = (nic_address_t *) addr;
658
659 /* ra_num = 0 is primary address */
660 for (unsigned int ra_num = 1;
661 ra_num <= addr_cnt;
662 ra_num++) {
663 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
664 addr_iterator++;
665 }
666}
667
668/** Write multicast receive addresses to receive address filter registers
669 *
670 * @param e1000 E1000 data structure
671 * @param addr Pointer to address array
672 * @param addr_cnt Address array count
673 *
674 */
675static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
676 const nic_address_t *addr, size_t addr_cnt)
677{
678 assert(addr_cnt <= get_free_multicast_address_count(e1000));
679
680 nic_address_t *addr_iterator = (nic_address_t *) addr;
681
682 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
683 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
684 ra_num >= first_multicast_ra_num;
685 ra_num--) {
686 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
687 addr_iterator++;
688 }
689}
690
691/** Disable receiving frames for default address
692 *
693 * @param e1000 E1000 data structure
694 *
695 */
696static void disable_ra0_address_filter(e1000_t *e1000)
697{
698 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
699 rah0 = rah0 & ~RAH_AV;
700 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
701}
702
703/** Enable receiving frames for default address
704 *
705 * @param e1000 E1000 data structure
706 *
707 */
708static void enable_ra0_address_filter(e1000_t *e1000)
709{
710 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
711 rah0 = rah0 | RAH_AV;
712 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
713}
714
715/** Disable unicast promiscuous mode
716 *
717 * @param e1000 E1000 data structure
718 *
719 */
720static void e1000_disable_unicast_promisc(e1000_t *e1000)
721{
722 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
723 rctl = rctl & ~RCTL_UPE;
724 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
725}
726
727/** Enable unicast promiscuous mode
728 *
729 * @param e1000 E1000 data structure
730 *
731 */
732static void e1000_enable_unicast_promisc(e1000_t *e1000)
733{
734 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
735 rctl = rctl | RCTL_UPE;
736 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
737}
738
739/** Disable multicast promiscuous mode
740 *
741 * @param e1000 E1000 data structure
742 *
743 */
744static void e1000_disable_multicast_promisc(e1000_t *e1000)
745{
746 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
747 rctl = rctl & ~RCTL_MPE;
748 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
749}
750
751/** Enable multicast promiscuous mode
752 *
753 * @param e1000 E1000 data structure
754 *
755 */
756static void e1000_enable_multicast_promisc(e1000_t *e1000)
757{
758 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
759 rctl = rctl | RCTL_MPE;
760 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
761}
762
763/** Enable accepting of broadcast frames
764 *
765 * @param e1000 E1000 data structure
766 *
767 */
768static void e1000_enable_broadcast_accept(e1000_t *e1000)
769{
770 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
771 rctl = rctl | RCTL_BAM;
772 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
773}
774
775/** Disable accepting of broadcast frames
776 *
777 * @param e1000 E1000 data structure
778 *
779 */
780static void e1000_disable_broadcast_accept(e1000_t *e1000)
781{
782 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
783 rctl = rctl & ~RCTL_BAM;
784 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
785}
786
787/** Enable VLAN filtering according to VFTA registers
788 *
789 * @param e1000 E1000 data structure
790 *
791 */
792static void e1000_enable_vlan_filter(e1000_t *e1000)
793{
794 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
795 rctl = rctl | RCTL_VFE;
796 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
797}
798
799/** Disable VLAN filtering
800 *
801 * @param e1000 E1000 data structure
802 *
803 */
804static void e1000_disable_vlan_filter(e1000_t *e1000)
805{
806 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
807 rctl = rctl & ~RCTL_VFE;
808 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
809}
810
811/** Set multicast frames acceptance mode
812 *
813 * @param nic NIC device to update
814 * @param mode Mode to set
815 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
816 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
817 *
818 * @return EOK
819 *
820 */
821static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
822 const nic_address_t *addr, size_t addr_cnt)
823{
824 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
825 int rc = EOK;
826
827 fibril_mutex_lock(&e1000->rx_lock);
828
829 switch (mode) {
830 case NIC_MULTICAST_BLOCKED:
831 e1000_clear_multicast_receive_addresses(e1000);
832 e1000_disable_multicast_promisc(e1000);
833 nic_report_hw_filtering(nic, -1, 1, -1);
834 break;
835 case NIC_MULTICAST_LIST:
836 e1000_clear_multicast_receive_addresses(e1000);
837 if (addr_cnt > get_free_multicast_address_count(e1000)) {
838 /*
839 * Future work: fill MTA table
840 * Not strictly neccessary, it only saves some compares
841 * in the NIC library.
842 */
843 e1000_enable_multicast_promisc(e1000);
844 nic_report_hw_filtering(nic, -1, 0, -1);
845 } else {
846 e1000_disable_multicast_promisc(e1000);
847 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
848 nic_report_hw_filtering(nic, -1, 1, -1);
849 }
850 break;
851 case NIC_MULTICAST_PROMISC:
852 e1000_enable_multicast_promisc(e1000);
853 e1000_clear_multicast_receive_addresses(e1000);
854 nic_report_hw_filtering(nic, -1, 1, -1);
855 break;
856 default:
857 rc = ENOTSUP;
858 break;
859 }
860
861 fibril_mutex_unlock(&e1000->rx_lock);
862 return rc;
863}
864
865/** Set unicast frames acceptance mode
866 *
867 * @param nic NIC device to update
868 * @param mode Mode to set
869 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
870 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
871 *
872 * @return EOK
873 *
874 */
875static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
876 const nic_address_t *addr, size_t addr_cnt)
877{
878 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
879 int rc = EOK;
880
881 fibril_mutex_lock(&e1000->rx_lock);
882
883 switch (mode) {
884 case NIC_UNICAST_BLOCKED:
885 disable_ra0_address_filter(e1000);
886 e1000_clear_unicast_receive_addresses(e1000);
887 e1000_disable_unicast_promisc(e1000);
888 nic_report_hw_filtering(nic, 1, -1, -1);
889 break;
890 case NIC_UNICAST_DEFAULT:
891 enable_ra0_address_filter(e1000);
892 e1000_clear_unicast_receive_addresses(e1000);
893 e1000_disable_unicast_promisc(e1000);
894 nic_report_hw_filtering(nic, 1, -1, -1);
895 break;
896 case NIC_UNICAST_LIST:
897 enable_ra0_address_filter(e1000);
898 e1000_clear_unicast_receive_addresses(e1000);
899 if (addr_cnt > get_free_unicast_address_count(e1000)) {
900 e1000_enable_unicast_promisc(e1000);
901 nic_report_hw_filtering(nic, 0, -1, -1);
902 } else {
903 e1000_disable_unicast_promisc(e1000);
904 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
905 nic_report_hw_filtering(nic, 1, -1, -1);
906 }
907 break;
908 case NIC_UNICAST_PROMISC:
909 e1000_enable_unicast_promisc(e1000);
910 enable_ra0_address_filter(e1000);
911 e1000_clear_unicast_receive_addresses(e1000);
912 nic_report_hw_filtering(nic, 1, -1, -1);
913 break;
914 default:
915 rc = ENOTSUP;
916 break;
917 }
918
919 fibril_mutex_unlock(&e1000->rx_lock);
920 return rc;
921}
922
923/** Set broadcast frames acceptance mode
924 *
925 * @param nic NIC device to update
926 * @param mode Mode to set
927 *
928 * @return EOK
929 *
930 */
931static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
932{
933 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
934 int rc = EOK;
935
936 fibril_mutex_lock(&e1000->rx_lock);
937
938 switch (mode) {
939 case NIC_BROADCAST_BLOCKED:
940 e1000_disable_broadcast_accept(e1000);
941 break;
942 case NIC_BROADCAST_ACCEPTED:
943 e1000_enable_broadcast_accept(e1000);
944 break;
945 default:
946 rc = ENOTSUP;
947 break;
948 }
949
950 fibril_mutex_unlock(&e1000->rx_lock);
951 return rc;
952}
953
954/** Check if receiving is enabled
955 *
956 * @param e1000 E1000 data structure
957 *
958 * @return true if receiving is enabled
959 *
960 */
961static bool e1000_is_rx_enabled(e1000_t *e1000)
962{
963 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
964 return true;
965
966 return false;
967}
968
969/** Enable receiving
970 *
971 * @param e1000 E1000 data structure
972 *
973 */
974static void e1000_enable_rx(e1000_t *e1000)
975{
976 /* Set Receive Enable Bit */
977 E1000_REG_WRITE(e1000, E1000_RCTL,
978 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
979}
980
981/** Disable receiving
982 *
983 * @param e1000 E1000 data structure
984 *
985 */
986static void e1000_disable_rx(e1000_t *e1000)
987{
988 /* Clear Receive Enable Bit */
989 E1000_REG_WRITE(e1000, E1000_RCTL,
990 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
991}
992
993/** Set VLAN mask
994 *
995 * @param nic NIC device to update
996 * @param vlan_mask VLAN mask
997 *
998 */
999static void e1000_on_vlan_mask_change(nic_t *nic,
1000 const nic_vlan_mask_t *vlan_mask)
1001{
1002 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1003
1004 fibril_mutex_lock(&e1000->rx_lock);
1005
1006 if (vlan_mask) {
1007 /*
1008 * Disable receiving, so that frame matching
1009 * partially written VLAN is not received.
1010 */
1011 bool rx_enabled = e1000_is_rx_enabled(e1000);
1012 if (rx_enabled)
1013 e1000_disable_rx(e1000);
1014
1015 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1016 uint32_t bitmap_part =
1017 ((uint32_t) vlan_mask->bitmap[i]) |
1018 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1019 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1020 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1021 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1022 }
1023
1024 e1000_enable_vlan_filter(e1000);
1025 if (rx_enabled)
1026 e1000_enable_rx(e1000);
1027 } else
1028 e1000_disable_vlan_filter(e1000);
1029
1030 fibril_mutex_unlock(&e1000->rx_lock);
1031}
1032
1033/** Set VLAN mask
1034 *
1035 * @param device E1000 device
1036 * @param tag VLAN tag
1037 *
1038 * @return EOK
1039 * @return ENOTSUP
1040 *
1041 */
1042static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
1043 bool strip)
1044{
1045 /* VLAN CFI bit cannot be set */
1046 if (tag & VLANTAG_CFI)
1047 return ENOTSUP;
1048
1049 /*
1050 * CTRL.VME is neccessary for both strip and add
1051 * but CTRL.VME means stripping tags on receive.
1052 */
1053 if (!strip && add)
1054 return ENOTSUP;
1055
1056 e1000_t *e1000 = DRIVER_DATA_DEV(device);
1057
1058 e1000->vlan_tag = tag;
1059 e1000->vlan_tag_add = add;
1060
1061 fibril_mutex_lock(&e1000->ctrl_lock);
1062
1063 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1064 if (strip)
1065 ctrl |= CTRL_VME;
1066 else
1067 ctrl &= ~CTRL_VME;
1068
1069 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1070
1071 fibril_mutex_unlock(&e1000->ctrl_lock);
1072 return EOK;
1073}
1074
1075/** Fill receive descriptor with new empty buffer
1076 *
1077 * Store frame in e1000->rx_frame_phys
1078 *
1079 * @param nic NIC data stricture
1080 * @param offset Receive descriptor offset
1081 *
1082 */
1083static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1084{
1085 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1086
1087 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1088 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1089
1090 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1091 rx_descriptor->length = 0;
1092 rx_descriptor->checksum = 0;
1093 rx_descriptor->status = 0;
1094 rx_descriptor->errors = 0;
1095 rx_descriptor->special = 0;
1096}
1097
1098/** Clear receive descriptor
1099 *
1100 * @param e1000 E1000 data
1101 * @param offset Receive descriptor offset
1102 *
1103 */
1104static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1105{
1106 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1107 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1108
1109 rx_descriptor->length = 0;
1110 rx_descriptor->checksum = 0;
1111 rx_descriptor->status = 0;
1112 rx_descriptor->errors = 0;
1113 rx_descriptor->special = 0;
1114}
1115
1116/** Clear receive descriptor
1117 *
1118 * @param nic NIC data
1119 * @param offset Receive descriptor offset
1120 *
1121 */
1122static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1123{
1124 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1125
1126 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1127 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1128
1129 tx_descriptor->phys_addr = 0;
1130 tx_descriptor->length = 0;
1131 tx_descriptor->checksum_offset = 0;
1132 tx_descriptor->command = 0;
1133 tx_descriptor->status = 0;
1134 tx_descriptor->checksum_start_field = 0;
1135 tx_descriptor->special = 0;
1136}
1137
1138/** Increment tail pointer for receive or transmit ring
1139 *
1140 * @param tail Old Tail
1141 * @param descriptors_count Ring length
1142 *
1143 * @return New tail
1144 *
1145 */
1146static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1147{
1148 if (tail + 1 == descriptors_count)
1149 return 0;
1150 else
1151 return tail + 1;
1152}
1153
1154/** Receive frames
1155 *
1156 * @param nic NIC data
1157 *
1158 */
1159static void e1000_receive_frames(nic_t *nic)
1160{
1161 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1162
1163 fibril_mutex_lock(&e1000->rx_lock);
1164
1165 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1166 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1167
1168 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1169 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1170
1171 while (rx_descriptor->status & 0x01) {
1172 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1173
1174 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1175 if (frame != NULL) {
1176 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1177 nic_received_frame(nic, frame);
1178 } else {
1179 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1180 }
1181
1182 e1000_fill_new_rx_descriptor(nic, next_tail);
1183
1184 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1185 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1186
1187 rx_descriptor = (e1000_rx_descriptor_t *)
1188 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1189 }
1190
1191 fibril_mutex_unlock(&e1000->rx_lock);
1192}
1193
1194/** Enable E1000 interupts
1195 *
1196 * @param e1000 E1000 data structure
1197 *
1198 */
1199static void e1000_enable_interrupts(e1000_t *e1000)
1200{
1201 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1202}
1203
1204/** Disable E1000 interupts
1205 *
1206 * @param e1000 E1000 data structure
1207 *
1208 */
1209static void e1000_disable_interrupts(e1000_t *e1000)
1210{
1211 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1212}
1213
1214/** Interrupt handler implementation
1215 *
1216 * This function is called from e1000_interrupt_handler()
1217 * and e1000_poll()
1218 *
1219 * @param nic NIC data
1220 * @param icr ICR register value
1221 *
1222 */
1223static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1224{
1225 if (icr & ICR_RXT0)
1226 e1000_receive_frames(nic);
1227}
1228
1229/** Handle device interrupt
1230 *
1231 * @param dev E1000 device
1232 * @param iid IPC call id
1233 * @param icall IPC call structure
1234 *
1235 */
1236static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1237 ipc_call_t *icall)
1238{
1239 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1240 nic_t *nic = NIC_DATA_DEV(dev);
1241 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1242
1243 e1000_interrupt_handler_impl(nic, icr);
1244 e1000_enable_interrupts(e1000);
1245}
1246
1247/** Register interrupt handler for the card in the system
1248 *
1249 * Note: The global irq_reg_mutex is locked because of work with global
1250 * structure.
1251 *
1252 * @param nic Driver data
1253 *
1254 * @return EOK if the handler was registered
1255 * @return Negative error code otherwise
1256 *
1257 */
1258inline static int e1000_register_int_handler(nic_t *nic)
1259{
1260 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1261
1262 /* Lock the mutex in whole driver while working with global structure */
1263 fibril_mutex_lock(&irq_reg_mutex);
1264
1265 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1266 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1267 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1268
1269 int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
1270 e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
1271
1272 fibril_mutex_unlock(&irq_reg_mutex);
1273 return rc;
1274}
1275
1276/** Force receiving all frames in the receive buffer
1277 *
1278 * @param nic NIC data
1279 *
1280 */
1281static void e1000_poll(nic_t *nic)
1282{
1283 assert(nic);
1284
1285 e1000_t *e1000 = nic_get_specific(nic);
1286 assert(e1000);
1287
1288 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1289 e1000_interrupt_handler_impl(nic, icr);
1290}
1291
1292/** Calculates ITR register interrupt from timeval structure
1293 *
1294 * @param period Period
1295 *
1296 */
1297static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1298{
1299 // TODO: use also tv_sec
1300 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1301}
1302
1303/** Set polling mode
1304 *
1305 * @param device Device to set
1306 * @param mode Mode to set
1307 * @param period Period for NIC_POLL_PERIODIC
1308 *
1309 * @return EOK if succeed
1310 * @return ENOTSUP if the mode is not supported
1311 *
1312 */
1313static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1314 const struct timeval *period)
1315{
1316 assert(nic);
1317
1318 e1000_t *e1000 = nic_get_specific(nic);
1319 assert(e1000);
1320
1321 switch (mode) {
1322 case NIC_POLL_IMMEDIATE:
1323 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1324 e1000_enable_interrupts(e1000);
1325 break;
1326 case NIC_POLL_ON_DEMAND:
1327 e1000_disable_interrupts(e1000);
1328 break;
1329 case NIC_POLL_PERIODIC:
1330 assert(period);
1331 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1332 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1333 e1000_enable_interrupts(e1000);
1334 break;
1335 default:
1336 return ENOTSUP;
1337 }
1338
1339 return EOK;
1340}
1341
1342/** Initialize receive registers
1343 *
1344 * @param e1000 E1000 data structure
1345 *
1346 */
1347static void e1000_initialize_rx_registers(e1000_t *e1000)
1348{
1349 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1350 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1351
1352 /* It is not posible to let HW use all descriptors */
1353 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1354
1355 /* Set Broadcast Enable Bit */
1356 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1357}
1358
1359/** Initialize receive structure
1360 *
1361 * @param nic NIC data
1362 *
1363 * @return EOK if succeed
1364 * @return Negative error code otherwise
1365 *
1366 */
1367static int e1000_initialize_rx_structure(nic_t *nic)
1368{
1369 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1370 fibril_mutex_lock(&e1000->rx_lock);
1371
1372 int rc = dmamem_map_anonymous(
1373 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1374 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,
1375 &e1000->rx_ring_virt);
1376 if (rc != EOK)
1377 return rc;
1378
1379 E1000_REG_WRITE(e1000, E1000_RDBAH,
1380 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1381 E1000_REG_WRITE(e1000, E1000_RDBAL,
1382 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1383
1384 e1000->rx_frame_phys =
1385 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1386 e1000->rx_frame_virt =
1387 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1388 if (e1000->rx_frame_phys == NULL || e1000->rx_frame_virt == NULL) {
1389 rc = ENOMEM;
1390 goto error;
1391 }
1392
1393 size_t i;
1394 void *frame_virt;
1395 void *frame_phys;
1396
1397 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1398 rc = dmamem_map_anonymous(
1399 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1400 0, &frame_phys, &frame_virt);
1401 if (rc != EOK)
1402 goto error;
1403
1404 e1000->rx_frame_virt[i] = frame_virt;
1405 e1000->rx_frame_phys[i] = frame_phys;
1406 }
1407
1408 /* Write descriptor */
1409 for (i = 0; i < E1000_RX_FRAME_COUNT; i++)
1410 e1000_fill_new_rx_descriptor(nic, i);
1411
1412 e1000_initialize_rx_registers(e1000);
1413
1414 fibril_mutex_unlock(&e1000->rx_lock);
1415 return EOK;
1416
1417error:
1418 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1419 if (e1000->rx_frame_virt[i] != NULL) {
1420 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1421 e1000->rx_frame_virt[i] = NULL;
1422 e1000->rx_frame_phys[i] = NULL;
1423 }
1424 }
1425
1426 if (e1000->rx_frame_phys != NULL) {
1427 free(e1000->rx_frame_phys);
1428 e1000->rx_frame_phys = NULL;
1429 }
1430
1431 if (e1000->rx_frame_virt != NULL) {
1432 free(e1000->rx_frame_virt);
1433 e1000->rx_frame_phys = NULL;
1434 }
1435
1436 return rc;
1437}
1438
1439/** Uninitialize receive structure
1440 *
1441 * @param nic NIC data
1442 *
1443 */
1444static void e1000_uninitialize_rx_structure(nic_t *nic)
1445{
1446 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1447
1448 /* Write descriptor */
1449 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1450 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1451 e1000->rx_frame_virt[offset] = NULL;
1452 e1000->rx_frame_phys[offset] = NULL;
1453 }
1454
1455 free(e1000->rx_frame_virt);
1456 free(e1000->rx_frame_phys);
1457 e1000->rx_frame_virt = NULL;
1458 e1000->rx_frame_phys = NULL;
1459 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1460}
1461
1462/** Clear receive descriptor ring
1463 *
1464 * @param e1000 E1000 data
1465 *
1466 */
1467static void e1000_clear_rx_ring(e1000_t *e1000)
1468{
1469 /* Write descriptor */
1470 for (unsigned int offset = 0;
1471 offset < E1000_RX_FRAME_COUNT;
1472 offset++)
1473 e1000_clear_rx_descriptor(e1000, offset);
1474}
1475
1476/** Initialize filters
1477 *
1478 * @param e1000 E1000 data
1479 *
1480 */
1481static void e1000_initialize_filters(e1000_t *e1000)
1482{
1483 /* Initialize address filter */
1484 e1000->unicast_ra_count = 0;
1485 e1000->multicast_ra_count = 0;
1486 e1000_clear_unicast_receive_addresses(e1000);
1487}
1488
1489/** Initialize VLAN
1490 *
1491 * @param e1000 E1000 data
1492 *
1493 */
1494static void e1000_initialize_vlan(e1000_t *e1000)
1495{
1496 e1000->vlan_tag_add = false;
1497}
1498
1499/** Fill MAC address from EEPROM to RA[0] register
1500 *
1501 * @param e1000 E1000 data
1502 *
1503 */
1504static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1505{
1506 /* MAC address from eeprom to RA[0] */
1507 nic_address_t address;
1508 e1000_eeprom_get_address(e1000, &address);
1509 e1000_write_receive_address(e1000, 0, &address, true);
1510}
1511
1512/** Initialize other registers
1513 *
1514 * @param dev E1000 data.
1515 *
1516 * @return EOK if succeed
1517 * @return Negative error code otherwise
1518 *
1519 */
1520static void e1000_initialize_registers(e1000_t *e1000)
1521{
1522 E1000_REG_WRITE(e1000, E1000_ITR,
1523 e1000_calculate_itr_interval_from_usecs(
1524 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1525 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1526 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1527 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1528 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1529 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1530 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1531}
1532
1533/** Initialize transmit registers
1534 *
1535 * @param e1000 E1000 data.
1536 *
1537 */
1538static void e1000_initialize_tx_registers(e1000_t *e1000)
1539{
1540 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1541 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1542 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1543
1544 E1000_REG_WRITE(e1000, E1000_TIPG,
1545 10 << TIPG_IPGT_SHIFT |
1546 8 << TIPG_IPGR1_SHIFT |
1547 6 << TIPG_IPGR2_SHIFT);
1548
1549 E1000_REG_WRITE(e1000, E1000_TCTL,
1550 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1551 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1552 TCTL_PSP /* Pad Short Packets */);
1553}
1554
1555/** Initialize transmit structure
1556 *
1557 * @param e1000 E1000 data.
1558 *
1559 */
1560static int e1000_initialize_tx_structure(e1000_t *e1000)
1561{
1562 size_t i;
1563
1564 fibril_mutex_lock(&e1000->tx_lock);
1565
1566 e1000->tx_ring_phys = NULL;
1567 e1000->tx_ring_virt = NULL;
1568 e1000->tx_frame_phys = NULL;
1569 e1000->tx_frame_virt = NULL;
1570
1571 int rc = dmamem_map_anonymous(
1572 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1573 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,
1574 &e1000->tx_ring_virt);
1575 if (rc != EOK)
1576 goto error;
1577
1578 bzero(e1000->tx_ring_virt,
1579 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1580
1581 e1000->tx_frame_phys = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1582 e1000->tx_frame_virt = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1583
1584 if (e1000->tx_frame_phys == NULL || e1000->tx_frame_virt == NULL) {
1585 rc = ENOMEM;
1586 goto error;
1587 }
1588
1589 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1590 rc = dmamem_map_anonymous(
1591 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1592 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1593 if (rc != EOK)
1594 goto error;
1595 }
1596
1597 E1000_REG_WRITE(e1000, E1000_TDBAH,
1598 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1599 E1000_REG_WRITE(e1000, E1000_TDBAL,
1600 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1601
1602 e1000_initialize_tx_registers(e1000);
1603
1604 fibril_mutex_unlock(&e1000->tx_lock);
1605 return EOK;
1606
1607error:
1608 if (e1000->tx_ring_virt != NULL) {
1609 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1610 e1000->tx_ring_virt = NULL;
1611 }
1612
1613 if (e1000->tx_frame_phys != NULL && e1000->tx_frame_virt != NULL) {
1614 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1615 if (e1000->tx_frame_virt[i] != NULL) {
1616 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1617 e1000->tx_frame_virt[i] = NULL;
1618 e1000->tx_frame_phys[i] = NULL;
1619 }
1620 }
1621 }
1622
1623 if (e1000->tx_frame_phys != NULL) {
1624 free(e1000->tx_frame_phys);
1625 e1000->tx_frame_phys = NULL;
1626 }
1627
1628 if (e1000->tx_frame_virt != NULL) {
1629 free(e1000->tx_frame_virt);
1630 e1000->tx_frame_phys = NULL;
1631 }
1632
1633 return rc;
1634}
1635
1636/** Uninitialize transmit structure
1637 *
1638 * @param nic NIC data
1639 *
1640 */
1641static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1642{
1643 size_t i;
1644
1645 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1646 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1647 e1000->tx_frame_virt[i] = NULL;
1648 e1000->tx_frame_phys[i] = NULL;
1649 }
1650
1651 if (e1000->tx_frame_phys != NULL) {
1652 free(e1000->tx_frame_phys);
1653 e1000->tx_frame_phys = NULL;
1654 }
1655
1656 if (e1000->tx_frame_virt != NULL) {
1657 free(e1000->tx_frame_virt);
1658 e1000->tx_frame_phys = NULL;
1659 }
1660
1661 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1662}
1663
1664/** Clear transmit descriptor ring
1665 *
1666 * @param nic NIC data
1667 *
1668 */
1669static void e1000_clear_tx_ring(nic_t *nic)
1670{
1671 /* Write descriptor */
1672 for (unsigned int offset = 0;
1673 offset < E1000_TX_FRAME_COUNT;
1674 offset++)
1675 e1000_clear_tx_descriptor(nic, offset);
1676}
1677
1678/** Enable transmit
1679 *
1680 * @param e1000 E1000 data
1681 *
1682 */
1683static void e1000_enable_tx(e1000_t *e1000)
1684{
1685 /* Set Transmit Enable Bit */
1686 E1000_REG_WRITE(e1000, E1000_TCTL,
1687 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1688}
1689
1690/** Disable transmit
1691 *
1692 * @param e1000 E1000 data
1693 *
1694 */
1695static void e1000_disable_tx(e1000_t *e1000)
1696{
1697 /* Clear Transmit Enable Bit */
1698 E1000_REG_WRITE(e1000, E1000_TCTL,
1699 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1700}
1701
1702/** Reset E1000 device
1703 *
1704 * @param e1000 The E1000 data
1705 *
1706 */
1707static int e1000_reset(nic_t *nic)
1708{
1709 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1710
1711 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1712
1713 /* Wait for the reset */
1714 usleep(20);
1715
1716 /* check if RST_BIT cleared */
1717 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1718 return EINVAL;
1719
1720 e1000_initialize_registers(e1000);
1721 e1000_initialize_rx_registers(e1000);
1722 e1000_initialize_tx_registers(e1000);
1723 e1000_fill_mac_from_eeprom(e1000);
1724 e1000_initialize_filters(e1000);
1725 e1000_initialize_vlan(e1000);
1726
1727 return EOK;
1728}
1729
1730/** Activate the device to receive and transmit frames
1731 *
1732 * @param nic NIC driver data
1733 *
1734 * @return EOK if activated successfully
1735 * @return Error code otherwise
1736 *
1737 */
1738static int e1000_on_activating(nic_t *nic)
1739{
1740 assert(nic);
1741
1742 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1743
1744 fibril_mutex_lock(&e1000->rx_lock);
1745 fibril_mutex_lock(&e1000->tx_lock);
1746 fibril_mutex_lock(&e1000->ctrl_lock);
1747
1748 e1000_enable_interrupts(e1000);
1749
1750 nic_enable_interrupt(nic, e1000->irq);
1751
1752 e1000_clear_rx_ring(e1000);
1753 e1000_enable_rx(e1000);
1754
1755 e1000_clear_tx_ring(nic);
1756 e1000_enable_tx(e1000);
1757
1758 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1759 ctrl |= CTRL_SLU;
1760 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1761
1762 fibril_mutex_unlock(&e1000->ctrl_lock);
1763 fibril_mutex_unlock(&e1000->tx_lock);
1764 fibril_mutex_unlock(&e1000->rx_lock);
1765
1766 return EOK;
1767}
1768
1769/** Callback for NIC_STATE_DOWN change
1770 *
1771 * @param nic NIC driver data
1772 *
1773 * @return EOK if succeed
1774 * @return Error code otherwise
1775 *
1776 */
1777static int e1000_on_down_unlocked(nic_t *nic)
1778{
1779 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1780
1781 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1782 ctrl &= ~CTRL_SLU;
1783 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1784
1785 e1000_disable_tx(e1000);
1786 e1000_disable_rx(e1000);
1787
1788 nic_disable_interrupt(nic, e1000->irq);
1789 e1000_disable_interrupts(e1000);
1790
1791 /*
1792 * Wait for the for the end of all data
1793 * transfers to descriptors.
1794 */
1795 usleep(100);
1796
1797 return EOK;
1798}
1799
1800/** Callback for NIC_STATE_DOWN change
1801 *
1802 * @param nic NIC driver data
1803 *
1804 * @return EOK if succeed
1805 * @return Error code otherwise
1806 *
1807 */
1808static int e1000_on_down(nic_t *nic)
1809{
1810 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1811
1812 fibril_mutex_lock(&e1000->rx_lock);
1813 fibril_mutex_lock(&e1000->tx_lock);
1814 fibril_mutex_lock(&e1000->ctrl_lock);
1815
1816 int rc = e1000_on_down_unlocked(nic);
1817
1818 fibril_mutex_unlock(&e1000->ctrl_lock);
1819 fibril_mutex_unlock(&e1000->tx_lock);
1820 fibril_mutex_unlock(&e1000->rx_lock);
1821
1822 return rc;
1823}
1824
1825/** Callback for NIC_STATE_STOPPED change
1826 *
1827 * @param nic NIC driver data
1828 *
1829 * @return EOK if succeed
1830 * @return Error code otherwise
1831 *
1832 */
1833static int e1000_on_stopping(nic_t *nic)
1834{
1835 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1836
1837 fibril_mutex_lock(&e1000->rx_lock);
1838 fibril_mutex_lock(&e1000->tx_lock);
1839 fibril_mutex_lock(&e1000->ctrl_lock);
1840
1841 int rc = e1000_on_down_unlocked(nic);
1842 if (rc == EOK)
1843 rc = e1000_reset(nic);
1844
1845 fibril_mutex_unlock(&e1000->ctrl_lock);
1846 fibril_mutex_unlock(&e1000->tx_lock);
1847 fibril_mutex_unlock(&e1000->rx_lock);
1848
1849 return rc;
1850}
1851
1852/** Create driver data structure
1853 *
1854 * @return Intialized device data structure or NULL
1855 *
1856 */
1857static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1858{
1859 assert(dev);
1860 assert(!dev->driver_data);
1861
1862 nic_t *nic = nic_create_and_bind(dev);
1863 if (!nic)
1864 return NULL;
1865
1866 e1000_t *e1000 = malloc(sizeof(e1000_t));
1867 if (!e1000) {
1868 nic_unbind_and_destroy(dev);
1869 return NULL;
1870 }
1871
1872 bzero(e1000, sizeof(e1000_t));
1873
1874 nic_set_specific(nic, e1000);
1875 nic_set_send_frame_handler(nic, e1000_send_frame);
1876 nic_set_state_change_handlers(nic, e1000_on_activating,
1877 e1000_on_down, e1000_on_stopping);
1878 nic_set_filtering_change_handlers(nic,
1879 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1880 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1881 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1882
1883 fibril_mutex_initialize(&e1000->ctrl_lock);
1884 fibril_mutex_initialize(&e1000->rx_lock);
1885 fibril_mutex_initialize(&e1000->tx_lock);
1886 fibril_mutex_initialize(&e1000->eeprom_lock);
1887
1888 return e1000;
1889}
1890
1891/** Delete driver data structure
1892 *
1893 * @param data E1000 device data structure
1894 *
1895 */
1896inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1897{
1898 assert(dev);
1899
1900 if (dev->driver_data != NULL)
1901 nic_unbind_and_destroy(dev);
1902}
1903
1904/** Clean up the E1000 device structure.
1905 *
1906 * @param dev Device structure.
1907 *
1908 */
1909static void e1000_dev_cleanup(ddf_dev_t *dev)
1910{
1911 assert(dev);
1912
1913 e1000_delete_dev_data(dev);
1914
1915 if (dev->parent_sess != NULL) {
1916 async_hangup(dev->parent_sess);
1917 dev->parent_sess = NULL;
1918 }
1919}
1920
1921/** Fill the irq and io_addr part of device data structure
1922 *
1923 * The hw_resources must be obtained before calling this function
1924 *
1925 * @param dev Device structure
1926 * @param hw_resources Hardware resources obtained from the parent device
1927 *
1928 * @return EOK if succeed
1929 * @return Negative error code otherwise
1930 *
1931 */
1932static int e1000_fill_resource_info(ddf_dev_t *dev,
1933 const hw_res_list_parsed_t *hw_resources)
1934{
1935 assert(dev != NULL);
1936 assert(hw_resources != NULL);
1937 assert(dev->driver_data != NULL);
1938
1939 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1940
1941 if (hw_resources->irqs.count != 1)
1942 return EINVAL;
1943
1944 e1000->irq = hw_resources->irqs.irqs[0];
1945 e1000->reg_base_phys =
1946 MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
1947
1948 return EOK;
1949}
1950
1951/** Obtain information about hardware resources of the device
1952 *
1953 * The device must be connected to the parent
1954 *
1955 * @param dev Device structure
1956 *
1957 * @return EOK if succeed
1958 * @return Negative error code otherwise
1959 *
1960 */
1961static int e1000_get_resource_info(ddf_dev_t *dev)
1962{
1963 assert(dev != NULL);
1964 assert(NIC_DATA_DEV(dev) != NULL);
1965
1966 hw_res_list_parsed_t hw_res_parsed;
1967 hw_res_list_parsed_init(&hw_res_parsed);
1968
1969 /* Get hw resources form parent driver */
1970 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1971 if (rc != EOK)
1972 return rc;
1973
1974 /* Fill resources information to the device */
1975 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1976 hw_res_list_parsed_clean(&hw_res_parsed);
1977
1978 return rc;
1979}
1980
1981/** Initialize the E1000 device structure
1982 *
1983 * @param dev Device information
1984 *
1985 * @return EOK if succeed
1986 * @return Negative error code otherwise
1987 *
1988 */
1989static int e1000_device_initialize(ddf_dev_t *dev)
1990{
1991 /* Allocate driver data for the device. */
1992 e1000_t *e1000 = e1000_create_dev_data(dev);
1993 if (e1000 == NULL) {
1994 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1995 return ENOMEM;
1996 }
1997
1998 /* Obtain and fill hardware resources info */
1999 int rc = e1000_get_resource_info(dev);
2000 if (rc != EOK) {
2001 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2002 e1000_dev_cleanup(dev);
2003 return rc;
2004 }
2005
2006 uint16_t device_id;
2007 rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
2008 &device_id);
2009 if (rc != EOK) {
2010 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2011 e1000_dev_cleanup(dev);
2012 return rc;
2013 }
2014
2015 e1000_board_t board;
2016 switch (device_id) {
2017 case 0x100e:
2018 case 0x1015:
2019 case 0x1016:
2020 case 0x1017:
2021 board = E1000_82540;
2022 break;
2023 case 0x1013:
2024 case 0x1018:
2025 case 0x1078:
2026 board = E1000_82541;
2027 break;
2028 case 0x1076:
2029 case 0x1077:
2030 case 0x107c:
2031 board = E1000_82541REV2;
2032 break;
2033 case 0x100f:
2034 case 0x1011:
2035 case 0x1026:
2036 case 0x1027:
2037 case 0x1028:
2038 board = E1000_82545;
2039 break;
2040 case 0x1010:
2041 case 0x1012:
2042 case 0x101d:
2043 case 0x1079:
2044 case 0x107a:
2045 case 0x107b:
2046 board = E1000_82546;
2047 break;
2048 case 0x1019:
2049 case 0x101a:
2050 board = E1000_82547;
2051 break;
2052 case 0x10b9:
2053 board = E1000_82572;
2054 break;
2055 case 0x1096:
2056 board = E1000_80003ES2;
2057 break;
2058 default:
2059 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2060 device_id);
2061 e1000_dev_cleanup(dev);
2062 return ENOTSUP;
2063 }
2064
2065 switch (board) {
2066 case E1000_82540:
2067 case E1000_82541:
2068 case E1000_82541REV2:
2069 case E1000_82545:
2070 case E1000_82546:
2071 e1000->info.eerd_start = 0x01;
2072 e1000->info.eerd_done = 0x10;
2073 e1000->info.eerd_address_offset = 8;
2074 e1000->info.eerd_data_offset = 16;
2075 break;
2076 case E1000_82547:
2077 case E1000_82572:
2078 case E1000_80003ES2:
2079 e1000->info.eerd_start = 0x01;
2080 e1000->info.eerd_done = 0x02;
2081 e1000->info.eerd_address_offset = 2;
2082 e1000->info.eerd_data_offset = 16;
2083 break;
2084 }
2085
2086 return EOK;
2087}
2088
2089/** Enable the I/O ports of the device.
2090 *
2091 * @param dev E1000 device.
2092 *
2093 * @return EOK if successed
2094 * @return Negative error code otherwise
2095 *
2096 */
2097static int e1000_pio_enable(ddf_dev_t *dev)
2098{
2099 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2100
2101 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2102 &e1000->reg_base_virt);
2103 if (rc != EOK)
2104 return EADDRNOTAVAIL;
2105
2106 return EOK;
2107}
2108
2109/** Probe and initialize the newly added device.
2110 *
2111 * @param dev E1000 device.
2112 *
2113 */
2114int e1000_dev_add(ddf_dev_t *dev)
2115{
2116 ddf_fun_t *fun;
2117 assert(dev);
2118
2119 /* Initialize device structure for E1000 */
2120 int rc = e1000_device_initialize(dev);
2121 if (rc != EOK)
2122 return rc;
2123
2124 /* Device initialization */
2125 nic_t *nic = dev->driver_data;
2126 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2127
2128 /* Map registers */
2129 rc = e1000_pio_enable(dev);
2130 if (rc != EOK)
2131 goto err_destroy;
2132
2133 e1000_initialize_registers(e1000);
2134 rc = e1000_initialize_tx_structure(e1000);
2135 if (rc != EOK)
2136 goto err_pio;
2137
2138 fibril_mutex_lock(&e1000->rx_lock);
2139
2140 e1000_fill_mac_from_eeprom(e1000);
2141 e1000_initialize_filters(e1000);
2142
2143 fibril_mutex_unlock(&e1000->rx_lock);
2144
2145 e1000_initialize_vlan(e1000);
2146
2147 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2148 if (fun == NULL)
2149 goto err_tx_structure;
2150 nic_set_ddf_fun(nic, fun);
2151 fun->ops = &e1000_dev_ops;
2152 fun->driver_data = nic;
2153
2154 rc = e1000_register_int_handler(nic);
2155 if (rc != EOK)
2156 goto err_fun_create;
2157
2158 rc = nic_connect_to_services(nic);
2159 if (rc != EOK)
2160 goto err_irq;
2161
2162 rc = e1000_initialize_rx_structure(nic);
2163 if (rc != EOK)
2164 goto err_irq;
2165
2166 nic_address_t e1000_address;
2167 e1000_get_address(e1000, &e1000_address);
2168 rc = nic_report_address(nic, &e1000_address);
2169 if (rc != EOK)
2170 goto err_rx_structure;
2171
2172 struct timeval period;
2173 period.tv_sec = 0;
2174 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2175 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2176 if (rc != EOK)
2177 goto err_rx_structure;
2178
2179 rc = ddf_fun_bind(fun);
2180 if (rc != EOK)
2181 goto err_fun_bind;
2182
2183 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2184 if (rc != EOK)
2185 goto err_add_to_cat;
2186
2187 return EOK;
2188
2189err_add_to_cat:
2190 ddf_fun_unbind(fun);
2191err_fun_bind:
2192err_rx_structure:
2193 e1000_uninitialize_rx_structure(nic);
2194err_irq:
2195 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
2196err_fun_create:
2197 ddf_fun_destroy(fun);
2198 nic_set_ddf_fun(nic, NULL);
2199err_tx_structure:
2200 e1000_uninitialize_tx_structure(e1000);
2201err_pio:
2202 // TODO: e1000_pio_disable(dev);
2203err_destroy:
2204 e1000_dev_cleanup(dev);
2205 return rc;
2206}
2207
2208/** Read 16-bit value from EEPROM of E1000 adapter
2209 *
2210 * Read using the EERD register.
2211 *
2212 * @param device E1000 device
2213 * @param eeprom_address 8-bit EEPROM address
2214 *
2215 * @return 16-bit value from EEPROM
2216 *
2217 */
2218static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2219{
2220 fibril_mutex_lock(&e1000->eeprom_lock);
2221
2222 /* Write address and START bit to EERD register */
2223 uint32_t write_data = e1000->info.eerd_start |
2224 (((uint32_t) eeprom_address) <<
2225 e1000->info.eerd_address_offset);
2226 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2227
2228 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2229 while ((eerd & e1000->info.eerd_done) == 0) {
2230 usleep(1);
2231 eerd = E1000_REG_READ(e1000, E1000_EERD);
2232 }
2233
2234 fibril_mutex_unlock(&e1000->eeprom_lock);
2235
2236 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2237}
2238
2239/** Get MAC address of the E1000 adapter
2240 *
2241 * @param device E1000 device
2242 * @param address Place to store the address
2243 * @param max_len Maximal addresss length to store
2244 *
2245 * @return EOK if succeed
2246 * @return Negative error code otherwise
2247 *
2248 */
2249static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2250{
2251 fibril_mutex_lock(&e1000->rx_lock);
2252
2253 uint8_t *mac0_dest = (uint8_t *) address->address;
2254 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2255 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2256 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2257 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2258 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2259
2260 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2261 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2262
2263 *mac0_dest = (uint8_t) ral;
2264 *mac1_dest = (uint8_t) (ral >> 8);
2265 *mac2_dest = (uint8_t) (ral >> 16);
2266 *mac3_dest = (uint8_t) (ral >> 24);
2267 *mac4_dest = (uint8_t) rah;
2268 *mac5_dest = (uint8_t) (rah >> 8);
2269
2270 fibril_mutex_unlock(&e1000->rx_lock);
2271 return EOK;
2272};
2273
2274/** Set card MAC address
2275 *
2276 * @param device E1000 device
2277 * @param address Address
2278 *
2279 * @return EOK if succeed
2280 * @return Negative error code otherwise
2281 */
2282static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
2283{
2284 nic_t *nic = NIC_DATA_DEV(dev);
2285 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2286
2287 fibril_mutex_lock(&e1000->rx_lock);
2288 fibril_mutex_lock(&e1000->tx_lock);
2289
2290 int rc = nic_report_address(nic, addr);
2291 if (rc == EOK)
2292 e1000_write_receive_address(e1000, 0, addr, false);
2293
2294 fibril_mutex_unlock(&e1000->tx_lock);
2295 fibril_mutex_unlock(&e1000->rx_lock);
2296
2297 return rc;
2298}
2299
2300static void e1000_eeprom_get_address(e1000_t *e1000,
2301 nic_address_t *address)
2302{
2303 uint16_t *mac0_dest = (uint16_t *) address->address;
2304 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2305 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2306
2307 *mac0_dest = e1000_eeprom_read(e1000, 0);
2308 *mac2_dest = e1000_eeprom_read(e1000, 1);
2309 *mac4_dest = e1000_eeprom_read(e1000, 2);
2310}
2311
2312/** Send frame
2313 *
2314 * @param nic NIC driver data structure
2315 * @param data Frame data
2316 * @param size Frame size in bytes
2317 *
2318 * @return EOK if succeed
2319 * @return Error code in the case of error
2320 *
2321 */
2322static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2323{
2324 assert(nic);
2325
2326 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2327 fibril_mutex_lock(&e1000->tx_lock);
2328
2329 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2330 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2331 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2332
2333 bool descriptor_available = false;
2334
2335 /* Descriptor never used */
2336 if (tx_descriptor_addr->length == 0)
2337 descriptor_available = true;
2338
2339 /* Descriptor done */
2340 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2341 descriptor_available = true;
2342
2343 if (!descriptor_available) {
2344 /* Frame lost */
2345 fibril_mutex_unlock(&e1000->tx_lock);
2346 return;
2347 }
2348
2349 memcpy(e1000->tx_frame_virt[tdt], data, size);
2350
2351 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2352 tx_descriptor_addr->length = size;
2353
2354 /*
2355 * Report status to STATUS.DD (descriptor done),
2356 * add ethernet CRC, end of packet.
2357 */
2358 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2359 TXDESCRIPTOR_COMMAND_IFCS |
2360 TXDESCRIPTOR_COMMAND_EOP;
2361
2362 tx_descriptor_addr->checksum_offset = 0;
2363 tx_descriptor_addr->status = 0;
2364 if (e1000->vlan_tag_add) {
2365 tx_descriptor_addr->special = e1000->vlan_tag;
2366 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2367 } else
2368 tx_descriptor_addr->special = 0;
2369
2370 tx_descriptor_addr->checksum_start_field = 0;
2371
2372 tdt++;
2373 if (tdt == E1000_TX_FRAME_COUNT)
2374 tdt = 0;
2375
2376 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2377
2378 fibril_mutex_unlock(&e1000->tx_lock);
2379}
2380
2381int main(void)
2382{
2383 int rc = nic_driver_init(NAME);
2384 if (rc != EOK)
2385 return rc;
2386
2387 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2388 &e1000_nic_iface);
2389
2390 ddf_log_init(NAME, LVL_ERROR);
2391 ddf_msg(LVL_NOTE, "HelenOS E1000 driver started");
2392 return ddf_driver_main(&e1000_driver);
2393}
Note: See TracBrowser for help on using the repository browser.