source: mainline/uspace/drv/nic/e1k/e1k.c@ 9916841

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9916841 was 9916841, checked in by Martin Decky <martin@…>, 14 years ago

make the e1k driver compile (non-fuctional)
  • Property mode set to 100644
File size: 54.3 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <byteorder.h>
41#include <sysinfo.h>
42#include <ipc/irc.h>
43#include <ipc/ns.h>
44#include <libarch/ddi.h>
45#include <as.h>
46#include <ddf/interrupt.h>
47#include <devman.h>
48#include <device/hw_res_parsed.h>
49#include <device/pci.h>
50#include <nic.h>
51#include <nil_remote.h>
52#include <ops/nic.h>
53#include <packet_client.h>
54#include <packet_remote.h>
55#include <net/packet_header.h>
56#include "e1k.h"
57
58#define NAME "e1k"
59
60#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
61
62/* Must be power of 8 */
63#define E1000_RX_PACKETS_COUNT 128
64#define E1000_TX_PACKETS_COUNT 128
65
66#define E1000_RECEIVE_ADDRESS 16
67
68/** Maximum receiving packet size */
69#define E1000_MAX_RECEIVE_PACKET_SIZE 2048
70
71/** nic_driver_data_t* -> e1000_t* cast */
72#define DRIVER_DATA_NIC(nic_data) \
73 ((e1000_t *) nic_get_specific(nic_data))
74
75/** device_t* -> nic_driver_data_t* cast */
76#define NIC_DATA_DEV(dev) \
77 ((nic_t *) ((dev)->driver_data))
78
79/** device_t* -> e1000_t* cast */
80#define DRIVER_DATA_DEV(dev) \
81 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
82
83/** Cast pointer to uint64_t
84 *
85 * @param ptr Pointer to cast
86 *
87 * @return The uint64_t pointer representation.
88 *
89 */
90#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
91
92/** Cast the memaddr part to the void*
93 *
94 * @param memaddr The memaddr value
95 *
96 */
97#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
98
99#define E1000_REG_BASE(e1000_data) \
100 ((e1000_data)->virt_reg_base)
101
102#define E1000_REG_ADDR(e1000_data, reg) \
103 ((uint32_t *) (E1000_REG_BASE(e1000_data) + reg))
104
105#define E1000_REG_READ(e1000_data, reg) \
106 (pio_read_32(E1000_REG_ADDR(e1000_data, reg)))
107
108#define E1000_REG_WRITE(e1000_data, reg, value) \
109 (pio_write_32(E1000_REG_ADDR(e1000_data, reg), value))
110
111/** E1000 device data */
112typedef struct e1000_data {
113 /** Physical registers base address */
114 void *phys_reg_base;
115 /** Virtual registers base address */
116 void *virt_reg_base;
117 /** Tx ring */
118 dmamem_t tx_ring;
119 /** Packets in tx ring */
120 packet_t **tx_ring_packets;
121 /** Rx ring */
122 dmamem_t rx_ring;
123 /** Packets in rx ring */
124 packet_t **rx_ring_packets;
125 /** VLAN tag */
126 uint16_t vlan_tag;
127 /** Add VLAN tag to packet */
128 bool vlan_tag_add;
129 /** Used unicast Receive Address count */
130 unsigned int unicast_ra_count;
131 /** Used milticast Receive addrress count */
132 unsigned int multicast_ra_count;
133 /** PCI device ID */
134 uint16_t device_id;
135 /** The irq assigned */
136 int irq;
137 /** Lock for CTRL register */
138 fibril_mutex_t ctrl_lock;
139 /** Lock for receiver */
140 fibril_mutex_t rx_lock;
141 /** Lock for transmitter */
142 fibril_mutex_t tx_lock;
143 /** Lock for EEPROM access */
144 fibril_mutex_t eeprom_lock;
145} e1000_t;
146
147/** Global mutex for work with shared irq structure */
148FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
149
150static int e1000_get_address(e1000_t *, nic_address_t *);
151static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
152static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
153
154static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
155static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
156
157static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
158static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
159static int e1000_get_operation_mode(ddf_fun_t *, int *,
160 nic_channel_mode_t *, nic_role_t *);
161static int e1000_set_operation_mode(ddf_fun_t *, int,
162 nic_channel_mode_t, nic_role_t);
163static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
164static int e1000_autoneg_disable(ddf_fun_t *);
165static int e1000_autoneg_restart(ddf_fun_t *);
166
167static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
168
169/** Network interface options for E1000 card driver */
170static nic_iface_t e1000_nic_iface;
171
172/** Network interface options for E1000 card driver */
173static nic_iface_t e1000_nic_iface = {
174 .set_address = &e1000_set_addr,
175 .get_device_info = &e1000_get_device_info,
176 .get_cable_state = &e1000_get_cable_state,
177 .get_operation_mode = &e1000_get_operation_mode,
178 .set_operation_mode = &e1000_set_operation_mode,
179 .autoneg_enable = &e1000_autoneg_enable,
180 .autoneg_disable = &e1000_autoneg_disable,
181 .autoneg_restart = &e1000_autoneg_restart,
182 .vlan_set_tag = &e1000_vlan_set_tag,
183 .defective_get_mode = &e1000_defective_get_mode,
184 .defective_set_mode = &e1000_defective_set_mode,
185};
186
187/** Basic device operations for E1000 driver */
188static ddf_dev_ops_t e1000_dev_ops;
189
190static int e1000_dev_add(ddf_dev_t *);
191
192/** Basic driver operations for E1000 driver */
193static driver_ops_t e1000_driver_ops = {
194 .dev_add = e1000_dev_add
195};
196
197/** Driver structure for E1000 driver */
198static driver_t e1000_driver = {
199 .name = NAME,
200 .driver_ops = &e1000_driver_ops
201};
202
203/* The default implementation callbacks */
204static int e1000_on_activating(nic_t *);
205static int e1000_on_stopping(nic_t *);
206static void e1000_write_packet(nic_t *, packet_t *);
207
208/** Commands to deal with interrupt
209 *
210 */
211irq_cmd_t e1000_irq_commands[] = {
212 {
213 /* Get the interrupt status */
214 .cmd = CMD_PIO_READ_32,
215 .addr = NULL,
216 .dstarg = 2
217 },
218 {
219 .cmd = CMD_PREDICATE,
220 .value = 2,
221 .srcarg = 2
222 },
223 {
224 /* Disable interrupts until interrupt routine is finished */
225 .cmd = CMD_PIO_WRITE_32,
226 .addr = NULL,
227 .value = 0xFFFFFFFF
228 },
229 {
230 .cmd = CMD_ACCEPT
231 }
232};
233
234/** Interrupt code definition */
235irq_code_t e1000_irq_code = {
236 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
237 .cmds = e1000_irq_commands
238};
239
240/** Get the device information
241 *
242 * @param dev NIC device
243 * @param info Information to fill
244 *
245 * @return EOK
246 *
247 */
248static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
249{
250 assert(dev);
251 assert(info);
252
253 bzero(info, sizeof(nic_device_info_t));
254
255 info->vendor_id = 0x8086;
256 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
257 "Intel Corporation");
258 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
259 "Intel Pro");
260
261 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
262 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
263 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
264
265 return EOK;
266}
267
268/** Check the cable state
269 *
270 * @param[in] dev device
271 * @param[out] state state to fill
272 *
273 * @return EOK
274 *
275 */
276static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
277{
278 assert(dev);
279 assert(DRIVER_DATA_DEV(dev));
280 assert(state);
281
282 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
283 if (E1000_REG_READ(e1000_data, E1000_STATUS) & (STATUS_LU))
284 *state = NIC_CS_PLUGGED;
285 else
286 *state = NIC_CS_UNPLUGGED;
287
288 return EOK;
289}
290
291static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
292{
293 return useconds * 4;
294}
295
296/** Get operation mode of the device
297 *
298 */
299static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
300 nic_channel_mode_t *duplex, nic_role_t *role)
301{
302 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
303 uint32_t status = E1000_REG_READ(e1000_data, E1000_STATUS);
304
305 if (status & STATUS_FD)
306 *duplex = NIC_CM_FULL_DUPLEX;
307 else
308 *duplex = NIC_CM_HALF_DUPLEX;
309
310 uint32_t speed_bits =
311 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
312
313 if (speed_bits == STATUS_SPEED_10)
314 *speed = 10;
315 else if (speed_bits == STATUS_SPEED_100)
316 *speed = 100;
317 else if ((speed_bits == STATUS_SPEED_1000A) ||
318 (speed_bits == STATUS_SPEED_1000B))
319 *speed = 1000;
320
321 *role = NIC_ROLE_UNKNOWN;
322 return EOK;
323}
324
325static void e1000_link_restart(e1000_t * e1000_data)
326{
327 fibril_mutex_lock(&e1000_data->ctrl_lock);
328
329 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
330
331 if (ctrl & CTRL_SLU) {
332 ctrl &= ~(CTRL_SLU);
333 fibril_mutex_unlock(&e1000_data->ctrl_lock);
334 usleep(10);
335 fibril_mutex_lock(&e1000_data->ctrl_lock);
336 ctrl |= CTRL_SLU;
337 }
338
339 fibril_mutex_unlock(&e1000_data->ctrl_lock);
340
341 e1000_link_restart(e1000_data);
342}
343
344/** Set operation mode of the device
345 *
346 */
347static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
348 nic_channel_mode_t duplex, nic_role_t role)
349{
350 if ((speed != 10) && (speed != 100) && (speed != 1000))
351 return EINVAL;
352
353 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
354 return EINVAL;
355
356 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
357
358 fibril_mutex_lock(&e1000_data->ctrl_lock);
359 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
360
361 ctrl |= CTRL_FRCSPD;
362 ctrl |= CTRL_FRCDPLX;
363 ctrl &= ~(CTRL_ASDE);
364
365 if (duplex == NIC_CM_FULL_DUPLEX)
366 ctrl |= CTRL_FD;
367 else
368 ctrl &= ~(CTRL_FD);
369
370 ctrl &= ~(CTRL_SPEED_MASK);
371 if (speed == 1000)
372 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
373 else if (speed == 100)
374 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
375 else
376 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
377
378 E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl);
379
380 fibril_mutex_unlock(&e1000_data->ctrl_lock);
381
382 e1000_link_restart(e1000_data);
383
384 return EOK;
385}
386
387/** Enable auto-negotiation
388 *
389 * @param dev Device to update
390 * @param advertisement Ignored on E1000
391 *
392 * @return EOK if advertisement mode set successfully
393 *
394 */
395static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
396{
397 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
398
399 fibril_mutex_lock(&e1000_data->ctrl_lock);
400
401 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
402
403 ctrl &= ~(CTRL_FRCSPD);
404 ctrl &= ~(CTRL_FRCDPLX);
405 ctrl |= CTRL_ASDE;
406
407 E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl);
408
409 fibril_mutex_unlock(&e1000_data->ctrl_lock);
410
411 e1000_link_restart(e1000_data);
412
413 return EOK;
414}
415
416/** Disable auto-negotiation
417 *
418 * @param dev Device to update
419 *
420 * @return EOK
421 *
422 */
423static int e1000_autoneg_disable(ddf_fun_t *dev)
424{
425 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
426
427 fibril_mutex_lock(&e1000_data->ctrl_lock);
428
429 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
430
431 ctrl |= CTRL_FRCSPD;
432 ctrl |= CTRL_FRCDPLX;
433 ctrl &= ~(CTRL_ASDE);
434
435 E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl);
436
437 fibril_mutex_unlock(&e1000_data->ctrl_lock);
438
439 e1000_link_restart(e1000_data);
440
441 return EOK;
442}
443
444/** Restart auto-negotiation
445 *
446 * @param dev Device to update
447 *
448 * @return EOK if advertisement mode set successfully
449 *
450 */
451static int e1000_autoneg_restart(ddf_fun_t *dev)
452{
453 return e1000_autoneg_enable(dev, 0);
454}
455
456/** Get state of acceptance of weird packets
457 *
458 * @param device Device to check
459 * @param[out] mode Current mode
460 *
461 */
462static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
463{
464 e1000_t *e1000_data = DRIVER_DATA_DEV(device);
465
466 *mode = 0;
467 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
468 if (rctl & RCTL_SBP)
469 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
470
471 return EOK;
472};
473
474/** Set acceptance of weird packets
475 *
476 * @param device Device to update
477 * @param mode Mode to set
478 *
479 * @return ENOTSUP if the mode is not supported
480 * @return EOK of mode was set
481 *
482 */
483static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
484{
485 e1000_t *e1000_data = DRIVER_DATA_DEV(device);
486 int rc = EOK;
487
488 fibril_mutex_lock(&e1000_data->rx_lock);
489
490 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
491 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
492 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
493
494 if (short_mode && bad_mode)
495 rctl |= RCTL_SBP;
496 else if ((!short_mode) && (!bad_mode))
497 rctl &= ~RCTL_SBP;
498 else
499 rc = ENOTSUP;
500
501 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
502
503 fibril_mutex_unlock(&e1000_data->rx_lock);
504 return rc;
505};
506
507/** Write receive address to RA registr
508 *
509 * @param e1000_data E1000 data structure
510 * @param position RA register position
511 * @param address Ethernet address
512 * @param set_av_bit Set the Addtess Valid bit
513 *
514 */
515static void e1000_write_receive_address(e1000_t *e1000_data,
516 unsigned int position, const nic_address_t * address,
517 bool set_av_bit)
518{
519 uint8_t *mac0 = (uint8_t *) address->address;
520 uint8_t *mac1 = (uint8_t *) address->address + 1;
521 uint8_t *mac2 = (uint8_t *) address->address + 2;
522 uint8_t *mac3 = (uint8_t *) address->address + 3;
523 uint8_t *mac4 = (uint8_t *) address->address + 4;
524 uint8_t *mac5 = (uint8_t *) address->address + 5;
525
526 uint32_t rah;
527 uint32_t ral;
528
529 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
530 rah = ((*mac5) << 8) | ((*mac4));
531
532 if (set_av_bit)
533 rah |= RAH_AV;
534 else
535 rah |= E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(position)) &
536 RAH_AV;
537
538 E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(position), rah);
539 E1000_REG_WRITE(e1000_data, E1000_RAL_ARRAY(position), ral);
540}
541
542/** Disable receive address in RA registr
543 *
544 * Clear Address Valid bit
545 *
546 * @param e1000_data E1000 data structure
547 * @param position RA register position
548 *
549 */
550static void e1000_disable_receive_address(e1000_t *e1000_data,
551 unsigned int position)
552{
553 uint32_t rah =
554 E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(position));
555 rah = rah & ~RAH_AV;
556 E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(position), rah);
557}
558
559/** Clear all unicast addresses from RA registers
560 *
561 * @param e1000_data E1000 data structure
562 *
563 */
564static void e1000_clear_unicast_receive_addresses(e1000_t *e1000_data)
565{
566 for (unsigned int ra_num = 1;
567 ra_num <= e1000_data->unicast_ra_count;
568 ra_num++)
569 e1000_disable_receive_address(e1000_data, ra_num);
570
571 e1000_data->unicast_ra_count = 0;
572}
573
574/** Clear all multicast addresses from RA registers
575 *
576 * @param e1000_data E1000 data structure
577 *
578 */
579static void e1000_clear_multicast_receive_addresses(e1000_t *e1000_data)
580{
581 unsigned int first_multicast_ra_num =
582 E1000_RECEIVE_ADDRESS - e1000_data->multicast_ra_count;
583
584 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
585 ra_num >= first_multicast_ra_num;
586 ra_num--)
587 e1000_disable_receive_address(e1000_data, ra_num);
588
589 e1000_data->multicast_ra_count = 0;
590}
591
592/** Return receive address filter positions count usable for unicast
593 *
594 * @param e1000_data E1000 data structure
595 *
596 * @return receive address filter positions count usable for unicast
597 *
598 */
599static unsigned int get_free_unicast_address_count(e1000_t *e1000_data)
600{
601 return E1000_RECEIVE_ADDRESS - 1 - e1000_data->multicast_ra_count;
602}
603
604/** Return receive address filter positions count usable for multicast
605 *
606 * @param e1000_data E1000 data structure
607 *
608 * @return receive address filter positions count usable for multicast
609 *
610 */
611static unsigned int get_free_multicast_address_count(e1000_t *e1000_data)
612{
613 return E1000_RECEIVE_ADDRESS - 1 - e1000_data->unicast_ra_count;
614}
615
616/** Write unicast receive addresses to receive address filter registers
617 *
618 * @param e1000_data E1000 data structure
619 * @param addr Pointer to address array
620 * @param addr_cnt Address array count
621 *
622 */
623static void e1000_add_unicast_receive_addresses(e1000_t *e1000_data,
624 const nic_address_t *addr, size_t addr_cnt)
625{
626 assert(addr_cnt <= get_free_unicast_address_count(e1000_data));
627
628 nic_address_t *addr_iterator = (nic_address_t *) addr;
629
630 /* ra_num = 0 is primary address */
631 for (unsigned int ra_num = 1;
632 ra_num <= addr_cnt;
633 ra_num++) {
634 e1000_write_receive_address(e1000_data, ra_num, addr_iterator, true);
635 addr_iterator++;
636 }
637}
638
639/** Write multicast receive addresses to receive address filter registers
640 *
641 * @param e1000_data E1000 data structure
642 * @param addr Pointer to address array
643 * @param addr_cnt Address array count
644 *
645 */
646static void e1000_add_multicast_receive_addresses(e1000_t *e1000_data,
647 const nic_address_t *addr, size_t addr_cnt)
648{
649 assert(addr_cnt <= get_free_multicast_address_count(e1000_data));
650
651 nic_address_t *addr_iterator = (nic_address_t *) addr;
652
653 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
654 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
655 ra_num >= first_multicast_ra_num;
656 ra_num--) {
657 e1000_write_receive_address(e1000_data, ra_num, addr_iterator, true);
658 addr_iterator++;
659 }
660}
661
662/** Disable receiving packets for default address
663 *
664 * @param e1000_data E1000 data structure
665 *
666 */
667static void disable_ra0_address_filter(e1000_t *e1000_data)
668{
669 uint32_t rah0 = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(0));
670 rah0 = rah0 & ~RAH_AV;
671 E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(0), rah0);
672}
673
674/** Enable receiving packets for default address
675 *
676 * @param e1000_data E1000 data structure
677 *
678 */
679static void enable_ra0_address_filter(e1000_t *e1000_data)
680{
681 uint32_t rah0 = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(0));
682 rah0 = rah0 | RAH_AV;
683 E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(0), rah0);
684}
685
686/** Disable unicast promiscuous mode
687 *
688 * @param e1000_data E1000 data structure
689 *
690 */
691static void e1000_disable_unicast_promisc(e1000_t *e1000_data)
692{
693 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
694 rctl = rctl & ~RCTL_UPE;
695 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
696}
697
698/** Enable unicast promiscuous mode
699 *
700 * @param e1000_data E1000 data structure
701 *
702 */
703static void e1000_enable_unicast_promisc(e1000_t *e1000_data)
704{
705 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
706 rctl = rctl | RCTL_UPE;
707 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
708}
709
710/** Disable multicast promiscuous mode
711 *
712 * @param e1000_data E1000 data structure
713 *
714 */
715static void e1000_disable_multicast_promisc(e1000_t *e1000_data)
716{
717 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
718 rctl = rctl & ~RCTL_MPE;
719 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
720}
721
722/** Enable multicast promiscuous mode
723 *
724 * @param e1000_data E1000 data structure
725 *
726 */
727static void e1000_enable_multicast_promisc(e1000_t *e1000_data)
728{
729 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
730 rctl = rctl | RCTL_MPE;
731 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
732}
733
734/** Enable accepting of broadcast packets
735 *
736 * @param e1000_data E1000 data structure
737 *
738 */
739static void e1000_enable_broadcast_accept(e1000_t *e1000_data)
740{
741 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
742 rctl = rctl | RCTL_BAM;
743 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
744}
745
746/** Disable accepting of broadcast packets
747 *
748 * @param e1000_data E1000 data structure
749 *
750 */
751static void e1000_disable_broadcast_accept(e1000_t *e1000_data)
752{
753 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
754 rctl = rctl & ~RCTL_BAM;
755 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
756}
757
758/** Enable VLAN filtering according to VFTA registers
759 *
760 * @param e1000_data E1000 data structure
761 *
762 */
763static void e1000_enable_vlan_filter(e1000_t *e1000_data)
764{
765 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
766 rctl = rctl | RCTL_VFE;
767 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
768}
769
770/** Disable VLAN filtering
771 *
772 * @param e1000_data E1000 data structure
773 *
774 */
775static void e1000_disable_vlan_filter(e1000_t *e1000_data)
776{
777 uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL);
778 rctl = rctl & ~RCTL_VFE;
779 E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl);
780}
781
782/** Set multicast packets acceptance mode
783 *
784 * @param nic_data NIC device to update
785 * @param mode Mode to set
786 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
787 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
788 *
789 * @return EOK
790 *
791 */
792static int e1000_on_multicast_mode_change(nic_t *nic_data,
793 nic_multicast_mode_t mode, const nic_address_t *addr, size_t addr_cnt)
794{
795 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
796 int rc = EOK;
797
798 fibril_mutex_lock(&e1000_data->rx_lock);
799
800 switch (mode) {
801 case NIC_MULTICAST_BLOCKED:
802 e1000_clear_multicast_receive_addresses(e1000_data);
803 e1000_disable_multicast_promisc(e1000_data);
804 nic_report_hw_filtering(nic_data, -1, 1, -1);
805 break;
806 case NIC_MULTICAST_LIST:
807 e1000_clear_multicast_receive_addresses(e1000_data);
808 if (addr_cnt > get_free_multicast_address_count(e1000_data)) {
809 /*
810 * Future work: fill MTA table
811 * Not strictly neccessary, it only saves some compares
812 * in the NIC library.
813 */
814 e1000_enable_multicast_promisc(e1000_data);
815 nic_report_hw_filtering(nic_data, -1, 0, -1);
816 } else {
817 e1000_disable_multicast_promisc(e1000_data);
818 e1000_add_multicast_receive_addresses(e1000_data, addr, addr_cnt);
819 nic_report_hw_filtering(nic_data, -1, 1, -1);
820 }
821 break;
822 case NIC_MULTICAST_PROMISC:
823 e1000_enable_multicast_promisc(e1000_data);
824 e1000_clear_multicast_receive_addresses(e1000_data);
825 nic_report_hw_filtering(nic_data, -1, 1, -1);
826 break;
827 default:
828 rc = ENOTSUP;
829 break;
830 }
831
832 fibril_mutex_unlock(&e1000_data->rx_lock);
833 return rc;
834}
835
836/** Set unicast packets acceptance mode
837 *
838 * @param nic_data NIC device to update
839 * @param mode Mode to set
840 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
841 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
842 *
843 * @return EOK
844 *
845 */
846static int e1000_on_unicast_mode_change(nic_t *nic_data,
847 nic_unicast_mode_t mode, const nic_address_t *addr, size_t addr_cnt)
848{
849 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
850 int rc = EOK;
851
852 fibril_mutex_lock(&e1000_data->rx_lock);
853
854 switch (mode) {
855 case NIC_UNICAST_BLOCKED:
856 disable_ra0_address_filter(e1000_data);
857 e1000_clear_unicast_receive_addresses(e1000_data);
858 e1000_disable_unicast_promisc(e1000_data);
859 nic_report_hw_filtering(nic_data, 1, -1, -1);
860 break;
861 case NIC_UNICAST_DEFAULT:
862 enable_ra0_address_filter(e1000_data);
863 e1000_clear_unicast_receive_addresses(e1000_data);
864 e1000_disable_unicast_promisc(e1000_data);
865 nic_report_hw_filtering(nic_data, 1, -1, -1);
866 break;
867 case NIC_UNICAST_LIST:
868 enable_ra0_address_filter(e1000_data);
869 e1000_clear_unicast_receive_addresses(e1000_data);
870 if (addr_cnt > get_free_unicast_address_count(e1000_data)) {
871 e1000_enable_unicast_promisc(e1000_data);
872 nic_report_hw_filtering(nic_data, 0, -1, -1);
873 } else {
874 e1000_disable_unicast_promisc(e1000_data);
875 e1000_add_unicast_receive_addresses(e1000_data, addr, addr_cnt);
876 nic_report_hw_filtering(nic_data, 1, -1, -1);
877 }
878 break;
879 case NIC_UNICAST_PROMISC:
880 e1000_enable_unicast_promisc(e1000_data);
881 enable_ra0_address_filter(e1000_data);
882 e1000_clear_unicast_receive_addresses(e1000_data);
883 nic_report_hw_filtering(nic_data, 1, -1, -1);
884 break;
885 default:
886 rc = ENOTSUP;
887 break;
888 }
889
890 fibril_mutex_unlock(&e1000_data->rx_lock);
891 return rc;
892}
893
894/** Set broadcast packets acceptance mode
895 *
896 * @param nic_data NIC device to update
897 * @param mode Mode to set
898 *
899 * @return EOK
900 *
901 */
902static int e1000_on_broadcast_mode_change(nic_t *nic_data,
903 nic_broadcast_mode_t mode)
904{
905 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
906 int rc = EOK;
907
908 fibril_mutex_lock(&e1000_data->rx_lock);
909
910 switch (mode) {
911 case NIC_BROADCAST_BLOCKED:
912 e1000_disable_broadcast_accept(e1000_data);
913 break;
914 case NIC_BROADCAST_ACCEPTED:
915 e1000_enable_broadcast_accept(e1000_data);
916 break;
917 default:
918 rc = ENOTSUP;
919 break;
920 }
921
922 fibril_mutex_unlock(&e1000_data->rx_lock);
923 return rc;
924}
925
926/** Check if receiving is enabled
927 *
928 * @param e1000_data E1000 data structure
929 *
930 * @return true if receiving is enabled
931 *
932 */
933static bool e1000_is_rx_enabled(e1000_t *e1000_data)
934{
935 if (E1000_REG_READ(e1000_data, E1000_RCTL) & (RCTL_EN))
936 return true;
937
938 return false;
939}
940
941/** Enable receiving
942 *
943 * @param e1000_data E1000 data structure
944 *
945 */
946static void e1000_enable_rx(e1000_t *e1000_data)
947{
948 /* Set Receive Enable Bit */
949 E1000_REG_WRITE(e1000_data, E1000_RCTL,
950 E1000_REG_READ(e1000_data, E1000_RCTL) | (RCTL_EN));
951}
952
953/** Disable receiving
954 *
955 * @param e1000_data E1000 data structure
956 *
957 */
958static void e1000_disable_rx(e1000_t *e1000_data)
959{
960 /* Clear Receive Enable Bit */
961 E1000_REG_WRITE(e1000_data, E1000_RCTL,
962 E1000_REG_READ(e1000_data, E1000_RCTL) & ~(RCTL_EN));
963}
964
965/** Set VLAN mask
966 *
967 * @param nic_data NIC device to update
968 * @param vlan_mask VLAN mask
969 *
970 */
971static void e1000_on_vlan_mask_change(nic_t *nic_data,
972 const nic_vlan_mask_t *vlan_mask)
973{
974 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
975
976 fibril_mutex_lock(&e1000_data->rx_lock);
977
978 if (vlan_mask) {
979 /*
980 * Disable receiving, so that packet matching
981 * partially written VLAN is not received.
982 */
983 bool rx_enabled = e1000_is_rx_enabled(e1000_data);
984 if (rx_enabled)
985 e1000_disable_rx(e1000_data);
986
987 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
988 uint32_t bitmap_part =
989 ((uint32_t) vlan_mask->bitmap[i]) |
990 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
991 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
992 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
993 E1000_REG_WRITE(e1000_data, E1000_VFTA_ARRAY(i / 4), bitmap_part);
994 }
995
996 e1000_enable_vlan_filter(e1000_data);
997 if (rx_enabled)
998 e1000_enable_rx(e1000_data);
999 } else
1000 e1000_disable_vlan_filter(e1000_data);
1001
1002 fibril_mutex_unlock(&e1000_data->rx_lock);
1003}
1004
1005/** Set VLAN mask
1006 *
1007 * @param device E1000 device
1008 * @param tag VLAN tag
1009 *
1010 * @return EOK
1011 * @return ENOTSUP
1012 *
1013 */
1014static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
1015 bool strip)
1016{
1017 /* VLAN CFI bit cannot be set */
1018 if (tag & VLANTAG_CFI)
1019 return ENOTSUP;
1020
1021 /*
1022 * CTRL.VME is neccessary for both strip and add
1023 * but CTRL.VME means stripping tags on receive.
1024 */
1025 if (!strip && add)
1026 return ENOTSUP;
1027
1028 e1000_t *e1000_data = DRIVER_DATA_DEV(device);
1029
1030 e1000_data->vlan_tag = tag;
1031 e1000_data->vlan_tag_add = add;
1032
1033 fibril_mutex_lock(&e1000_data->ctrl_lock);
1034
1035 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
1036 if (strip)
1037 ctrl |= CTRL_VME;
1038 else
1039 ctrl &= ~CTRL_VME;
1040
1041 E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl);
1042
1043 fibril_mutex_unlock(&e1000_data->ctrl_lock);
1044 return EOK;
1045}
1046
1047/** Fill receive descriptor with new empty packet
1048 *
1049 * Store packet in e1000_data->rx_ring_packets
1050 *
1051 * @param nic_data NIC data stricture
1052 * @param offset Receive descriptor offset
1053 *
1054 */
1055static void e1000_fill_new_rx_descriptor(nic_t *nic_data, unsigned int offset)
1056{
1057 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1058 packet_t *packet = nic_alloc_packet(nic_data, E1000_MAX_RECEIVE_PACKET_SIZE);
1059
1060 assert(packet);
1061
1062 *(e1000_data->rx_ring_packets + offset) = packet;
1063 e1000_rx_descriptor_t * rx_descriptor = (e1000_rx_descriptor_t *)
1064 (e1000_data->rx_ring.virt +
1065 offset * sizeof(e1000_rx_descriptor_t));
1066
1067 void *phys_addr = nic_dma_lock_packet(packet);
1068
1069 if (phys_addr) {
1070 rx_descriptor->phys_addr =
1071 PTR_TO_U64(phys_addr + packet->data_start);
1072 } else
1073 rx_descriptor->phys_addr = 0;
1074
1075 rx_descriptor->length = 0;
1076 rx_descriptor->checksum = 0;
1077 rx_descriptor->status = 0;
1078 rx_descriptor->errors = 0;
1079 rx_descriptor->special = 0;
1080}
1081
1082/** Clear receive descriptor
1083 *
1084 * @param e1000_data E1000 data
1085 * @param offset Receive descriptor offset
1086 *
1087 */
1088static void e1000_clear_rx_descriptor(e1000_t *e1000_data, unsigned int offset)
1089{
1090 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1091 (e1000_data->rx_ring.virt +
1092 offset * sizeof(e1000_rx_descriptor_t));
1093
1094 rx_descriptor->length = 0;
1095 rx_descriptor->checksum = 0;
1096 rx_descriptor->status = 0;
1097 rx_descriptor->errors = 0;
1098 rx_descriptor->special = 0;
1099}
1100
1101/** Clear receive descriptor
1102 *
1103 * @param nic_data NIC data
1104 * @param offset Receive descriptor offset
1105 *
1106 */
1107static void e1000_clear_tx_descriptor(nic_t *nic_data, unsigned int offset)
1108{
1109 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1110
1111 e1000_tx_descriptor_t * tx_descriptor = (e1000_tx_descriptor_t *)
1112 (e1000_data->tx_ring.virt +
1113 offset * sizeof(e1000_tx_descriptor_t));
1114
1115 if (tx_descriptor->length) {
1116 packet_t * old_packet = *(e1000_data->tx_ring_packets + offset);
1117 if (old_packet)
1118 nic_release_packet(nic_data, old_packet);
1119 }
1120
1121 tx_descriptor->phys_addr = 0;
1122 tx_descriptor->length = 0;
1123 tx_descriptor->checksum_offset = 0;
1124 tx_descriptor->command = 0;
1125 tx_descriptor->status = 0;
1126 tx_descriptor->checksum_start_field = 0;
1127 tx_descriptor->special = 0;
1128}
1129
1130/** Increment tail pointer for receive or transmit ring
1131 *
1132 * @param tail Old Tail
1133 * @param descriptors_count Ring length
1134 *
1135 * @return New tail
1136 *
1137 */
1138static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1139{
1140 if (tail + 1 == descriptors_count)
1141 return 0;
1142 else
1143 return tail + 1;
1144}
1145
1146/** Receive packets
1147 *
1148 * @param nic_data NIC data
1149 *
1150 */
1151static void e1000_receive_packets(nic_t *nic_data)
1152{
1153 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1154
1155 fibril_mutex_lock(&e1000_data->rx_lock);
1156
1157 uint32_t *tail_addr = E1000_REG_ADDR(e1000_data, E1000_RDT);
1158 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT);
1159
1160 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1161 (e1000_data->rx_ring.virt +
1162 next_tail * sizeof(e1000_rx_descriptor_t));
1163
1164 while (rx_descriptor->status & 0x01) {
1165 uint32_t packet_size = rx_descriptor->length - E1000_CRC_SIZE;
1166
1167 packet_t *packet = *(e1000_data->rx_ring_packets + next_tail);
1168 packet_suffix(packet, packet_size);
1169
1170 nic_dma_unlock_packet(packet);
1171 nic_received_packet(nic_data, packet);
1172
1173 e1000_fill_new_rx_descriptor(nic_data, next_tail);
1174
1175 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT);
1176 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT);
1177
1178 rx_descriptor = (e1000_rx_descriptor_t *)
1179 (e1000_data->rx_ring.virt +
1180 next_tail * sizeof(e1000_rx_descriptor_t));
1181 }
1182
1183 fibril_mutex_unlock(&e1000_data->rx_lock);
1184}
1185
1186/** Enable E1000 interupts
1187 *
1188 * @param e1000_data E1000 data structure
1189 *
1190 */
1191static void e1000_enable_interrupts(e1000_t *e1000_data)
1192{
1193 E1000_REG_WRITE(e1000_data, E1000_IMS, ICR_RXT0);
1194}
1195
1196/** Disable E1000 interupts
1197 *
1198 * @param e1000_data E1000 data structure
1199 *
1200 */
1201static void e1000_disable_interrupts(e1000_t *e1000_data)
1202{
1203 E1000_REG_WRITE(e1000_data, E1000_IMS, 0);
1204}
1205
1206/** Interrupt handler implementation
1207 *
1208 * This function is called from e1000_interrupt_handler()
1209 * and e1000_poll()
1210 *
1211 * @param nic_data NIC data
1212 * @param icr ICR register value
1213 *
1214 */
1215static void e1000_interrupt_handler_impl(nic_t *nic_data, uint32_t icr)
1216{
1217 if (icr & ICR_RXT0)
1218 e1000_receive_packets(nic_data);
1219}
1220
1221/** Handle device interrupt
1222 *
1223 * @param dev E1000 device
1224 * @param iid IPC call id
1225 * @param icall IPC call structure
1226 *
1227 */
1228static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1229 ipc_call_t *icall)
1230{
1231 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1232 nic_t *nic_data = NIC_DATA_DEV(dev);
1233 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1234
1235 e1000_interrupt_handler_impl(nic_data, icr);
1236 e1000_enable_interrupts(e1000_data);
1237}
1238
1239/** Register interrupt handler for the card in the system
1240 *
1241 * Note: The global irq_reg_mutex is locked because of work with global
1242 * structure.
1243 *
1244 * @param nic_data Driver data
1245 *
1246 * @return EOK if the handler was registered
1247 * @return Negative error code otherwise
1248 *
1249 */
1250inline static int e1000_register_int_handler(nic_t *nic_data)
1251{
1252 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1253
1254 /* Lock the mutex in whole driver while working with global structure */
1255 fibril_mutex_lock(&irq_reg_mutex);
1256
1257 // FIXME: This is not supported in mainline
1258 e1000_irq_code.cmds[0].addr =
1259 0xffff800000000000 + e1000_data->phys_reg_base + E1000_ICR;
1260 e1000_irq_code.cmds[2].addr =
1261 0xffff800000000000 + e1000_data->phys_reg_base + E1000_IMC;
1262
1263 int rc = register_interrupt_handler(nic_get_ddf_dev(nic_data),
1264 e1000_data->irq, e1000_interrupt_handler, &e1000_irq_code);
1265
1266 fibril_mutex_unlock(&irq_reg_mutex);
1267 return rc;
1268}
1269
1270/** Force receiving all packets in the receive buffer
1271 *
1272 * @param nic_data NIC data
1273 *
1274 */
1275static void e1000_poll(nic_t *nic_data)
1276{
1277 assert(nic_data);
1278
1279 e1000_t *e1000_data = nic_get_specific(nic_data);
1280 assert(e1000_data);
1281
1282 uint32_t icr = E1000_REG_READ(e1000_data, E1000_ICR);
1283 e1000_interrupt_handler_impl(nic_data, icr);
1284}
1285
1286/** Calculates ITR register interrupt from timeval structure
1287 *
1288 * @param period Period
1289 *
1290 */
1291static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1292{
1293 // TODO: use also tv_sec
1294 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1295}
1296
1297/** Set polling mode
1298 *
1299 * @param device Device to set
1300 * @param mode Mode to set
1301 * @param period Period for NIC_POLL_PERIODIC
1302 *
1303 * @return EOK if succeed
1304 * @return ENOTSUP if the mode is not supported
1305 *
1306 */
1307static int e1000_poll_mode_change(nic_t *nic_data, nic_poll_mode_t mode,
1308 const struct timeval *period)
1309{
1310 assert(nic_data);
1311
1312 e1000_t *e1000_data = nic_get_specific(nic_data);
1313 assert(e1000_data);
1314
1315 switch (mode) {
1316 case NIC_POLL_IMMEDIATE:
1317 E1000_REG_WRITE(e1000_data, E1000_ITR, 0);
1318 e1000_enable_interrupts(e1000_data);
1319 break;
1320 case NIC_POLL_ON_DEMAND:
1321 e1000_disable_interrupts(e1000_data);
1322 break;
1323 case NIC_POLL_PERIODIC:
1324 assert(period);
1325 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1326 E1000_REG_WRITE(e1000_data, E1000_ITR, (uint32_t) itr_interval);
1327 e1000_enable_interrupts(e1000_data);
1328 break;
1329 default:
1330 return ENOTSUP;
1331 }
1332
1333 return EOK;
1334}
1335
1336/** Initialize receive registers
1337 *
1338 * @param e1000_data E1000 data structure
1339 *
1340 */
1341static void e1000_initialize_rx_registers(e1000_t * e1000_data)
1342{
1343 E1000_REG_WRITE(e1000_data, E1000_RDLEN, E1000_RX_PACKETS_COUNT * 16);
1344 E1000_REG_WRITE(e1000_data, E1000_RDH, 0);
1345
1346 /* It is not posible to let HW use all descriptors */
1347 E1000_REG_WRITE(e1000_data, E1000_RDT, E1000_RX_PACKETS_COUNT - 1);
1348
1349 /* Set Broadcast Enable Bit */
1350 E1000_REG_WRITE(e1000_data, E1000_RCTL, RCTL_BAM);
1351}
1352
1353/** Initialize receive structure
1354 *
1355 * @param nic_data NIC data
1356 *
1357 * @return EOK if succeed
1358 * @return Negative error code otherwise
1359 *
1360 */
1361static int e1000_initialize_rx_structure(nic_t *nic_data)
1362{
1363 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1364 fibril_mutex_lock(&e1000_data->rx_lock);
1365
1366 int rc = dmamem_map(&e1000_data->rx_ring,
1367 SIZE2PAGES(E1000_RX_PACKETS_COUNT * sizeof(e1000_rx_descriptor_t)),
1368 AS_AREA_READ | AS_AREA_WRITE, 0);
1369 if (rc != EOK)
1370 return rc;
1371
1372 E1000_REG_WRITE(e1000_data, E1000_RDBAH,
1373 (uint32_t) (PTR_TO_U64(e1000_data->rx_ring.phys) >> 32));
1374 E1000_REG_WRITE(e1000_data, E1000_RDBAL,
1375 (uint32_t) PTR_TO_U64(e1000_data->rx_ring.phys));
1376
1377 e1000_data->rx_ring_packets =
1378 malloc(E1000_RX_PACKETS_COUNT * sizeof(packet_t *));
1379 // FIXME: Check return value
1380
1381 /* Write descriptor */
1382 for (unsigned int offset = 0;
1383 offset < E1000_RX_PACKETS_COUNT;
1384 offset++)
1385 e1000_fill_new_rx_descriptor(nic_data, offset);
1386
1387 e1000_initialize_rx_registers(e1000_data);
1388
1389 fibril_mutex_unlock(&e1000_data->rx_lock);
1390 return EOK;
1391}
1392
1393/** Uninitialize receive structure
1394 *
1395 * @param nic_data NIC data
1396 *
1397 */
1398static void e1000_uninitialize_rx_structure(nic_t *nic_data)
1399{
1400 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1401
1402 /* Write descriptor */
1403 for (unsigned int offset = 0;
1404 offset < E1000_RX_PACKETS_COUNT;
1405 offset++) {
1406 packet_t *packet = *(e1000_data->rx_ring_packets + offset);
1407 nic_dma_unlock_packet(packet);
1408 nic_release_packet(nic_data, packet);
1409 }
1410
1411 free(e1000_data->rx_ring_packets);
1412 dmamem_unmap(&e1000_data->rx_ring);
1413}
1414
1415/** Clear receive descriptor ring
1416 *
1417 * @param e1000_data E1000 data
1418 *
1419 */
1420static void e1000_clear_rx_ring(e1000_t * e1000_data)
1421{
1422 /* Write descriptor */
1423 for (unsigned int offset = 0;
1424 offset < E1000_RX_PACKETS_COUNT;
1425 offset++)
1426 e1000_clear_rx_descriptor(e1000_data, offset);
1427}
1428
1429/** Initialize filters
1430 *
1431 * @param e1000_data E1000 data
1432 *
1433 */
1434static void e1000_initialize_filters(e1000_t *e1000_data)
1435{
1436 /* Initialize address filter */
1437 e1000_data->unicast_ra_count = 0;
1438 e1000_data->multicast_ra_count = 0;
1439 e1000_clear_unicast_receive_addresses(e1000_data);
1440}
1441
1442/** Initialize VLAN
1443 *
1444 * @param e1000_data E1000 data
1445 *
1446 */
1447static void e1000_initialize_vlan(e1000_t *e1000_data)
1448{
1449 e1000_data->vlan_tag_add = false;
1450}
1451
1452/** Fill MAC address from EEPROM to RA[0] register
1453 *
1454 * @param e1000_data E1000 data
1455 *
1456 */
1457static void e1000_fill_mac_from_eeprom(e1000_t *e1000_data)
1458{
1459 /* MAC address from eeprom to RA[0] */
1460 nic_address_t address;
1461 e1000_eeprom_get_address(e1000_data, &address);
1462 e1000_write_receive_address(e1000_data, 0, &address, true);
1463}
1464
1465/** Initialize other registers
1466 *
1467 * @param dev E1000 data.
1468 *
1469 * @return EOK if succeed
1470 * @return Negative error code otherwise
1471 *
1472 */
1473static void e1000_initialize_registers(e1000_t *e1000_data)
1474{
1475 E1000_REG_WRITE(e1000_data, E1000_ITR,
1476 e1000_calculate_itr_interval_from_usecs(
1477 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1478 E1000_REG_WRITE(e1000_data, E1000_FCAH, 0);
1479 E1000_REG_WRITE(e1000_data, E1000_FCAL, 0);
1480 E1000_REG_WRITE(e1000_data, E1000_FCT, 0);
1481 E1000_REG_WRITE(e1000_data, E1000_FCTTV, 0);
1482 E1000_REG_WRITE(e1000_data, E1000_VET, VET_VALUE);
1483 E1000_REG_WRITE(e1000_data, E1000_CTRL, CTRL_ASDE);
1484}
1485
1486/** Initialize transmit registers
1487 *
1488 * @param e1000_data E1000 data.
1489 *
1490 */
1491static void e1000_initialize_tx_registers(e1000_t *e1000_data)
1492{
1493 E1000_REG_WRITE(e1000_data, E1000_TDLEN, E1000_TX_PACKETS_COUNT * 16);
1494 E1000_REG_WRITE(e1000_data, E1000_TDH, 0);
1495 E1000_REG_WRITE(e1000_data, E1000_TDT, 0);
1496
1497 E1000_REG_WRITE(e1000_data, E1000_TIPG,
1498 10 << TIPG_IPGT_SHIFT |
1499 8 << TIPG_IPGR1_SHIFT |
1500 6 << TIPG_IPGR2_SHIFT);
1501
1502 E1000_REG_WRITE(e1000_data, E1000_TCTL,
1503 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1504 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1505 TCTL_PSP /* Pad Short Packets */);
1506}
1507
1508/** Initialize transmit structure
1509 *
1510 * @param e1000_data E1000 data.
1511 *
1512 */
1513static int e1000_initialize_tx_structure(e1000_t *e1000_data)
1514{
1515 fibril_mutex_lock(&e1000_data->tx_lock);
1516
1517 int rc = dmamem_map(&e1000_data->tx_ring,
1518 SIZE2PAGES(E1000_TX_PACKETS_COUNT * sizeof(e1000_tx_descriptor_t)),
1519 AS_AREA_READ | AS_AREA_WRITE, 0);
1520 if (rc != EOK)
1521 return rc;
1522
1523 bzero(e1000_data->tx_ring.virt,
1524 E1000_TX_PACKETS_COUNT * sizeof(e1000_tx_descriptor_t));
1525
1526 E1000_REG_WRITE(e1000_data, E1000_TDBAH,
1527 (uint32_t) (PTR_TO_U64(e1000_data->tx_ring.phys) >> 32));
1528 E1000_REG_WRITE(e1000_data, E1000_TDBAL,
1529 (uint32_t) PTR_TO_U64(e1000_data->tx_ring.phys));
1530
1531 e1000_data->tx_ring_packets =
1532 malloc(E1000_TX_PACKETS_COUNT * sizeof(packet_t *));
1533 // FIXME: Check return value
1534
1535 e1000_initialize_tx_registers(e1000_data);
1536
1537 fibril_mutex_unlock(&e1000_data->tx_lock);
1538 return EOK;
1539}
1540
1541/** Uninitialize transmit structure
1542 *
1543 * @param nic_data NIC data
1544 *
1545 */
1546static void e1000_uninitialize_tx_structure(e1000_t *e1000_data)
1547{
1548 free(e1000_data->tx_ring_packets);
1549 dmamem_unmap(&e1000_data->tx_ring);
1550}
1551
1552/** Clear transmit descriptor ring
1553 *
1554 * @param nic_data NIC data
1555 *
1556 */
1557static void e1000_clear_tx_ring(nic_t *nic_data)
1558{
1559 /* Write descriptor */
1560 for (unsigned int offset = 0;
1561 offset < E1000_TX_PACKETS_COUNT;
1562 offset++)
1563 e1000_clear_tx_descriptor(nic_data, offset);
1564}
1565
1566/** Enable transmit
1567 *
1568 * @param e1000_data E1000 data
1569 *
1570 */
1571static void e1000_enable_tx(e1000_t *e1000_data)
1572{
1573 /* Set Transmit Enable Bit */
1574 E1000_REG_WRITE(e1000_data, E1000_TCTL,
1575 E1000_REG_READ(e1000_data, E1000_TCTL) | (TCTL_EN));
1576}
1577
1578/** Disable transmit
1579 *
1580 * @param e1000_data E1000 data
1581 *
1582 */
1583static void e1000_disable_tx(e1000_t *e1000_data)
1584{
1585 /* Clear Transmit Enable Bit */
1586 E1000_REG_WRITE(e1000_data, E1000_TCTL,
1587 E1000_REG_READ(e1000_data, E1000_TCTL) & ~(TCTL_EN));
1588}
1589
1590/** Reset E1000 device
1591 *
1592 * @param e1000_data The E1000 data
1593 *
1594 */
1595static int e1000_reset(nic_t *nic_data)
1596{
1597 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1598
1599 E1000_REG_WRITE(e1000_data, E1000_CTRL, CTRL_RST);
1600
1601 /* Wait for the reset */
1602 usleep(20);
1603
1604 /* check if RST_BIT cleared */
1605 if (E1000_REG_READ(e1000_data, E1000_CTRL) & (CTRL_RST))
1606 return EINVAL;
1607
1608 e1000_initialize_registers(e1000_data);
1609 e1000_initialize_rx_registers(e1000_data);
1610 e1000_initialize_tx_registers(e1000_data);
1611 e1000_fill_mac_from_eeprom(e1000_data);
1612 e1000_initialize_filters(e1000_data);
1613 e1000_initialize_vlan(e1000_data);
1614
1615 return EOK;
1616}
1617
1618/** Activate the device to receive and transmit packets
1619 *
1620 * @param nic_data NIC driver data
1621 *
1622 * @return EOK if activated successfully
1623 * @return Error code otherwise
1624 *
1625 */
1626static int e1000_on_activating(nic_t *nic_data)
1627{
1628 assert(nic_data);
1629
1630 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1631
1632 fibril_mutex_lock(&e1000_data->rx_lock);
1633 fibril_mutex_lock(&e1000_data->tx_lock);
1634 fibril_mutex_lock(&e1000_data->ctrl_lock);
1635
1636 e1000_enable_interrupts(e1000_data);
1637
1638 nic_enable_interrupt(nic_data, e1000_data->irq);
1639
1640 e1000_clear_rx_ring(e1000_data);
1641 e1000_enable_rx(e1000_data);
1642
1643 e1000_clear_tx_ring(nic_data);
1644 e1000_enable_tx(e1000_data);
1645
1646 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
1647 ctrl |= CTRL_SLU;
1648 E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl);
1649
1650 fibril_mutex_unlock(&e1000_data->ctrl_lock);
1651 fibril_mutex_unlock(&e1000_data->tx_lock);
1652 fibril_mutex_unlock(&e1000_data->rx_lock);
1653
1654 return EOK;
1655}
1656
1657/** Callback for NIC_STATE_DOWN change
1658 *
1659 * @param nic_data NIC driver data
1660 *
1661 * @return EOK if succeed
1662 * @return Error code otherwise
1663 *
1664 */
1665static int e1000_on_down_unlocked(nic_t *nic_data)
1666{
1667 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1668
1669 uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL);
1670 ctrl &= ~CTRL_SLU;
1671 E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl);
1672
1673 e1000_disable_tx(e1000_data);
1674 e1000_disable_rx(e1000_data);
1675
1676 nic_disable_interrupt(nic_data, e1000_data->irq);
1677 e1000_disable_interrupts(e1000_data);
1678
1679 /*
1680 * Wait for the for the end of all data
1681 * transfers to descriptors.
1682 */
1683 usleep(100);
1684
1685 return EOK;
1686}
1687
1688/** Callback for NIC_STATE_DOWN change
1689 *
1690 * @param nic_data NIC driver data
1691 *
1692 * @return EOK if succeed
1693 * @return Error code otherwise
1694 *
1695 */
1696static int e1000_on_down(nic_t *nic_data)
1697{
1698 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1699
1700 fibril_mutex_lock(&e1000_data->rx_lock);
1701 fibril_mutex_lock(&e1000_data->tx_lock);
1702 fibril_mutex_lock(&e1000_data->ctrl_lock);
1703
1704 int rc = e1000_on_down_unlocked(nic_data);
1705
1706 fibril_mutex_unlock(&e1000_data->ctrl_lock);
1707 fibril_mutex_unlock(&e1000_data->tx_lock);
1708 fibril_mutex_unlock(&e1000_data->rx_lock);
1709
1710 return rc;
1711}
1712
1713/** Callback for NIC_STATE_STOPPED change
1714 *
1715 * @param nic_data NIC driver data
1716 *
1717 * @return EOK if succeed
1718 * @return Error code otherwise
1719 *
1720 */
1721static int e1000_on_stopping(nic_t *nic_data)
1722{
1723 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1724
1725 fibril_mutex_lock(&e1000_data->rx_lock);
1726 fibril_mutex_lock(&e1000_data->tx_lock);
1727 fibril_mutex_lock(&e1000_data->ctrl_lock);
1728
1729 int rc = e1000_on_down_unlocked(nic_data);
1730 if (rc == EOK)
1731 rc = e1000_reset(nic_data);
1732
1733 fibril_mutex_unlock(&e1000_data->ctrl_lock);
1734 fibril_mutex_unlock(&e1000_data->tx_lock);
1735 fibril_mutex_unlock(&e1000_data->rx_lock);
1736
1737 return rc;
1738}
1739
1740/** Create driver data structure
1741 *
1742 * @return Intialized device data structure or NULL
1743 *
1744 */
1745static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1746{
1747 assert(dev);
1748 assert(!dev->driver_data);
1749
1750 nic_t *nic_data = nic_create_and_bind(dev);
1751 if (!nic_data)
1752 return NULL;
1753
1754 e1000_t *e1000_data = malloc(sizeof(e1000_t));
1755 if (!e1000_data) {
1756 nic_unbind_and_destroy(dev);
1757 return NULL;
1758 }
1759
1760 bzero(e1000_data, sizeof(e1000_t));
1761
1762 nic_set_specific(nic_data, e1000_data);
1763 nic_set_write_packet_handler(nic_data, e1000_write_packet);
1764 nic_set_state_change_handlers(nic_data, e1000_on_activating,
1765 e1000_on_down, e1000_on_stopping);
1766 nic_set_filtering_change_handlers(nic_data,
1767 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1768 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1769 nic_set_poll_handlers(nic_data, e1000_poll_mode_change, e1000_poll);
1770
1771 fibril_mutex_initialize(&e1000_data->ctrl_lock);
1772 fibril_mutex_initialize(&e1000_data->rx_lock);
1773 fibril_mutex_initialize(&e1000_data->tx_lock);
1774 fibril_mutex_initialize(&e1000_data->eeprom_lock);
1775
1776 return e1000_data;
1777}
1778
1779/** Delete driver data structure
1780 *
1781 * @param data E1000 device data structure
1782 *
1783 */
1784inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1785{
1786 assert(dev);
1787
1788 if (dev->driver_data != NULL)
1789 nic_unbind_and_destroy(dev);
1790}
1791
1792/** Clean up the E1000 device structure.
1793 *
1794 * @param dev Device structure.
1795 *
1796 */
1797static void e1000_dev_cleanup(ddf_dev_t *dev)
1798{
1799 assert(dev);
1800
1801 e1000_delete_dev_data(dev);
1802
1803 if (dev->parent_sess != NULL) {
1804 async_hangup(dev->parent_sess);
1805 dev->parent_sess = NULL;
1806 }
1807}
1808
1809/** Fill the irq and io_addr part of device data structure
1810 *
1811 * The hw_resources must be obtained before calling this function
1812 *
1813 * @param dev Device structure
1814 * @param hw_resources Hardware resources obtained from the parent device
1815 *
1816 * @return EOK if succeed
1817 * @return Negative error code otherwise
1818 *
1819 */
1820static int e1000_fill_resource_info(ddf_dev_t *dev,
1821 const hw_res_list_parsed_t *hw_resources)
1822{
1823 assert(dev != NULL);
1824 assert(hw_resources != NULL);
1825 assert(dev->driver_data != NULL);
1826
1827 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
1828
1829 if (hw_resources->irqs.count != 1)
1830 return EINVAL;
1831
1832 e1000_data->irq = hw_resources->irqs.irqs[0];
1833 e1000_data->phys_reg_base =
1834 MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
1835
1836 return EOK;
1837}
1838
1839/** Obtain information about hardware resources of the device
1840 *
1841 * The device must be connected to the parent
1842 *
1843 * @param dev Device structure
1844 *
1845 * @return EOK if succeed
1846 * @return Negative error code otherwise
1847 *
1848 */
1849static int e1000_get_resource_info(ddf_dev_t *dev)
1850{
1851 assert(dev != NULL);
1852 assert(NIC_DATA_DEV(dev) != NULL);
1853
1854 hw_res_list_parsed_t hw_res_parsed;
1855 hw_res_list_parsed_init(&hw_res_parsed);
1856
1857 /* Get hw resources form parent driver */
1858 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1859 if (rc != EOK)
1860 return rc;
1861
1862 /* Fill resources information to the device */
1863 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1864 hw_res_list_parsed_clean(&hw_res_parsed);
1865
1866 return rc;
1867}
1868
1869/** Initialize the E1000 device structure
1870 *
1871 * @param dev Device information
1872 *
1873 * @return EOK if succeed
1874 * @return Negative error code otherwise
1875 *
1876 */
1877static int e1000_device_initialize(ddf_dev_t *dev)
1878{
1879 /* Allocate driver data for the device. */
1880 e1000_t *e1000_data = e1000_create_dev_data(dev);
1881 if (e1000_data == NULL)
1882 return ENOMEM;
1883
1884 /* Obtain and fill hardware resources info */
1885 int rc = e1000_get_resource_info(dev);
1886 if (rc != EOK) {
1887 e1000_dev_cleanup(dev);
1888 return rc;
1889 }
1890
1891 rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
1892 &e1000_data->device_id);
1893 if (rc != EOK) {
1894 e1000_dev_cleanup(dev);
1895 return rc;
1896 }
1897
1898 return EOK;
1899}
1900
1901/** Enable the I/O ports of the device.
1902 *
1903 * @param dev E1000 device.
1904 *
1905 * @return EOK if successed
1906 * @return Negative error code otherwise
1907 *
1908 */
1909static int e1000_pio_enable(ddf_dev_t *dev)
1910{
1911 e1000_t *e1000_data = DRIVER_DATA_DEV(dev);
1912
1913 int rc = pio_enable(e1000_data->phys_reg_base, 8 * PAGE_SIZE,
1914 &e1000_data->virt_reg_base);
1915 if (rc != EOK)
1916 return EADDRNOTAVAIL;
1917
1918 return EOK;
1919}
1920
1921/** Probe and initialize the newly added device.
1922 *
1923 * @param dev E1000 device.
1924 *
1925 */
1926int e1000_dev_add(ddf_dev_t *dev)
1927{
1928 assert(dev);
1929
1930 /* Initialize device structure for E1000 */
1931 int rc = e1000_device_initialize(dev);
1932 if (rc != EOK)
1933 return rc;
1934
1935 /* Device initialization */
1936 nic_t *nic_data = dev->driver_data;
1937 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
1938
1939 /* Map registers */
1940 rc = e1000_pio_enable(dev);
1941 if (rc != EOK)
1942 goto err_destroy;
1943
1944 e1000_initialize_registers(e1000_data);
1945 rc = e1000_initialize_tx_structure(e1000_data);
1946 if (rc != EOK)
1947 goto err_pio;
1948
1949 fibril_mutex_lock(&e1000_data->rx_lock);
1950
1951 e1000_fill_mac_from_eeprom(e1000_data);
1952 e1000_initialize_filters(e1000_data);
1953
1954 fibril_mutex_unlock(&e1000_data->rx_lock);
1955
1956 e1000_initialize_vlan(e1000_data);
1957
1958 rc = nic_register_as_ddf_fun(nic_data, &e1000_dev_ops);
1959 if (rc != EOK)
1960 goto err_tx_structure;
1961
1962 rc = e1000_register_int_handler(nic_data);
1963 if (rc != EOK)
1964 goto err_tx_structure;
1965
1966 rc = nic_connect_to_services(nic_data);
1967 if (rc != EOK)
1968 goto err_irq;
1969
1970 rc = e1000_initialize_rx_structure(nic_data);
1971 if (rc != EOK)
1972 goto err_irq;
1973
1974 nic_address_t e1000_address;
1975 e1000_get_address(e1000_data, &e1000_address);
1976 rc = nic_report_address(nic_data, &e1000_address);
1977 if (rc != EOK)
1978 goto err_rx_structure;
1979
1980 struct timeval period;
1981 period.tv_sec = 0;
1982 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
1983 rc = nic_report_poll_mode(nic_data, NIC_POLL_PERIODIC, &period);
1984 if (rc != EOK)
1985 goto err_rx_structure;
1986
1987 return EOK;
1988
1989err_rx_structure:
1990 e1000_uninitialize_rx_structure(nic_data);
1991err_irq:
1992 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
1993err_tx_structure:
1994 e1000_uninitialize_tx_structure(e1000_data);
1995err_pio:
1996 // TODO: e1000_pio_disable(dev);
1997err_destroy:
1998 e1000_dev_cleanup(dev);
1999 return rc;
2000}
2001
2002/** Read 16-bit value from EEPROM of E1000 adapter
2003 *
2004 * Read using the EERD register.
2005 *
2006 * @param device E1000 device
2007 * @param eeprom_address 8-bit EEPROM address
2008 *
2009 * @return 16-bit value from EEPROM
2010 *
2011 */
2012static uint16_t e1000_eeprom_read(e1000_t *e1000_data, uint8_t eeprom_address)
2013{
2014 fibril_mutex_lock(&e1000_data->eeprom_lock);
2015
2016 uint32_t eerd_done;
2017 uint32_t eerd_address_offset;
2018
2019 switch (e1000_data->device_id) {
2020 case 0x107c:
2021 case 0x1013:
2022 case 0x1018:
2023 case 0x1019:
2024 case 0x101A:
2025 case 0x1076:
2026 case 0x1077:
2027 case 0x1078:
2028 case 0x10b9:
2029 /* 82541xx and 82547GI/EI */
2030 eerd_done = EERD_DONE_82541XX_82547GI_EI;
2031 eerd_address_offset = EERD_ADDRESS_OFFSET_82541XX_82547GI_EI;
2032 break;
2033 default:
2034 eerd_done = EERD_DONE;
2035 eerd_address_offset = EERD_ADDRESS_OFFSET;
2036 break;
2037 }
2038
2039 /* Write address and START bit to EERD register */
2040 uint32_t write_data = EERD_START |
2041 (((uint32_t) eeprom_address) << eerd_address_offset);
2042 E1000_REG_WRITE(e1000_data, E1000_EERD, write_data);
2043
2044 uint32_t eerd = E1000_REG_READ(e1000_data, E1000_EERD);
2045 while ((eerd & eerd_done) == 0) {
2046 usleep(1);
2047 eerd = E1000_REG_READ(e1000_data, E1000_EERD);
2048 }
2049
2050 fibril_mutex_unlock(&e1000_data->eeprom_lock);
2051
2052 return (uint16_t) (eerd >> EERD_DATA_OFFSET);
2053}
2054
2055/** Get MAC address of the E1000 adapter
2056 *
2057 * @param device E1000 device
2058 * @param address Place to store the address
2059 * @param max_len Maximal addresss length to store
2060 *
2061 * @return EOK if succeed
2062 * @return Negative error code otherwise
2063 *
2064 */
2065static int e1000_get_address(e1000_t *e1000_data, nic_address_t *address)
2066{
2067 fibril_mutex_lock(&e1000_data->rx_lock);
2068
2069 uint8_t *mac0_dest = (uint8_t *) address->address;
2070 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2071 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2072 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2073 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2074 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2075
2076 uint32_t rah = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(0));
2077 uint32_t ral = E1000_REG_READ(e1000_data, E1000_RAL_ARRAY(0));
2078
2079 *mac0_dest = (uint8_t) ral;
2080 *mac1_dest = (uint8_t) (ral >> 8);
2081 *mac2_dest = (uint8_t) (ral >> 16);
2082 *mac3_dest = (uint8_t) (ral >> 24);
2083 *mac4_dest = (uint8_t) rah;
2084 *mac5_dest = (uint8_t) (rah >> 8);
2085
2086 fibril_mutex_unlock(&e1000_data->rx_lock);
2087 return EOK;
2088};
2089
2090/** Set card MAC address
2091 *
2092 * @param device E1000 device
2093 * @param address Address
2094 *
2095 * @return EOK if succeed
2096 * @return Negative error code otherwise
2097 */
2098static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
2099{
2100 nic_t *nic_data = NIC_DATA_DEV(dev);
2101 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
2102
2103 fibril_mutex_lock(&e1000_data->rx_lock);
2104 fibril_mutex_lock(&e1000_data->tx_lock);
2105
2106 int rc = nic_report_address(nic_data, addr);
2107 if (rc == EOK)
2108 e1000_write_receive_address(e1000_data, 0, addr, false);
2109
2110 fibril_mutex_unlock(&e1000_data->tx_lock);
2111 fibril_mutex_unlock(&e1000_data->rx_lock);
2112
2113 return rc;
2114}
2115
2116static void e1000_eeprom_get_address(e1000_t *e1000_data,
2117 nic_address_t *address)
2118{
2119 uint16_t *mac0_dest = (uint16_t *) address->address;
2120 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2121 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2122
2123 *mac0_dest = e1000_eeprom_read(e1000_data, 0);
2124 *mac2_dest = e1000_eeprom_read(e1000_data, 1);
2125 *mac4_dest = e1000_eeprom_read(e1000_data, 2);
2126}
2127
2128/** Send packet
2129 *
2130 * @param nic_data NIC driver data structure
2131 * @param packet Packet to send
2132 *
2133 * @return EOK if succeed
2134 * @return Error code in the case of error
2135 *
2136 */
2137static void e1000_write_packet(nic_t *nic_data, packet_t *packet)
2138{
2139 assert(nic_data);
2140
2141 e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data);
2142 fibril_mutex_lock(&e1000_data->tx_lock);
2143
2144 uint32_t tdt = E1000_REG_READ(e1000_data, E1000_TDT);
2145 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2146 (e1000_data->tx_ring.virt + tdt * sizeof(e1000_tx_descriptor_t));
2147
2148 bool descriptor_available = false;
2149
2150 /* Descriptor never used */
2151 if (tx_descriptor_addr->length == 0)
2152 descriptor_available = true;
2153
2154 /* Descriptor done */
2155 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD) {
2156 descriptor_available = true;
2157 packet_t *old_packet = *(e1000_data->tx_ring_packets + tdt);
2158 if (old_packet) {
2159 nic_dma_unlock_packet(old_packet);
2160 nic_release_packet(nic_data, old_packet);
2161 }
2162 }
2163
2164 if (!descriptor_available) {
2165 /* Packet lost */
2166 fibril_mutex_unlock(&e1000_data->tx_lock);
2167 return;
2168 }
2169
2170 size_t packet_size = packet_get_data_length(packet);
2171
2172 void *phys_addr = nic_dma_lock_packet(packet);
2173 if (!phys_addr) {
2174 fibril_mutex_unlock(&e1000_data->tx_lock);
2175 return;
2176 }
2177
2178 *(e1000_data->tx_ring_packets + tdt) = packet;
2179
2180 tx_descriptor_addr->phys_addr =
2181 PTR_TO_U64(phys_addr + packet->data_start);
2182 tx_descriptor_addr->length = packet_size;
2183
2184 /*
2185 * Report status to STATUS.DD (descriptor done),
2186 * add ethernet CRC, end of packet.
2187 */
2188 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2189 TXDESCRIPTOR_COMMAND_IFCS |
2190 TXDESCRIPTOR_COMMAND_EOP;
2191
2192 tx_descriptor_addr->checksum_offset = 0;
2193 tx_descriptor_addr->status = 0;
2194 if (e1000_data->vlan_tag_add) {
2195 tx_descriptor_addr->special = e1000_data->vlan_tag;
2196 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2197 } else
2198 tx_descriptor_addr->special = 0;
2199
2200 tx_descriptor_addr->checksum_start_field = 0;
2201
2202 tdt++;
2203 if (tdt == E1000_TX_PACKETS_COUNT)
2204 tdt = 0;
2205
2206 E1000_REG_WRITE(e1000_data, E1000_TDT, tdt);
2207
2208 fibril_mutex_unlock(&e1000_data->tx_lock);
2209}
2210
2211int main(void)
2212{
2213 int rc = nic_driver_init(NAME);
2214 if (rc != EOK)
2215 return rc;
2216
2217 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops, &e1000_nic_iface);
2218 return ddf_driver_main(&e1000_driver);
2219}
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