source: mainline/uspace/drv/nic/e1k/e1k.c@ 8974294

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8974294 was 8974294, checked in by jzr <zarevucky.jiri@…>, 8 years ago

Attempt to fix e1000_link_restart().

My understanding of the driver is limited,
so I'm not positive it's entirely correct,
but it's most definitely more correct now
than it had been before.

Fixes #695, probably.
  • Property mode set to 100644
File size: 56.0 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <thread.h>
41#include <byteorder.h>
42#include <irc.h>
43#include <as.h>
44#include <ddi.h>
45#include <ddf/log.h>
46#include <ddf/interrupt.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include "e1k.h"
52
53#define NAME "e1k"
54
55#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
56
57/* Must be power of 8 */
58#define E1000_RX_FRAME_COUNT 128
59#define E1000_TX_FRAME_COUNT 128
60
61#define E1000_RECEIVE_ADDRESS 16
62
63/** Maximum sending frame size */
64#define E1000_MAX_SEND_FRAME_SIZE 2048
65/** Maximum receiving frame size */
66#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
67
68/** nic_driver_data_t* -> e1000_t* cast */
69#define DRIVER_DATA_NIC(nic) \
70 ((e1000_t *) nic_get_specific(nic))
71
72/** ddf_fun_t * -> nic_driver_data_t* cast */
73#define NIC_DATA_FUN(fun) \
74 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
75
76/** ddf_dev_t * -> nic_driver_data_t* cast */
77#define NIC_DATA_DEV(dev) \
78 ((nic_t *) ddf_dev_data_get(dev))
79
80/** ddf_dev_t * -> e1000_t* cast */
81#define DRIVER_DATA_DEV(dev) \
82 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
83
84/** ddf_fun_t * -> e1000_t* cast */
85#define DRIVER_DATA_FUN(fun) \
86 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
87
88/** Cast pointer to uint64_t
89 *
90 * @param ptr Pointer to cast
91 *
92 * @return The uint64_t pointer representation.
93 *
94 */
95#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
96
97/** Cast the memaddr part to the void*
98 *
99 * @param memaddr The memaddr value
100 *
101 */
102#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
103
104#define E1000_REG_BASE(e1000) \
105 ((e1000)->reg_base_virt)
106
107#define E1000_REG_ADDR(e1000, reg) \
108 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
109
110#define E1000_REG_READ(e1000, reg) \
111 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
112
113#define E1000_REG_WRITE(e1000, reg, value) \
114 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
115
116/** E1000 device data */
117typedef struct {
118 /** Device configuration */
119 e1000_info_t info;
120
121 /** Physical registers base address */
122 void *reg_base_phys;
123 /** Virtual registers base address */
124 void *reg_base_virt;
125
126 /** Physical tx ring address */
127 uintptr_t tx_ring_phys;
128 /** Virtual tx ring address */
129 void *tx_ring_virt;
130
131 /** Ring of TX frames, physical address */
132 uintptr_t *tx_frame_phys;
133 /** Ring of TX frames, virtual address */
134 void **tx_frame_virt;
135
136 /** Physical rx ring address */
137 uintptr_t rx_ring_phys;
138 /** Virtual rx ring address */
139 void *rx_ring_virt;
140
141 /** Ring of RX frames, physical address */
142 uintptr_t *rx_frame_phys;
143 /** Ring of RX frames, virtual address */
144 void **rx_frame_virt;
145
146 /** VLAN tag */
147 uint16_t vlan_tag;
148
149 /** Add VLAN tag to frame */
150 bool vlan_tag_add;
151
152 /** Used unicast Receive Address count */
153 unsigned int unicast_ra_count;
154
155 /** Used milticast Receive addrress count */
156 unsigned int multicast_ra_count;
157
158 /** The irq assigned */
159 int irq;
160
161 /** Lock for CTRL register */
162 fibril_mutex_t ctrl_lock;
163
164 /** Lock for receiver */
165 fibril_mutex_t rx_lock;
166
167 /** Lock for transmitter */
168 fibril_mutex_t tx_lock;
169
170 /** Lock for EEPROM access */
171 fibril_mutex_t eeprom_lock;
172} e1000_t;
173
174/** Global mutex for work with shared irq structure */
175FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
176
177static int e1000_get_address(e1000_t *, nic_address_t *);
178static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
179static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
180
181static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
182static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
183
184static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
185static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
186static int e1000_get_operation_mode(ddf_fun_t *, int *,
187 nic_channel_mode_t *, nic_role_t *);
188static int e1000_set_operation_mode(ddf_fun_t *, int,
189 nic_channel_mode_t, nic_role_t);
190static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
191static int e1000_autoneg_disable(ddf_fun_t *);
192static int e1000_autoneg_restart(ddf_fun_t *);
193
194static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
195
196/** Network interface options for E1000 card driver */
197static nic_iface_t e1000_nic_iface;
198
199/** Network interface options for E1000 card driver */
200static nic_iface_t e1000_nic_iface = {
201 .set_address = &e1000_set_addr,
202 .get_device_info = &e1000_get_device_info,
203 .get_cable_state = &e1000_get_cable_state,
204 .get_operation_mode = &e1000_get_operation_mode,
205 .set_operation_mode = &e1000_set_operation_mode,
206 .autoneg_enable = &e1000_autoneg_enable,
207 .autoneg_disable = &e1000_autoneg_disable,
208 .autoneg_restart = &e1000_autoneg_restart,
209 .vlan_set_tag = &e1000_vlan_set_tag,
210 .defective_get_mode = &e1000_defective_get_mode,
211 .defective_set_mode = &e1000_defective_set_mode,
212};
213
214/** Basic device operations for E1000 driver */
215static ddf_dev_ops_t e1000_dev_ops;
216
217static int e1000_dev_add(ddf_dev_t *);
218
219/** Basic driver operations for E1000 driver */
220static driver_ops_t e1000_driver_ops = {
221 .dev_add = e1000_dev_add
222};
223
224/** Driver structure for E1000 driver */
225static driver_t e1000_driver = {
226 .name = NAME,
227 .driver_ops = &e1000_driver_ops
228};
229
230/* The default implementation callbacks */
231static int e1000_on_activating(nic_t *);
232static int e1000_on_stopping(nic_t *);
233static void e1000_send_frame(nic_t *, void *, size_t);
234
235/** PIO ranges used in the IRQ code. */
236irq_pio_range_t e1000_irq_pio_ranges[] = {
237 {
238 .base = 0,
239 .size = PAGE_SIZE, /* XXX */
240 }
241};
242
243/** Commands to deal with interrupt
244 *
245 */
246irq_cmd_t e1000_irq_commands[] = {
247 {
248 /* Get the interrupt status */
249 .cmd = CMD_PIO_READ_32,
250 .addr = NULL,
251 .dstarg = 2
252 },
253 {
254 .cmd = CMD_PREDICATE,
255 .value = 2,
256 .srcarg = 2
257 },
258 {
259 /* Disable interrupts until interrupt routine is finished */
260 .cmd = CMD_PIO_WRITE_32,
261 .addr = NULL,
262 .value = 0xffffffff
263 },
264 {
265 .cmd = CMD_ACCEPT
266 }
267};
268
269/** Interrupt code definition */
270irq_code_t e1000_irq_code = {
271 .rangecount = sizeof(e1000_irq_pio_ranges) /
272 sizeof(irq_pio_range_t),
273 .ranges = e1000_irq_pio_ranges,
274 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
275 .cmds = e1000_irq_commands
276};
277
278/** Get the device information
279 *
280 * @param dev NIC device
281 * @param info Information to fill
282 *
283 * @return EOK
284 *
285 */
286static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
287{
288 assert(dev);
289 assert(info);
290
291 memset(info, 0, sizeof(nic_device_info_t));
292
293 info->vendor_id = 0x8086;
294 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
295 "Intel Corporation");
296 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
297 "Intel Pro");
298
299 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
300 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
301 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
302
303 return EOK;
304}
305
306/** Check the cable state
307 *
308 * @param[in] dev device
309 * @param[out] state state to fill
310 *
311 * @return EOK
312 *
313 */
314static int e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
315{
316 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
317 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
318 *state = NIC_CS_PLUGGED;
319 else
320 *state = NIC_CS_UNPLUGGED;
321
322 return EOK;
323}
324
325static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
326{
327 return useconds * 4;
328}
329
330/** Get operation mode of the device
331 *
332 */
333static int e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
334 nic_channel_mode_t *duplex, nic_role_t *role)
335{
336 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
337 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
338
339 if (status & STATUS_FD)
340 *duplex = NIC_CM_FULL_DUPLEX;
341 else
342 *duplex = NIC_CM_HALF_DUPLEX;
343
344 uint32_t speed_bits =
345 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
346
347 if (speed_bits == STATUS_SPEED_10)
348 *speed = 10;
349 else if (speed_bits == STATUS_SPEED_100)
350 *speed = 100;
351 else if ((speed_bits == STATUS_SPEED_1000A) ||
352 (speed_bits == STATUS_SPEED_1000B))
353 *speed = 1000;
354
355 *role = NIC_ROLE_UNKNOWN;
356 return EOK;
357}
358
359static void e1000_link_restart(e1000_t *e1000)
360{
361 fibril_mutex_lock(&e1000->ctrl_lock);
362
363 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
364
365 if (ctrl & CTRL_SLU) {
366 ctrl &= ~(CTRL_SLU);
367 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
368 fibril_mutex_unlock(&e1000->ctrl_lock);
369
370 thread_usleep(10);
371
372 fibril_mutex_lock(&e1000->ctrl_lock);
373 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
374 ctrl |= CTRL_SLU;
375 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
376 }
377
378 fibril_mutex_unlock(&e1000->ctrl_lock);
379}
380
381/** Set operation mode of the device
382 *
383 */
384static int e1000_set_operation_mode(ddf_fun_t *fun, int speed,
385 nic_channel_mode_t duplex, nic_role_t role)
386{
387 if ((speed != 10) && (speed != 100) && (speed != 1000))
388 return EINVAL;
389
390 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
391 return EINVAL;
392
393 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
394
395 fibril_mutex_lock(&e1000->ctrl_lock);
396 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
397
398 ctrl |= CTRL_FRCSPD;
399 ctrl |= CTRL_FRCDPLX;
400 ctrl &= ~(CTRL_ASDE);
401
402 if (duplex == NIC_CM_FULL_DUPLEX)
403 ctrl |= CTRL_FD;
404 else
405 ctrl &= ~(CTRL_FD);
406
407 ctrl &= ~(CTRL_SPEED_MASK);
408 if (speed == 1000)
409 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
410 else if (speed == 100)
411 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
412 else
413 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
414
415 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
416
417 fibril_mutex_unlock(&e1000->ctrl_lock);
418
419 e1000_link_restart(e1000);
420
421 return EOK;
422}
423
424/** Enable auto-negotiation
425 *
426 * @param dev Device to update
427 * @param advertisement Ignored on E1000
428 *
429 * @return EOK if advertisement mode set successfully
430 *
431 */
432static int e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
433{
434 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
435
436 fibril_mutex_lock(&e1000->ctrl_lock);
437
438 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
439
440 ctrl &= ~(CTRL_FRCSPD);
441 ctrl &= ~(CTRL_FRCDPLX);
442 ctrl |= CTRL_ASDE;
443
444 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
445
446 fibril_mutex_unlock(&e1000->ctrl_lock);
447
448 e1000_link_restart(e1000);
449
450 return EOK;
451}
452
453/** Disable auto-negotiation
454 *
455 * @param dev Device to update
456 *
457 * @return EOK
458 *
459 */
460static int e1000_autoneg_disable(ddf_fun_t *fun)
461{
462 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
463
464 fibril_mutex_lock(&e1000->ctrl_lock);
465
466 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
467
468 ctrl |= CTRL_FRCSPD;
469 ctrl |= CTRL_FRCDPLX;
470 ctrl &= ~(CTRL_ASDE);
471
472 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
473
474 fibril_mutex_unlock(&e1000->ctrl_lock);
475
476 e1000_link_restart(e1000);
477
478 return EOK;
479}
480
481/** Restart auto-negotiation
482 *
483 * @param dev Device to update
484 *
485 * @return EOK if advertisement mode set successfully
486 *
487 */
488static int e1000_autoneg_restart(ddf_fun_t *dev)
489{
490 return e1000_autoneg_enable(dev, 0);
491}
492
493/** Get state of acceptance of weird frames
494 *
495 * @param device Device to check
496 * @param[out] mode Current mode
497 *
498 */
499static int e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
500{
501 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
502
503 *mode = 0;
504 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
505 if (rctl & RCTL_SBP)
506 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
507
508 return EOK;
509};
510
511/** Set acceptance of weird frames
512 *
513 * @param device Device to update
514 * @param mode Mode to set
515 *
516 * @return ENOTSUP if the mode is not supported
517 * @return EOK of mode was set
518 *
519 */
520static int e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
521{
522 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
523 int rc = EOK;
524
525 fibril_mutex_lock(&e1000->rx_lock);
526
527 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
528 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
529 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
530
531 if (short_mode && bad_mode)
532 rctl |= RCTL_SBP;
533 else if ((!short_mode) && (!bad_mode))
534 rctl &= ~RCTL_SBP;
535 else
536 rc = ENOTSUP;
537
538 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
539
540 fibril_mutex_unlock(&e1000->rx_lock);
541 return rc;
542};
543
544/** Write receive address to RA registr
545 *
546 * @param e1000 E1000 data structure
547 * @param position RA register position
548 * @param address Ethernet address
549 * @param set_av_bit Set the Addtess Valid bit
550 *
551 */
552static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
553 const nic_address_t * address, bool set_av_bit)
554{
555 uint8_t *mac0 = (uint8_t *) address->address;
556 uint8_t *mac1 = (uint8_t *) address->address + 1;
557 uint8_t *mac2 = (uint8_t *) address->address + 2;
558 uint8_t *mac3 = (uint8_t *) address->address + 3;
559 uint8_t *mac4 = (uint8_t *) address->address + 4;
560 uint8_t *mac5 = (uint8_t *) address->address + 5;
561
562 uint32_t rah;
563 uint32_t ral;
564
565 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
566 rah = ((*mac5) << 8) | ((*mac4));
567
568 if (set_av_bit)
569 rah |= RAH_AV;
570 else
571 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
572
573 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
574 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
575}
576
577/** Disable receive address in RA registr
578 *
579 * Clear Address Valid bit
580 *
581 * @param e1000 E1000 data structure
582 * @param position RA register position
583 *
584 */
585static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
586{
587 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
588 rah = rah & ~RAH_AV;
589 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
590}
591
592/** Clear all unicast addresses from RA registers
593 *
594 * @param e1000 E1000 data structure
595 *
596 */
597static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
598{
599 for (unsigned int ra_num = 1;
600 ra_num <= e1000->unicast_ra_count;
601 ra_num++)
602 e1000_disable_receive_address(e1000, ra_num);
603
604 e1000->unicast_ra_count = 0;
605}
606
607/** Clear all multicast addresses from RA registers
608 *
609 * @param e1000 E1000 data structure
610 *
611 */
612static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
613{
614 unsigned int first_multicast_ra_num =
615 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
616
617 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
618 ra_num >= first_multicast_ra_num;
619 ra_num--)
620 e1000_disable_receive_address(e1000, ra_num);
621
622 e1000->multicast_ra_count = 0;
623}
624
625/** Return receive address filter positions count usable for unicast
626 *
627 * @param e1000 E1000 data structure
628 *
629 * @return receive address filter positions count usable for unicast
630 *
631 */
632static unsigned int get_free_unicast_address_count(e1000_t *e1000)
633{
634 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
635}
636
637/** Return receive address filter positions count usable for multicast
638 *
639 * @param e1000 E1000 data structure
640 *
641 * @return receive address filter positions count usable for multicast
642 *
643 */
644static unsigned int get_free_multicast_address_count(e1000_t *e1000)
645{
646 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
647}
648
649/** Write unicast receive addresses to receive address filter registers
650 *
651 * @param e1000 E1000 data structure
652 * @param addr Pointer to address array
653 * @param addr_cnt Address array count
654 *
655 */
656static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
657 const nic_address_t *addr, size_t addr_cnt)
658{
659 assert(addr_cnt <= get_free_unicast_address_count(e1000));
660
661 nic_address_t *addr_iterator = (nic_address_t *) addr;
662
663 /* ra_num = 0 is primary address */
664 for (unsigned int ra_num = 1;
665 ra_num <= addr_cnt;
666 ra_num++) {
667 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
668 addr_iterator++;
669 }
670}
671
672/** Write multicast receive addresses to receive address filter registers
673 *
674 * @param e1000 E1000 data structure
675 * @param addr Pointer to address array
676 * @param addr_cnt Address array count
677 *
678 */
679static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
680 const nic_address_t *addr, size_t addr_cnt)
681{
682 assert(addr_cnt <= get_free_multicast_address_count(e1000));
683
684 nic_address_t *addr_iterator = (nic_address_t *) addr;
685
686 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
687 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
688 ra_num >= first_multicast_ra_num;
689 ra_num--) {
690 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
691 addr_iterator++;
692 }
693}
694
695/** Disable receiving frames for default address
696 *
697 * @param e1000 E1000 data structure
698 *
699 */
700static void disable_ra0_address_filter(e1000_t *e1000)
701{
702 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
703 rah0 = rah0 & ~RAH_AV;
704 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
705}
706
707/** Enable receiving frames for default address
708 *
709 * @param e1000 E1000 data structure
710 *
711 */
712static void enable_ra0_address_filter(e1000_t *e1000)
713{
714 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
715 rah0 = rah0 | RAH_AV;
716 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
717}
718
719/** Disable unicast promiscuous mode
720 *
721 * @param e1000 E1000 data structure
722 *
723 */
724static void e1000_disable_unicast_promisc(e1000_t *e1000)
725{
726 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
727 rctl = rctl & ~RCTL_UPE;
728 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
729}
730
731/** Enable unicast promiscuous mode
732 *
733 * @param e1000 E1000 data structure
734 *
735 */
736static void e1000_enable_unicast_promisc(e1000_t *e1000)
737{
738 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
739 rctl = rctl | RCTL_UPE;
740 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
741}
742
743/** Disable multicast promiscuous mode
744 *
745 * @param e1000 E1000 data structure
746 *
747 */
748static void e1000_disable_multicast_promisc(e1000_t *e1000)
749{
750 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
751 rctl = rctl & ~RCTL_MPE;
752 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
753}
754
755/** Enable multicast promiscuous mode
756 *
757 * @param e1000 E1000 data structure
758 *
759 */
760static void e1000_enable_multicast_promisc(e1000_t *e1000)
761{
762 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
763 rctl = rctl | RCTL_MPE;
764 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
765}
766
767/** Enable accepting of broadcast frames
768 *
769 * @param e1000 E1000 data structure
770 *
771 */
772static void e1000_enable_broadcast_accept(e1000_t *e1000)
773{
774 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
775 rctl = rctl | RCTL_BAM;
776 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
777}
778
779/** Disable accepting of broadcast frames
780 *
781 * @param e1000 E1000 data structure
782 *
783 */
784static void e1000_disable_broadcast_accept(e1000_t *e1000)
785{
786 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
787 rctl = rctl & ~RCTL_BAM;
788 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
789}
790
791/** Enable VLAN filtering according to VFTA registers
792 *
793 * @param e1000 E1000 data structure
794 *
795 */
796static void e1000_enable_vlan_filter(e1000_t *e1000)
797{
798 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
799 rctl = rctl | RCTL_VFE;
800 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
801}
802
803/** Disable VLAN filtering
804 *
805 * @param e1000 E1000 data structure
806 *
807 */
808static void e1000_disable_vlan_filter(e1000_t *e1000)
809{
810 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
811 rctl = rctl & ~RCTL_VFE;
812 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
813}
814
815/** Set multicast frames acceptance mode
816 *
817 * @param nic NIC device to update
818 * @param mode Mode to set
819 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
820 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
821 *
822 * @return EOK
823 *
824 */
825static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
826 const nic_address_t *addr, size_t addr_cnt)
827{
828 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
829 int rc = EOK;
830
831 fibril_mutex_lock(&e1000->rx_lock);
832
833 switch (mode) {
834 case NIC_MULTICAST_BLOCKED:
835 e1000_clear_multicast_receive_addresses(e1000);
836 e1000_disable_multicast_promisc(e1000);
837 nic_report_hw_filtering(nic, -1, 1, -1);
838 break;
839 case NIC_MULTICAST_LIST:
840 e1000_clear_multicast_receive_addresses(e1000);
841 if (addr_cnt > get_free_multicast_address_count(e1000)) {
842 /*
843 * Future work: fill MTA table
844 * Not strictly neccessary, it only saves some compares
845 * in the NIC library.
846 */
847 e1000_enable_multicast_promisc(e1000);
848 nic_report_hw_filtering(nic, -1, 0, -1);
849 } else {
850 e1000_disable_multicast_promisc(e1000);
851 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
852 nic_report_hw_filtering(nic, -1, 1, -1);
853 }
854 break;
855 case NIC_MULTICAST_PROMISC:
856 e1000_enable_multicast_promisc(e1000);
857 e1000_clear_multicast_receive_addresses(e1000);
858 nic_report_hw_filtering(nic, -1, 1, -1);
859 break;
860 default:
861 rc = ENOTSUP;
862 break;
863 }
864
865 fibril_mutex_unlock(&e1000->rx_lock);
866 return rc;
867}
868
869/** Set unicast frames acceptance mode
870 *
871 * @param nic NIC device to update
872 * @param mode Mode to set
873 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
874 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
875 *
876 * @return EOK
877 *
878 */
879static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
880 const nic_address_t *addr, size_t addr_cnt)
881{
882 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
883 int rc = EOK;
884
885 fibril_mutex_lock(&e1000->rx_lock);
886
887 switch (mode) {
888 case NIC_UNICAST_BLOCKED:
889 disable_ra0_address_filter(e1000);
890 e1000_clear_unicast_receive_addresses(e1000);
891 e1000_disable_unicast_promisc(e1000);
892 nic_report_hw_filtering(nic, 1, -1, -1);
893 break;
894 case NIC_UNICAST_DEFAULT:
895 enable_ra0_address_filter(e1000);
896 e1000_clear_unicast_receive_addresses(e1000);
897 e1000_disable_unicast_promisc(e1000);
898 nic_report_hw_filtering(nic, 1, -1, -1);
899 break;
900 case NIC_UNICAST_LIST:
901 enable_ra0_address_filter(e1000);
902 e1000_clear_unicast_receive_addresses(e1000);
903 if (addr_cnt > get_free_unicast_address_count(e1000)) {
904 e1000_enable_unicast_promisc(e1000);
905 nic_report_hw_filtering(nic, 0, -1, -1);
906 } else {
907 e1000_disable_unicast_promisc(e1000);
908 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
909 nic_report_hw_filtering(nic, 1, -1, -1);
910 }
911 break;
912 case NIC_UNICAST_PROMISC:
913 e1000_enable_unicast_promisc(e1000);
914 enable_ra0_address_filter(e1000);
915 e1000_clear_unicast_receive_addresses(e1000);
916 nic_report_hw_filtering(nic, 1, -1, -1);
917 break;
918 default:
919 rc = ENOTSUP;
920 break;
921 }
922
923 fibril_mutex_unlock(&e1000->rx_lock);
924 return rc;
925}
926
927/** Set broadcast frames acceptance mode
928 *
929 * @param nic NIC device to update
930 * @param mode Mode to set
931 *
932 * @return EOK
933 *
934 */
935static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
936{
937 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
938 int rc = EOK;
939
940 fibril_mutex_lock(&e1000->rx_lock);
941
942 switch (mode) {
943 case NIC_BROADCAST_BLOCKED:
944 e1000_disable_broadcast_accept(e1000);
945 break;
946 case NIC_BROADCAST_ACCEPTED:
947 e1000_enable_broadcast_accept(e1000);
948 break;
949 default:
950 rc = ENOTSUP;
951 break;
952 }
953
954 fibril_mutex_unlock(&e1000->rx_lock);
955 return rc;
956}
957
958/** Check if receiving is enabled
959 *
960 * @param e1000 E1000 data structure
961 *
962 * @return true if receiving is enabled
963 *
964 */
965static bool e1000_is_rx_enabled(e1000_t *e1000)
966{
967 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
968 return true;
969
970 return false;
971}
972
973/** Enable receiving
974 *
975 * @param e1000 E1000 data structure
976 *
977 */
978static void e1000_enable_rx(e1000_t *e1000)
979{
980 /* Set Receive Enable Bit */
981 E1000_REG_WRITE(e1000, E1000_RCTL,
982 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
983}
984
985/** Disable receiving
986 *
987 * @param e1000 E1000 data structure
988 *
989 */
990static void e1000_disable_rx(e1000_t *e1000)
991{
992 /* Clear Receive Enable Bit */
993 E1000_REG_WRITE(e1000, E1000_RCTL,
994 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
995}
996
997/** Set VLAN mask
998 *
999 * @param nic NIC device to update
1000 * @param vlan_mask VLAN mask
1001 *
1002 */
1003static void e1000_on_vlan_mask_change(nic_t *nic,
1004 const nic_vlan_mask_t *vlan_mask)
1005{
1006 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1007
1008 fibril_mutex_lock(&e1000->rx_lock);
1009
1010 if (vlan_mask) {
1011 /*
1012 * Disable receiving, so that frame matching
1013 * partially written VLAN is not received.
1014 */
1015 bool rx_enabled = e1000_is_rx_enabled(e1000);
1016 if (rx_enabled)
1017 e1000_disable_rx(e1000);
1018
1019 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1020 uint32_t bitmap_part =
1021 ((uint32_t) vlan_mask->bitmap[i]) |
1022 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1023 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1024 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1025 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1026 }
1027
1028 e1000_enable_vlan_filter(e1000);
1029 if (rx_enabled)
1030 e1000_enable_rx(e1000);
1031 } else
1032 e1000_disable_vlan_filter(e1000);
1033
1034 fibril_mutex_unlock(&e1000->rx_lock);
1035}
1036
1037/** Set VLAN mask
1038 *
1039 * @param device E1000 device
1040 * @param tag VLAN tag
1041 *
1042 * @return EOK
1043 * @return ENOTSUP
1044 *
1045 */
1046static int e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1047 bool strip)
1048{
1049 /* VLAN CFI bit cannot be set */
1050 if (tag & VLANTAG_CFI)
1051 return ENOTSUP;
1052
1053 /*
1054 * CTRL.VME is neccessary for both strip and add
1055 * but CTRL.VME means stripping tags on receive.
1056 */
1057 if (!strip && add)
1058 return ENOTSUP;
1059
1060 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1061
1062 e1000->vlan_tag = tag;
1063 e1000->vlan_tag_add = add;
1064
1065 fibril_mutex_lock(&e1000->ctrl_lock);
1066
1067 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1068 if (strip)
1069 ctrl |= CTRL_VME;
1070 else
1071 ctrl &= ~CTRL_VME;
1072
1073 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1074
1075 fibril_mutex_unlock(&e1000->ctrl_lock);
1076 return EOK;
1077}
1078
1079/** Fill receive descriptor with new empty buffer
1080 *
1081 * Store frame in e1000->rx_frame_phys
1082 *
1083 * @param nic NIC data stricture
1084 * @param offset Receive descriptor offset
1085 *
1086 */
1087static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1088{
1089 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1090
1091 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1092 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1093
1094 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1095 rx_descriptor->length = 0;
1096 rx_descriptor->checksum = 0;
1097 rx_descriptor->status = 0;
1098 rx_descriptor->errors = 0;
1099 rx_descriptor->special = 0;
1100}
1101
1102/** Clear receive descriptor
1103 *
1104 * @param e1000 E1000 data
1105 * @param offset Receive descriptor offset
1106 *
1107 */
1108static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1109{
1110 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1111 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1112
1113 rx_descriptor->length = 0;
1114 rx_descriptor->checksum = 0;
1115 rx_descriptor->status = 0;
1116 rx_descriptor->errors = 0;
1117 rx_descriptor->special = 0;
1118}
1119
1120/** Clear receive descriptor
1121 *
1122 * @param nic NIC data
1123 * @param offset Receive descriptor offset
1124 *
1125 */
1126static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1127{
1128 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1129
1130 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1131 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1132
1133 tx_descriptor->phys_addr = 0;
1134 tx_descriptor->length = 0;
1135 tx_descriptor->checksum_offset = 0;
1136 tx_descriptor->command = 0;
1137 tx_descriptor->status = 0;
1138 tx_descriptor->checksum_start_field = 0;
1139 tx_descriptor->special = 0;
1140}
1141
1142/** Increment tail pointer for receive or transmit ring
1143 *
1144 * @param tail Old Tail
1145 * @param descriptors_count Ring length
1146 *
1147 * @return New tail
1148 *
1149 */
1150static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1151{
1152 if (tail + 1 == descriptors_count)
1153 return 0;
1154 else
1155 return tail + 1;
1156}
1157
1158/** Receive frames
1159 *
1160 * @param nic NIC data
1161 *
1162 */
1163static void e1000_receive_frames(nic_t *nic)
1164{
1165 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1166
1167 fibril_mutex_lock(&e1000->rx_lock);
1168
1169 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1170 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1171
1172 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1173 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1174
1175 while (rx_descriptor->status & 0x01) {
1176 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1177
1178 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1179 if (frame != NULL) {
1180 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1181 nic_received_frame(nic, frame);
1182 } else {
1183 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1184 }
1185
1186 e1000_fill_new_rx_descriptor(nic, next_tail);
1187
1188 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1189 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1190
1191 rx_descriptor = (e1000_rx_descriptor_t *)
1192 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1193 }
1194
1195 fibril_mutex_unlock(&e1000->rx_lock);
1196}
1197
1198/** Enable E1000 interupts
1199 *
1200 * @param e1000 E1000 data structure
1201 *
1202 */
1203static void e1000_enable_interrupts(e1000_t *e1000)
1204{
1205 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1206}
1207
1208/** Disable E1000 interupts
1209 *
1210 * @param e1000 E1000 data structure
1211 *
1212 */
1213static void e1000_disable_interrupts(e1000_t *e1000)
1214{
1215 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1216}
1217
1218/** Interrupt handler implementation
1219 *
1220 * This function is called from e1000_interrupt_handler()
1221 * and e1000_poll()
1222 *
1223 * @param nic NIC data
1224 * @param icr ICR register value
1225 *
1226 */
1227static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1228{
1229 if (icr & ICR_RXT0)
1230 e1000_receive_frames(nic);
1231}
1232
1233/** Handle device interrupt
1234 *
1235 * @param iid IPC call id
1236 * @param icall IPC call structure
1237 * @param dev E1000 device
1238 *
1239 */
1240static void e1000_interrupt_handler(ipc_callid_t iid, ipc_call_t *icall,
1241 ddf_dev_t *dev)
1242{
1243 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1244 nic_t *nic = NIC_DATA_DEV(dev);
1245 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1246
1247 e1000_interrupt_handler_impl(nic, icr);
1248 e1000_enable_interrupts(e1000);
1249}
1250
1251/** Register interrupt handler for the card in the system
1252 *
1253 * Note: The global irq_reg_mutex is locked because of work with global
1254 * structure.
1255 *
1256 * @param nic Driver data
1257 *
1258 * @return IRQ capability handle if the handler was registered
1259 * @return Negative error code otherwise
1260 *
1261 */
1262inline static int e1000_register_int_handler(nic_t *nic)
1263{
1264 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1265
1266 /* Lock the mutex in whole driver while working with global structure */
1267 fibril_mutex_lock(&irq_reg_mutex);
1268
1269 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1270 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1271 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1272
1273 int cap = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1274 e1000_interrupt_handler, &e1000_irq_code);
1275
1276 fibril_mutex_unlock(&irq_reg_mutex);
1277 return cap;
1278}
1279
1280/** Force receiving all frames in the receive buffer
1281 *
1282 * @param nic NIC data
1283 *
1284 */
1285static void e1000_poll(nic_t *nic)
1286{
1287 assert(nic);
1288
1289 e1000_t *e1000 = nic_get_specific(nic);
1290 assert(e1000);
1291
1292 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1293 e1000_interrupt_handler_impl(nic, icr);
1294}
1295
1296/** Calculates ITR register interrupt from timeval structure
1297 *
1298 * @param period Period
1299 *
1300 */
1301static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1302{
1303 // TODO: use also tv_sec
1304 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1305}
1306
1307/** Set polling mode
1308 *
1309 * @param device Device to set
1310 * @param mode Mode to set
1311 * @param period Period for NIC_POLL_PERIODIC
1312 *
1313 * @return EOK if succeed
1314 * @return ENOTSUP if the mode is not supported
1315 *
1316 */
1317static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1318 const struct timeval *period)
1319{
1320 assert(nic);
1321
1322 e1000_t *e1000 = nic_get_specific(nic);
1323 assert(e1000);
1324
1325 switch (mode) {
1326 case NIC_POLL_IMMEDIATE:
1327 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1328 e1000_enable_interrupts(e1000);
1329 break;
1330 case NIC_POLL_ON_DEMAND:
1331 e1000_disable_interrupts(e1000);
1332 break;
1333 case NIC_POLL_PERIODIC:
1334 assert(period);
1335 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1336 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1337 e1000_enable_interrupts(e1000);
1338 break;
1339 default:
1340 return ENOTSUP;
1341 }
1342
1343 return EOK;
1344}
1345
1346/** Initialize receive registers
1347 *
1348 * @param e1000 E1000 data structure
1349 *
1350 */
1351static void e1000_initialize_rx_registers(e1000_t *e1000)
1352{
1353 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1354 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1355
1356 /* It is not posible to let HW use all descriptors */
1357 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1358
1359 /* Set Broadcast Enable Bit */
1360 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1361}
1362
1363/** Initialize receive structure
1364 *
1365 * @param nic NIC data
1366 *
1367 * @return EOK if succeed
1368 * @return Negative error code otherwise
1369 *
1370 */
1371static int e1000_initialize_rx_structure(nic_t *nic)
1372{
1373 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1374 fibril_mutex_lock(&e1000->rx_lock);
1375
1376 e1000->rx_ring_virt = AS_AREA_ANY;
1377 int rc = dmamem_map_anonymous(
1378 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1379 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1380 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1381 if (rc != EOK)
1382 return rc;
1383
1384 E1000_REG_WRITE(e1000, E1000_RDBAH,
1385 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1386 E1000_REG_WRITE(e1000, E1000_RDBAL,
1387 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1388
1389 e1000->rx_frame_phys = (uintptr_t *)
1390 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1391 e1000->rx_frame_virt =
1392 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1393 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1394 rc = ENOMEM;
1395 goto error;
1396 }
1397
1398 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1399 uintptr_t frame_phys;
1400 void *frame_virt = AS_AREA_ANY;
1401
1402 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1403 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1404 &frame_phys, &frame_virt);
1405 if (rc != EOK)
1406 goto error;
1407
1408 e1000->rx_frame_phys[i] = frame_phys;
1409 e1000->rx_frame_virt[i] = frame_virt;
1410 }
1411
1412 /* Write descriptor */
1413 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1414 e1000_fill_new_rx_descriptor(nic, i);
1415
1416 e1000_initialize_rx_registers(e1000);
1417
1418 fibril_mutex_unlock(&e1000->rx_lock);
1419 return EOK;
1420
1421error:
1422 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1423 if (e1000->rx_frame_virt[i] != NULL) {
1424 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1425 e1000->rx_frame_phys[i] = 0;
1426 e1000->rx_frame_virt[i] = NULL;
1427 }
1428 }
1429
1430 if (e1000->rx_frame_phys != NULL) {
1431 free(e1000->rx_frame_phys);
1432 e1000->rx_frame_phys = NULL;
1433 }
1434
1435 if (e1000->rx_frame_virt != NULL) {
1436 free(e1000->rx_frame_virt);
1437 e1000->rx_frame_virt = NULL;
1438 }
1439
1440 return rc;
1441}
1442
1443/** Uninitialize receive structure
1444 *
1445 * @param nic NIC data
1446 *
1447 */
1448static void e1000_uninitialize_rx_structure(nic_t *nic)
1449{
1450 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1451
1452 /* Write descriptor */
1453 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1454 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1455 e1000->rx_frame_phys[offset] = 0;
1456 e1000->rx_frame_virt[offset] = NULL;
1457 }
1458
1459 free(e1000->rx_frame_virt);
1460
1461 e1000->rx_frame_phys = NULL;
1462 e1000->rx_frame_virt = NULL;
1463
1464 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1465}
1466
1467/** Clear receive descriptor ring
1468 *
1469 * @param e1000 E1000 data
1470 *
1471 */
1472static void e1000_clear_rx_ring(e1000_t *e1000)
1473{
1474 /* Write descriptor */
1475 for (unsigned int offset = 0;
1476 offset < E1000_RX_FRAME_COUNT;
1477 offset++)
1478 e1000_clear_rx_descriptor(e1000, offset);
1479}
1480
1481/** Initialize filters
1482 *
1483 * @param e1000 E1000 data
1484 *
1485 */
1486static void e1000_initialize_filters(e1000_t *e1000)
1487{
1488 /* Initialize address filter */
1489 e1000->unicast_ra_count = 0;
1490 e1000->multicast_ra_count = 0;
1491 e1000_clear_unicast_receive_addresses(e1000);
1492}
1493
1494/** Initialize VLAN
1495 *
1496 * @param e1000 E1000 data
1497 *
1498 */
1499static void e1000_initialize_vlan(e1000_t *e1000)
1500{
1501 e1000->vlan_tag_add = false;
1502}
1503
1504/** Fill MAC address from EEPROM to RA[0] register
1505 *
1506 * @param e1000 E1000 data
1507 *
1508 */
1509static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1510{
1511 /* MAC address from eeprom to RA[0] */
1512 nic_address_t address;
1513 e1000_eeprom_get_address(e1000, &address);
1514 e1000_write_receive_address(e1000, 0, &address, true);
1515}
1516
1517/** Initialize other registers
1518 *
1519 * @param dev E1000 data.
1520 *
1521 * @return EOK if succeed
1522 * @return Negative error code otherwise
1523 *
1524 */
1525static void e1000_initialize_registers(e1000_t *e1000)
1526{
1527 E1000_REG_WRITE(e1000, E1000_ITR,
1528 e1000_calculate_itr_interval_from_usecs(
1529 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1530 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1531 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1532 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1533 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1534 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1535 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1536}
1537
1538/** Initialize transmit registers
1539 *
1540 * @param e1000 E1000 data.
1541 *
1542 */
1543static void e1000_initialize_tx_registers(e1000_t *e1000)
1544{
1545 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1546 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1547 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1548
1549 E1000_REG_WRITE(e1000, E1000_TIPG,
1550 10 << TIPG_IPGT_SHIFT |
1551 8 << TIPG_IPGR1_SHIFT |
1552 6 << TIPG_IPGR2_SHIFT);
1553
1554 E1000_REG_WRITE(e1000, E1000_TCTL,
1555 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1556 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1557 TCTL_PSP /* Pad Short Packets */);
1558}
1559
1560/** Initialize transmit structure
1561 *
1562 * @param e1000 E1000 data.
1563 *
1564 */
1565static int e1000_initialize_tx_structure(e1000_t *e1000)
1566{
1567 size_t i;
1568
1569 fibril_mutex_lock(&e1000->tx_lock);
1570
1571 e1000->tx_ring_phys = 0;
1572 e1000->tx_ring_virt = AS_AREA_ANY;
1573
1574 e1000->tx_frame_phys = NULL;
1575 e1000->tx_frame_virt = NULL;
1576
1577 int rc = dmamem_map_anonymous(
1578 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1579 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1580 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1581 if (rc != EOK)
1582 goto error;
1583
1584 memset(e1000->tx_ring_virt, 0,
1585 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1586
1587 e1000->tx_frame_phys = (uintptr_t *)
1588 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1589 e1000->tx_frame_virt =
1590 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1591
1592 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1593 rc = ENOMEM;
1594 goto error;
1595 }
1596
1597 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1598 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1599 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1600 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1601 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1602 if (rc != EOK)
1603 goto error;
1604 }
1605
1606 E1000_REG_WRITE(e1000, E1000_TDBAH,
1607 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1608 E1000_REG_WRITE(e1000, E1000_TDBAL,
1609 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1610
1611 e1000_initialize_tx_registers(e1000);
1612
1613 fibril_mutex_unlock(&e1000->tx_lock);
1614 return EOK;
1615
1616error:
1617 if (e1000->tx_ring_virt != NULL) {
1618 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1619 e1000->tx_ring_virt = NULL;
1620 }
1621
1622 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1623 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1624 if (e1000->tx_frame_virt[i] != NULL) {
1625 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1626 e1000->tx_frame_phys[i] = 0;
1627 e1000->tx_frame_virt[i] = NULL;
1628 }
1629 }
1630 }
1631
1632 if (e1000->tx_frame_phys != NULL) {
1633 free(e1000->tx_frame_phys);
1634 e1000->tx_frame_phys = NULL;
1635 }
1636
1637 if (e1000->tx_frame_virt != NULL) {
1638 free(e1000->tx_frame_virt);
1639 e1000->tx_frame_virt = NULL;
1640 }
1641
1642 return rc;
1643}
1644
1645/** Uninitialize transmit structure
1646 *
1647 * @param nic NIC data
1648 *
1649 */
1650static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1651{
1652 size_t i;
1653
1654 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1655 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1656 e1000->tx_frame_phys[i] = 0;
1657 e1000->tx_frame_virt[i] = NULL;
1658 }
1659
1660 if (e1000->tx_frame_phys != NULL) {
1661 free(e1000->tx_frame_phys);
1662 e1000->tx_frame_phys = NULL;
1663 }
1664
1665 if (e1000->tx_frame_virt != NULL) {
1666 free(e1000->tx_frame_virt);
1667 e1000->tx_frame_virt = NULL;
1668 }
1669
1670 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1671}
1672
1673/** Clear transmit descriptor ring
1674 *
1675 * @param nic NIC data
1676 *
1677 */
1678static void e1000_clear_tx_ring(nic_t *nic)
1679{
1680 /* Write descriptor */
1681 for (unsigned int offset = 0;
1682 offset < E1000_TX_FRAME_COUNT;
1683 offset++)
1684 e1000_clear_tx_descriptor(nic, offset);
1685}
1686
1687/** Enable transmit
1688 *
1689 * @param e1000 E1000 data
1690 *
1691 */
1692static void e1000_enable_tx(e1000_t *e1000)
1693{
1694 /* Set Transmit Enable Bit */
1695 E1000_REG_WRITE(e1000, E1000_TCTL,
1696 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1697}
1698
1699/** Disable transmit
1700 *
1701 * @param e1000 E1000 data
1702 *
1703 */
1704static void e1000_disable_tx(e1000_t *e1000)
1705{
1706 /* Clear Transmit Enable Bit */
1707 E1000_REG_WRITE(e1000, E1000_TCTL,
1708 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1709}
1710
1711/** Reset E1000 device
1712 *
1713 * @param e1000 The E1000 data
1714 *
1715 */
1716static int e1000_reset(nic_t *nic)
1717{
1718 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1719
1720 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1721
1722 /* Wait for the reset */
1723 thread_usleep(20);
1724
1725 /* check if RST_BIT cleared */
1726 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1727 return EINVAL;
1728
1729 e1000_initialize_registers(e1000);
1730 e1000_initialize_rx_registers(e1000);
1731 e1000_initialize_tx_registers(e1000);
1732 e1000_fill_mac_from_eeprom(e1000);
1733 e1000_initialize_filters(e1000);
1734 e1000_initialize_vlan(e1000);
1735
1736 return EOK;
1737}
1738
1739/** Activate the device to receive and transmit frames
1740 *
1741 * @param nic NIC driver data
1742 *
1743 * @return EOK if activated successfully
1744 * @return Error code otherwise
1745 *
1746 */
1747static int e1000_on_activating(nic_t *nic)
1748{
1749 assert(nic);
1750
1751 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1752
1753 fibril_mutex_lock(&e1000->rx_lock);
1754 fibril_mutex_lock(&e1000->tx_lock);
1755 fibril_mutex_lock(&e1000->ctrl_lock);
1756
1757 e1000_enable_interrupts(e1000);
1758
1759 int rc = irc_enable_interrupt(e1000->irq);
1760 if (rc != EOK) {
1761 e1000_disable_interrupts(e1000);
1762 fibril_mutex_unlock(&e1000->ctrl_lock);
1763 fibril_mutex_unlock(&e1000->tx_lock);
1764 fibril_mutex_unlock(&e1000->rx_lock);
1765 return rc;
1766 }
1767
1768 e1000_clear_rx_ring(e1000);
1769 e1000_enable_rx(e1000);
1770
1771 e1000_clear_tx_ring(nic);
1772 e1000_enable_tx(e1000);
1773
1774 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1775 ctrl |= CTRL_SLU;
1776 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1777
1778 fibril_mutex_unlock(&e1000->ctrl_lock);
1779 fibril_mutex_unlock(&e1000->tx_lock);
1780 fibril_mutex_unlock(&e1000->rx_lock);
1781
1782 return EOK;
1783}
1784
1785/** Callback for NIC_STATE_DOWN change
1786 *
1787 * @param nic NIC driver data
1788 *
1789 * @return EOK if succeed
1790 * @return Error code otherwise
1791 *
1792 */
1793static int e1000_on_down_unlocked(nic_t *nic)
1794{
1795 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1796
1797 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1798 ctrl &= ~CTRL_SLU;
1799 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1800
1801 e1000_disable_tx(e1000);
1802 e1000_disable_rx(e1000);
1803
1804 irc_disable_interrupt(e1000->irq);
1805 e1000_disable_interrupts(e1000);
1806
1807 /*
1808 * Wait for the for the end of all data
1809 * transfers to descriptors.
1810 */
1811 thread_usleep(100);
1812
1813 return EOK;
1814}
1815
1816/** Callback for NIC_STATE_DOWN change
1817 *
1818 * @param nic NIC driver data
1819 *
1820 * @return EOK if succeed
1821 * @return Error code otherwise
1822 *
1823 */
1824static int e1000_on_down(nic_t *nic)
1825{
1826 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1827
1828 fibril_mutex_lock(&e1000->rx_lock);
1829 fibril_mutex_lock(&e1000->tx_lock);
1830 fibril_mutex_lock(&e1000->ctrl_lock);
1831
1832 int rc = e1000_on_down_unlocked(nic);
1833
1834 fibril_mutex_unlock(&e1000->ctrl_lock);
1835 fibril_mutex_unlock(&e1000->tx_lock);
1836 fibril_mutex_unlock(&e1000->rx_lock);
1837
1838 return rc;
1839}
1840
1841/** Callback for NIC_STATE_STOPPED change
1842 *
1843 * @param nic NIC driver data
1844 *
1845 * @return EOK if succeed
1846 * @return Error code otherwise
1847 *
1848 */
1849static int e1000_on_stopping(nic_t *nic)
1850{
1851 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1852
1853 fibril_mutex_lock(&e1000->rx_lock);
1854 fibril_mutex_lock(&e1000->tx_lock);
1855 fibril_mutex_lock(&e1000->ctrl_lock);
1856
1857 int rc = e1000_on_down_unlocked(nic);
1858 if (rc == EOK)
1859 rc = e1000_reset(nic);
1860
1861 fibril_mutex_unlock(&e1000->ctrl_lock);
1862 fibril_mutex_unlock(&e1000->tx_lock);
1863 fibril_mutex_unlock(&e1000->rx_lock);
1864
1865 return rc;
1866}
1867
1868/** Create driver data structure
1869 *
1870 * @return Intialized device data structure or NULL
1871 *
1872 */
1873static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1874{
1875 nic_t *nic = nic_create_and_bind(dev);
1876 if (!nic)
1877 return NULL;
1878
1879 e1000_t *e1000 = malloc(sizeof(e1000_t));
1880 if (!e1000) {
1881 nic_unbind_and_destroy(dev);
1882 return NULL;
1883 }
1884
1885 memset(e1000, 0, sizeof(e1000_t));
1886
1887 nic_set_specific(nic, e1000);
1888 nic_set_send_frame_handler(nic, e1000_send_frame);
1889 nic_set_state_change_handlers(nic, e1000_on_activating,
1890 e1000_on_down, e1000_on_stopping);
1891 nic_set_filtering_change_handlers(nic,
1892 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1893 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1894 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1895
1896 fibril_mutex_initialize(&e1000->ctrl_lock);
1897 fibril_mutex_initialize(&e1000->rx_lock);
1898 fibril_mutex_initialize(&e1000->tx_lock);
1899 fibril_mutex_initialize(&e1000->eeprom_lock);
1900
1901 return e1000;
1902}
1903
1904/** Delete driver data structure
1905 *
1906 * @param data E1000 device data structure
1907 *
1908 */
1909inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1910{
1911 assert(dev);
1912
1913 if (ddf_dev_data_get(dev) != NULL)
1914 nic_unbind_and_destroy(dev);
1915}
1916
1917/** Clean up the E1000 device structure.
1918 *
1919 * @param dev Device structure.
1920 *
1921 */
1922static void e1000_dev_cleanup(ddf_dev_t *dev)
1923{
1924 assert(dev);
1925
1926 e1000_delete_dev_data(dev);
1927}
1928
1929/** Fill the irq and io_addr part of device data structure
1930 *
1931 * The hw_resources must be obtained before calling this function
1932 *
1933 * @param dev Device structure
1934 * @param hw_resources Hardware resources obtained from the parent device
1935 *
1936 * @return EOK if succeed
1937 * @return Negative error code otherwise
1938 *
1939 */
1940static int e1000_fill_resource_info(ddf_dev_t *dev,
1941 const hw_res_list_parsed_t *hw_resources)
1942{
1943 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1944
1945 if (hw_resources->irqs.count != 1)
1946 return EINVAL;
1947
1948 e1000->irq = hw_resources->irqs.irqs[0];
1949 e1000->reg_base_phys =
1950 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1951
1952 return EOK;
1953}
1954
1955/** Obtain information about hardware resources of the device
1956 *
1957 * The device must be connected to the parent
1958 *
1959 * @param dev Device structure
1960 *
1961 * @return EOK if succeed
1962 * @return Negative error code otherwise
1963 *
1964 */
1965static int e1000_get_resource_info(ddf_dev_t *dev)
1966{
1967 assert(dev != NULL);
1968 assert(NIC_DATA_DEV(dev) != NULL);
1969
1970 hw_res_list_parsed_t hw_res_parsed;
1971 hw_res_list_parsed_init(&hw_res_parsed);
1972
1973 /* Get hw resources form parent driver */
1974 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1975 if (rc != EOK)
1976 return rc;
1977
1978 /* Fill resources information to the device */
1979 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1980 hw_res_list_parsed_clean(&hw_res_parsed);
1981
1982 return rc;
1983}
1984
1985/** Initialize the E1000 device structure
1986 *
1987 * @param dev Device information
1988 *
1989 * @return EOK if succeed
1990 * @return Negative error code otherwise
1991 *
1992 */
1993static int e1000_device_initialize(ddf_dev_t *dev)
1994{
1995 /* Allocate driver data for the device. */
1996 e1000_t *e1000 = e1000_create_dev_data(dev);
1997 if (e1000 == NULL) {
1998 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1999 return ENOMEM;
2000 }
2001
2002 /* Obtain and fill hardware resources info */
2003 int rc = e1000_get_resource_info(dev);
2004 if (rc != EOK) {
2005 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2006 e1000_dev_cleanup(dev);
2007 return rc;
2008 }
2009
2010 uint16_t device_id;
2011 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2012 &device_id);
2013 if (rc != EOK) {
2014 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2015 e1000_dev_cleanup(dev);
2016 return rc;
2017 }
2018
2019 e1000_board_t board;
2020 switch (device_id) {
2021 case 0x100e:
2022 case 0x1015:
2023 case 0x1016:
2024 case 0x1017:
2025 board = E1000_82540;
2026 break;
2027 case 0x1013:
2028 case 0x1018:
2029 case 0x1078:
2030 board = E1000_82541;
2031 break;
2032 case 0x1076:
2033 case 0x1077:
2034 case 0x107c:
2035 board = E1000_82541REV2;
2036 break;
2037 case 0x100f:
2038 case 0x1011:
2039 case 0x1026:
2040 case 0x1027:
2041 case 0x1028:
2042 board = E1000_82545;
2043 break;
2044 case 0x1010:
2045 case 0x1012:
2046 case 0x101d:
2047 case 0x1079:
2048 case 0x107a:
2049 case 0x107b:
2050 board = E1000_82546;
2051 break;
2052 case 0x1019:
2053 case 0x101a:
2054 board = E1000_82547;
2055 break;
2056 case 0x10b9:
2057 board = E1000_82572;
2058 break;
2059 case 0x1096:
2060 board = E1000_80003ES2;
2061 break;
2062 default:
2063 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2064 device_id);
2065 e1000_dev_cleanup(dev);
2066 return ENOTSUP;
2067 }
2068
2069 switch (board) {
2070 case E1000_82540:
2071 case E1000_82541:
2072 case E1000_82541REV2:
2073 case E1000_82545:
2074 case E1000_82546:
2075 e1000->info.eerd_start = 0x01;
2076 e1000->info.eerd_done = 0x10;
2077 e1000->info.eerd_address_offset = 8;
2078 e1000->info.eerd_data_offset = 16;
2079 break;
2080 case E1000_82547:
2081 case E1000_82572:
2082 case E1000_80003ES2:
2083 e1000->info.eerd_start = 0x01;
2084 e1000->info.eerd_done = 0x02;
2085 e1000->info.eerd_address_offset = 2;
2086 e1000->info.eerd_data_offset = 16;
2087 break;
2088 }
2089
2090 return EOK;
2091}
2092
2093/** Enable the I/O ports of the device.
2094 *
2095 * @param dev E1000 device.
2096 *
2097 * @return EOK if successed
2098 * @return Negative error code otherwise
2099 *
2100 */
2101static int e1000_pio_enable(ddf_dev_t *dev)
2102{
2103 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2104
2105 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2106 &e1000->reg_base_virt);
2107 if (rc != EOK)
2108 return EADDRNOTAVAIL;
2109
2110 return EOK;
2111}
2112
2113/** Probe and initialize the newly added device.
2114 *
2115 * @param dev E1000 device.
2116 *
2117 */
2118int e1000_dev_add(ddf_dev_t *dev)
2119{
2120 ddf_fun_t *fun;
2121 assert(dev);
2122
2123 /* Initialize device structure for E1000 */
2124 int rc = e1000_device_initialize(dev);
2125 if (rc != EOK)
2126 return rc;
2127
2128 /* Device initialization */
2129 nic_t *nic = ddf_dev_data_get(dev);
2130 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2131
2132 /* Map registers */
2133 rc = e1000_pio_enable(dev);
2134 if (rc != EOK)
2135 goto err_destroy;
2136
2137 e1000_initialize_registers(e1000);
2138 rc = e1000_initialize_tx_structure(e1000);
2139 if (rc != EOK)
2140 goto err_pio;
2141
2142 fibril_mutex_lock(&e1000->rx_lock);
2143
2144 e1000_fill_mac_from_eeprom(e1000);
2145 e1000_initialize_filters(e1000);
2146
2147 fibril_mutex_unlock(&e1000->rx_lock);
2148
2149 e1000_initialize_vlan(e1000);
2150
2151 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2152 if (fun == NULL)
2153 goto err_tx_structure;
2154 nic_set_ddf_fun(nic, fun);
2155 ddf_fun_set_ops(fun, &e1000_dev_ops);
2156
2157 int irq_cap = e1000_register_int_handler(nic);
2158 if (irq_cap < 0) {
2159 rc = irq_cap;
2160 goto err_fun_create;
2161 }
2162
2163 rc = e1000_initialize_rx_structure(nic);
2164 if (rc != EOK)
2165 goto err_irq;
2166
2167 nic_address_t e1000_address;
2168 e1000_get_address(e1000, &e1000_address);
2169 rc = nic_report_address(nic, &e1000_address);
2170 if (rc != EOK)
2171 goto err_rx_structure;
2172
2173 struct timeval period;
2174 period.tv_sec = 0;
2175 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2176 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2177 if (rc != EOK)
2178 goto err_rx_structure;
2179
2180 rc = ddf_fun_bind(fun);
2181 if (rc != EOK)
2182 goto err_fun_bind;
2183
2184 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2185 if (rc != EOK)
2186 goto err_add_to_cat;
2187
2188 return EOK;
2189
2190err_add_to_cat:
2191 ddf_fun_unbind(fun);
2192err_fun_bind:
2193err_rx_structure:
2194 e1000_uninitialize_rx_structure(nic);
2195err_irq:
2196 unregister_interrupt_handler(dev, irq_cap);
2197err_fun_create:
2198 ddf_fun_destroy(fun);
2199 nic_set_ddf_fun(nic, NULL);
2200err_tx_structure:
2201 e1000_uninitialize_tx_structure(e1000);
2202err_pio:
2203 // TODO: e1000_pio_disable(dev);
2204err_destroy:
2205 e1000_dev_cleanup(dev);
2206 return rc;
2207}
2208
2209/** Read 16-bit value from EEPROM of E1000 adapter
2210 *
2211 * Read using the EERD register.
2212 *
2213 * @param device E1000 device
2214 * @param eeprom_address 8-bit EEPROM address
2215 *
2216 * @return 16-bit value from EEPROM
2217 *
2218 */
2219static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2220{
2221 fibril_mutex_lock(&e1000->eeprom_lock);
2222
2223 /* Write address and START bit to EERD register */
2224 uint32_t write_data = e1000->info.eerd_start |
2225 (((uint32_t) eeprom_address) <<
2226 e1000->info.eerd_address_offset);
2227 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2228
2229 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2230 while ((eerd & e1000->info.eerd_done) == 0) {
2231 thread_usleep(1);
2232 eerd = E1000_REG_READ(e1000, E1000_EERD);
2233 }
2234
2235 fibril_mutex_unlock(&e1000->eeprom_lock);
2236
2237 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2238}
2239
2240/** Get MAC address of the E1000 adapter
2241 *
2242 * @param device E1000 device
2243 * @param address Place to store the address
2244 * @param max_len Maximal addresss length to store
2245 *
2246 * @return EOK if succeed
2247 * @return Negative error code otherwise
2248 *
2249 */
2250static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2251{
2252 fibril_mutex_lock(&e1000->rx_lock);
2253
2254 uint8_t *mac0_dest = (uint8_t *) address->address;
2255 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2256 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2257 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2258 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2259 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2260
2261 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2262 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2263
2264 *mac0_dest = (uint8_t) ral;
2265 *mac1_dest = (uint8_t) (ral >> 8);
2266 *mac2_dest = (uint8_t) (ral >> 16);
2267 *mac3_dest = (uint8_t) (ral >> 24);
2268 *mac4_dest = (uint8_t) rah;
2269 *mac5_dest = (uint8_t) (rah >> 8);
2270
2271 fibril_mutex_unlock(&e1000->rx_lock);
2272 return EOK;
2273};
2274
2275/** Set card MAC address
2276 *
2277 * @param device E1000 device
2278 * @param address Address
2279 *
2280 * @return EOK if succeed
2281 * @return Negative error code otherwise
2282 */
2283static int e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2284{
2285 nic_t *nic = NIC_DATA_FUN(fun);
2286 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2287
2288 fibril_mutex_lock(&e1000->rx_lock);
2289 fibril_mutex_lock(&e1000->tx_lock);
2290
2291 int rc = nic_report_address(nic, addr);
2292 if (rc == EOK)
2293 e1000_write_receive_address(e1000, 0, addr, false);
2294
2295 fibril_mutex_unlock(&e1000->tx_lock);
2296 fibril_mutex_unlock(&e1000->rx_lock);
2297
2298 return rc;
2299}
2300
2301static void e1000_eeprom_get_address(e1000_t *e1000,
2302 nic_address_t *address)
2303{
2304 uint16_t *mac0_dest = (uint16_t *) address->address;
2305 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2306 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2307
2308 *mac0_dest = e1000_eeprom_read(e1000, 0);
2309 *mac2_dest = e1000_eeprom_read(e1000, 1);
2310 *mac4_dest = e1000_eeprom_read(e1000, 2);
2311}
2312
2313/** Send frame
2314 *
2315 * @param nic NIC driver data structure
2316 * @param data Frame data
2317 * @param size Frame size in bytes
2318 *
2319 * @return EOK if succeed
2320 * @return Error code in the case of error
2321 *
2322 */
2323static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2324{
2325 assert(nic);
2326
2327 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2328 fibril_mutex_lock(&e1000->tx_lock);
2329
2330 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2331 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2332 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2333
2334 bool descriptor_available = false;
2335
2336 /* Descriptor never used */
2337 if (tx_descriptor_addr->length == 0)
2338 descriptor_available = true;
2339
2340 /* Descriptor done */
2341 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2342 descriptor_available = true;
2343
2344 if (!descriptor_available) {
2345 /* Frame lost */
2346 fibril_mutex_unlock(&e1000->tx_lock);
2347 return;
2348 }
2349
2350 memcpy(e1000->tx_frame_virt[tdt], data, size);
2351
2352 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2353 tx_descriptor_addr->length = size;
2354
2355 /*
2356 * Report status to STATUS.DD (descriptor done),
2357 * add ethernet CRC, end of packet.
2358 */
2359 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2360 TXDESCRIPTOR_COMMAND_IFCS |
2361 TXDESCRIPTOR_COMMAND_EOP;
2362
2363 tx_descriptor_addr->checksum_offset = 0;
2364 tx_descriptor_addr->status = 0;
2365 if (e1000->vlan_tag_add) {
2366 tx_descriptor_addr->special = e1000->vlan_tag;
2367 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2368 } else
2369 tx_descriptor_addr->special = 0;
2370
2371 tx_descriptor_addr->checksum_start_field = 0;
2372
2373 tdt++;
2374 if (tdt == E1000_TX_FRAME_COUNT)
2375 tdt = 0;
2376
2377 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2378
2379 fibril_mutex_unlock(&e1000->tx_lock);
2380}
2381
2382int main(void)
2383{
2384 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2385
2386 if (nic_driver_init(NAME) != EOK)
2387 return 1;
2388
2389 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2390 &e1000_nic_iface);
2391
2392 ddf_log_init(NAME);
2393 return ddf_driver_main(&e1000_driver);
2394}
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