source: mainline/uspace/drv/nic/e1k/e1k.c@ 321052f7

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 321052f7 was 321052f7, checked in by Martin Decky <martin@…>, 14 years ago

fix typos
  • Property mode set to 100644
File size: 55.0 KB
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1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <byteorder.h>
41#include <sysinfo.h>
42#include <ipc/irc.h>
43#include <ipc/ns.h>
44#include <libarch/ddi.h>
45#include <as.h>
46#include <ddf/log.h>
47#include <ddf/interrupt.h>
48#include <devman.h>
49#include <device/hw_res_parsed.h>
50#include <device/pci.h>
51#include <nic.h>
52#include <nil_remote.h>
53#include <ops/nic.h>
54#include "e1k.h"
55
56#define NAME "e1k"
57
58#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
59
60/* Must be power of 8 */
61#define E1000_RX_FRAME_COUNT 128
62#define E1000_TX_FRAME_COUNT 128
63
64#define E1000_RECEIVE_ADDRESS 16
65
66/** Maximum sending frame size */
67#define E1000_MAX_SEND_FRAME_SIZE 2048
68/** Maximum receiving frame size */
69#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
70
71/** nic_driver_data_t* -> e1000_t* cast */
72#define DRIVER_DATA_NIC(nic) \
73 ((e1000_t *) nic_get_specific(nic))
74
75/** device_t* -> nic_driver_data_t* cast */
76#define NIC_DATA_DEV(dev) \
77 ((nic_t *) ((dev)->driver_data))
78
79/** device_t* -> e1000_t* cast */
80#define DRIVER_DATA_DEV(dev) \
81 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
82
83/** Cast pointer to uint64_t
84 *
85 * @param ptr Pointer to cast
86 *
87 * @return The uint64_t pointer representation.
88 *
89 */
90#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
91
92/** Cast the memaddr part to the void*
93 *
94 * @param memaddr The memaddr value
95 *
96 */
97#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
98
99#define E1000_REG_BASE(e1000) \
100 ((e1000)->reg_base_virt)
101
102#define E1000_REG_ADDR(e1000, reg) \
103 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
104
105#define E1000_REG_READ(e1000, reg) \
106 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
107
108#define E1000_REG_WRITE(e1000, reg, value) \
109 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
110
111/** E1000 device data */
112typedef struct {
113 /** Device configuration */
114 e1000_info_t info;
115
116 /** Physical registers base address */
117 void *reg_base_phys;
118 /** Virtual registers base address */
119 void *reg_base_virt;
120
121 /** Physical tx ring address */
122 void *tx_ring_phys;
123 /** Virtual tx ring address */
124 void *tx_ring_virt;
125
126 /** Ring of TX frames, physical address */
127 void **tx_frame_phys;
128 /** Ring of TX frames, virtual address */
129 void **tx_frame_virt;
130
131 /** Physical rx ring address */
132 void *rx_ring_phys;
133 /** Virtual rx ring address */
134 void *rx_ring_virt;
135
136 /** Ring of RX frames, physical address */
137 void **rx_frame_phys;
138 /** Ring of RX frames, virtual address */
139 void **rx_frame_virt;
140
141 /** VLAN tag */
142 uint16_t vlan_tag;
143
144 /** Add VLAN tag to frame */
145 bool vlan_tag_add;
146
147 /** Used unicast Receive Address count */
148 unsigned int unicast_ra_count;
149
150 /** Used milticast Receive addrress count */
151 unsigned int multicast_ra_count;
152
153 /** The irq assigned */
154 int irq;
155
156 /** Lock for CTRL register */
157 fibril_mutex_t ctrl_lock;
158
159 /** Lock for receiver */
160 fibril_mutex_t rx_lock;
161
162 /** Lock for transmitter */
163 fibril_mutex_t tx_lock;
164
165 /** Lock for EEPROM access */
166 fibril_mutex_t eeprom_lock;
167} e1000_t;
168
169/** Global mutex for work with shared irq structure */
170FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
171
172static int e1000_get_address(e1000_t *, nic_address_t *);
173static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
174static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
175
176static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
177static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
178
179static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
180static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
181static int e1000_get_operation_mode(ddf_fun_t *, int *,
182 nic_channel_mode_t *, nic_role_t *);
183static int e1000_set_operation_mode(ddf_fun_t *, int,
184 nic_channel_mode_t, nic_role_t);
185static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
186static int e1000_autoneg_disable(ddf_fun_t *);
187static int e1000_autoneg_restart(ddf_fun_t *);
188
189static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
190
191/** Network interface options for E1000 card driver */
192static nic_iface_t e1000_nic_iface;
193
194/** Network interface options for E1000 card driver */
195static nic_iface_t e1000_nic_iface = {
196 .set_address = &e1000_set_addr,
197 .get_device_info = &e1000_get_device_info,
198 .get_cable_state = &e1000_get_cable_state,
199 .get_operation_mode = &e1000_get_operation_mode,
200 .set_operation_mode = &e1000_set_operation_mode,
201 .autoneg_enable = &e1000_autoneg_enable,
202 .autoneg_disable = &e1000_autoneg_disable,
203 .autoneg_restart = &e1000_autoneg_restart,
204 .vlan_set_tag = &e1000_vlan_set_tag,
205 .defective_get_mode = &e1000_defective_get_mode,
206 .defective_set_mode = &e1000_defective_set_mode,
207};
208
209/** Basic device operations for E1000 driver */
210static ddf_dev_ops_t e1000_dev_ops;
211
212static int e1000_dev_add(ddf_dev_t *);
213
214/** Basic driver operations for E1000 driver */
215static driver_ops_t e1000_driver_ops = {
216 .dev_add = e1000_dev_add
217};
218
219/** Driver structure for E1000 driver */
220static driver_t e1000_driver = {
221 .name = NAME,
222 .driver_ops = &e1000_driver_ops
223};
224
225/* The default implementation callbacks */
226static int e1000_on_activating(nic_t *);
227static int e1000_on_stopping(nic_t *);
228static void e1000_send_frame(nic_t *, void *, size_t);
229
230/** Commands to deal with interrupt
231 *
232 */
233irq_cmd_t e1000_irq_commands[] = {
234 {
235 /* Get the interrupt status */
236 .cmd = CMD_PIO_READ_32,
237 .addr = NULL,
238 .dstarg = 2
239 },
240 {
241 .cmd = CMD_PREDICATE,
242 .value = 2,
243 .srcarg = 2
244 },
245 {
246 /* Disable interrupts until interrupt routine is finished */
247 .cmd = CMD_PIO_WRITE_32,
248 .addr = NULL,
249 .value = 0xffffffff
250 },
251 {
252 .cmd = CMD_ACCEPT
253 }
254};
255
256/** Interrupt code definition */
257irq_code_t e1000_irq_code = {
258 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
259 .cmds = e1000_irq_commands
260};
261
262/** Get the device information
263 *
264 * @param dev NIC device
265 * @param info Information to fill
266 *
267 * @return EOK
268 *
269 */
270static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
271{
272 assert(dev);
273 assert(info);
274
275 bzero(info, sizeof(nic_device_info_t));
276
277 info->vendor_id = 0x8086;
278 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
279 "Intel Corporation");
280 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
281 "Intel Pro");
282
283 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
284 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
285 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
286
287 return EOK;
288}
289
290/** Check the cable state
291 *
292 * @param[in] dev device
293 * @param[out] state state to fill
294 *
295 * @return EOK
296 *
297 */
298static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
299{
300 assert(dev);
301 assert(DRIVER_DATA_DEV(dev));
302 assert(state);
303
304 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
305 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
306 *state = NIC_CS_PLUGGED;
307 else
308 *state = NIC_CS_UNPLUGGED;
309
310 return EOK;
311}
312
313static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
314{
315 return useconds * 4;
316}
317
318/** Get operation mode of the device
319 *
320 */
321static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
322 nic_channel_mode_t *duplex, nic_role_t *role)
323{
324 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
325 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
326
327 if (status & STATUS_FD)
328 *duplex = NIC_CM_FULL_DUPLEX;
329 else
330 *duplex = NIC_CM_HALF_DUPLEX;
331
332 uint32_t speed_bits =
333 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
334
335 if (speed_bits == STATUS_SPEED_10)
336 *speed = 10;
337 else if (speed_bits == STATUS_SPEED_100)
338 *speed = 100;
339 else if ((speed_bits == STATUS_SPEED_1000A) ||
340 (speed_bits == STATUS_SPEED_1000B))
341 *speed = 1000;
342
343 *role = NIC_ROLE_UNKNOWN;
344 return EOK;
345}
346
347static void e1000_link_restart(e1000_t *e1000)
348{
349 fibril_mutex_lock(&e1000->ctrl_lock);
350
351 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
352
353 if (ctrl & CTRL_SLU) {
354 ctrl &= ~(CTRL_SLU);
355 fibril_mutex_unlock(&e1000->ctrl_lock);
356 usleep(10);
357 fibril_mutex_lock(&e1000->ctrl_lock);
358 ctrl |= CTRL_SLU;
359 }
360
361 fibril_mutex_unlock(&e1000->ctrl_lock);
362
363 e1000_link_restart(e1000);
364}
365
366/** Set operation mode of the device
367 *
368 */
369static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
370 nic_channel_mode_t duplex, nic_role_t role)
371{
372 if ((speed != 10) && (speed != 100) && (speed != 1000))
373 return EINVAL;
374
375 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
376 return EINVAL;
377
378 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
379
380 fibril_mutex_lock(&e1000->ctrl_lock);
381 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
382
383 ctrl |= CTRL_FRCSPD;
384 ctrl |= CTRL_FRCDPLX;
385 ctrl &= ~(CTRL_ASDE);
386
387 if (duplex == NIC_CM_FULL_DUPLEX)
388 ctrl |= CTRL_FD;
389 else
390 ctrl &= ~(CTRL_FD);
391
392 ctrl &= ~(CTRL_SPEED_MASK);
393 if (speed == 1000)
394 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
395 else if (speed == 100)
396 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
397 else
398 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
399
400 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
401
402 fibril_mutex_unlock(&e1000->ctrl_lock);
403
404 e1000_link_restart(e1000);
405
406 return EOK;
407}
408
409/** Enable auto-negotiation
410 *
411 * @param dev Device to update
412 * @param advertisement Ignored on E1000
413 *
414 * @return EOK if advertisement mode set successfully
415 *
416 */
417static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
418{
419 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
420
421 fibril_mutex_lock(&e1000->ctrl_lock);
422
423 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
424
425 ctrl &= ~(CTRL_FRCSPD);
426 ctrl &= ~(CTRL_FRCDPLX);
427 ctrl |= CTRL_ASDE;
428
429 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
430
431 fibril_mutex_unlock(&e1000->ctrl_lock);
432
433 e1000_link_restart(e1000);
434
435 return EOK;
436}
437
438/** Disable auto-negotiation
439 *
440 * @param dev Device to update
441 *
442 * @return EOK
443 *
444 */
445static int e1000_autoneg_disable(ddf_fun_t *dev)
446{
447 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
448
449 fibril_mutex_lock(&e1000->ctrl_lock);
450
451 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
452
453 ctrl |= CTRL_FRCSPD;
454 ctrl |= CTRL_FRCDPLX;
455 ctrl &= ~(CTRL_ASDE);
456
457 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
458
459 fibril_mutex_unlock(&e1000->ctrl_lock);
460
461 e1000_link_restart(e1000);
462
463 return EOK;
464}
465
466/** Restart auto-negotiation
467 *
468 * @param dev Device to update
469 *
470 * @return EOK if advertisement mode set successfully
471 *
472 */
473static int e1000_autoneg_restart(ddf_fun_t *dev)
474{
475 return e1000_autoneg_enable(dev, 0);
476}
477
478/** Get state of acceptance of weird frames
479 *
480 * @param device Device to check
481 * @param[out] mode Current mode
482 *
483 */
484static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
485{
486 e1000_t *e1000 = DRIVER_DATA_DEV(device);
487
488 *mode = 0;
489 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
490 if (rctl & RCTL_SBP)
491 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
492
493 return EOK;
494};
495
496/** Set acceptance of weird frames
497 *
498 * @param device Device to update
499 * @param mode Mode to set
500 *
501 * @return ENOTSUP if the mode is not supported
502 * @return EOK of mode was set
503 *
504 */
505static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
506{
507 e1000_t *e1000 = DRIVER_DATA_DEV(device);
508 int rc = EOK;
509
510 fibril_mutex_lock(&e1000->rx_lock);
511
512 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
513 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
514 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
515
516 if (short_mode && bad_mode)
517 rctl |= RCTL_SBP;
518 else if ((!short_mode) && (!bad_mode))
519 rctl &= ~RCTL_SBP;
520 else
521 rc = ENOTSUP;
522
523 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
524
525 fibril_mutex_unlock(&e1000->rx_lock);
526 return rc;
527};
528
529/** Write receive address to RA registr
530 *
531 * @param e1000 E1000 data structure
532 * @param position RA register position
533 * @param address Ethernet address
534 * @param set_av_bit Set the Addtess Valid bit
535 *
536 */
537static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
538 const nic_address_t * address, bool set_av_bit)
539{
540 uint8_t *mac0 = (uint8_t *) address->address;
541 uint8_t *mac1 = (uint8_t *) address->address + 1;
542 uint8_t *mac2 = (uint8_t *) address->address + 2;
543 uint8_t *mac3 = (uint8_t *) address->address + 3;
544 uint8_t *mac4 = (uint8_t *) address->address + 4;
545 uint8_t *mac5 = (uint8_t *) address->address + 5;
546
547 uint32_t rah;
548 uint32_t ral;
549
550 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
551 rah = ((*mac5) << 8) | ((*mac4));
552
553 if (set_av_bit)
554 rah |= RAH_AV;
555 else
556 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
557
558 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
559 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
560}
561
562/** Disable receive address in RA registr
563 *
564 * Clear Address Valid bit
565 *
566 * @param e1000 E1000 data structure
567 * @param position RA register position
568 *
569 */
570static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
571{
572 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
573 rah = rah & ~RAH_AV;
574 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
575}
576
577/** Clear all unicast addresses from RA registers
578 *
579 * @param e1000 E1000 data structure
580 *
581 */
582static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
583{
584 for (unsigned int ra_num = 1;
585 ra_num <= e1000->unicast_ra_count;
586 ra_num++)
587 e1000_disable_receive_address(e1000, ra_num);
588
589 e1000->unicast_ra_count = 0;
590}
591
592/** Clear all multicast addresses from RA registers
593 *
594 * @param e1000 E1000 data structure
595 *
596 */
597static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
598{
599 unsigned int first_multicast_ra_num =
600 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
601
602 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
603 ra_num >= first_multicast_ra_num;
604 ra_num--)
605 e1000_disable_receive_address(e1000, ra_num);
606
607 e1000->multicast_ra_count = 0;
608}
609
610/** Return receive address filter positions count usable for unicast
611 *
612 * @param e1000 E1000 data structure
613 *
614 * @return receive address filter positions count usable for unicast
615 *
616 */
617static unsigned int get_free_unicast_address_count(e1000_t *e1000)
618{
619 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
620}
621
622/** Return receive address filter positions count usable for multicast
623 *
624 * @param e1000 E1000 data structure
625 *
626 * @return receive address filter positions count usable for multicast
627 *
628 */
629static unsigned int get_free_multicast_address_count(e1000_t *e1000)
630{
631 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
632}
633
634/** Write unicast receive addresses to receive address filter registers
635 *
636 * @param e1000 E1000 data structure
637 * @param addr Pointer to address array
638 * @param addr_cnt Address array count
639 *
640 */
641static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
642 const nic_address_t *addr, size_t addr_cnt)
643{
644 assert(addr_cnt <= get_free_unicast_address_count(e1000));
645
646 nic_address_t *addr_iterator = (nic_address_t *) addr;
647
648 /* ra_num = 0 is primary address */
649 for (unsigned int ra_num = 1;
650 ra_num <= addr_cnt;
651 ra_num++) {
652 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
653 addr_iterator++;
654 }
655}
656
657/** Write multicast receive addresses to receive address filter registers
658 *
659 * @param e1000 E1000 data structure
660 * @param addr Pointer to address array
661 * @param addr_cnt Address array count
662 *
663 */
664static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
665 const nic_address_t *addr, size_t addr_cnt)
666{
667 assert(addr_cnt <= get_free_multicast_address_count(e1000));
668
669 nic_address_t *addr_iterator = (nic_address_t *) addr;
670
671 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
672 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
673 ra_num >= first_multicast_ra_num;
674 ra_num--) {
675 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
676 addr_iterator++;
677 }
678}
679
680/** Disable receiving frames for default address
681 *
682 * @param e1000 E1000 data structure
683 *
684 */
685static void disable_ra0_address_filter(e1000_t *e1000)
686{
687 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
688 rah0 = rah0 & ~RAH_AV;
689 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
690}
691
692/** Enable receiving frames for default address
693 *
694 * @param e1000 E1000 data structure
695 *
696 */
697static void enable_ra0_address_filter(e1000_t *e1000)
698{
699 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
700 rah0 = rah0 | RAH_AV;
701 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
702}
703
704/** Disable unicast promiscuous mode
705 *
706 * @param e1000 E1000 data structure
707 *
708 */
709static void e1000_disable_unicast_promisc(e1000_t *e1000)
710{
711 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
712 rctl = rctl & ~RCTL_UPE;
713 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
714}
715
716/** Enable unicast promiscuous mode
717 *
718 * @param e1000 E1000 data structure
719 *
720 */
721static void e1000_enable_unicast_promisc(e1000_t *e1000)
722{
723 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
724 rctl = rctl | RCTL_UPE;
725 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
726}
727
728/** Disable multicast promiscuous mode
729 *
730 * @param e1000 E1000 data structure
731 *
732 */
733static void e1000_disable_multicast_promisc(e1000_t *e1000)
734{
735 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
736 rctl = rctl & ~RCTL_MPE;
737 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
738}
739
740/** Enable multicast promiscuous mode
741 *
742 * @param e1000 E1000 data structure
743 *
744 */
745static void e1000_enable_multicast_promisc(e1000_t *e1000)
746{
747 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
748 rctl = rctl | RCTL_MPE;
749 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
750}
751
752/** Enable accepting of broadcast frames
753 *
754 * @param e1000 E1000 data structure
755 *
756 */
757static void e1000_enable_broadcast_accept(e1000_t *e1000)
758{
759 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
760 rctl = rctl | RCTL_BAM;
761 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
762}
763
764/** Disable accepting of broadcast frames
765 *
766 * @param e1000 E1000 data structure
767 *
768 */
769static void e1000_disable_broadcast_accept(e1000_t *e1000)
770{
771 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
772 rctl = rctl & ~RCTL_BAM;
773 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
774}
775
776/** Enable VLAN filtering according to VFTA registers
777 *
778 * @param e1000 E1000 data structure
779 *
780 */
781static void e1000_enable_vlan_filter(e1000_t *e1000)
782{
783 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
784 rctl = rctl | RCTL_VFE;
785 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
786}
787
788/** Disable VLAN filtering
789 *
790 * @param e1000 E1000 data structure
791 *
792 */
793static void e1000_disable_vlan_filter(e1000_t *e1000)
794{
795 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
796 rctl = rctl & ~RCTL_VFE;
797 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
798}
799
800/** Set multicast frames acceptance mode
801 *
802 * @param nic NIC device to update
803 * @param mode Mode to set
804 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
805 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
806 *
807 * @return EOK
808 *
809 */
810static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
811 const nic_address_t *addr, size_t addr_cnt)
812{
813 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
814 int rc = EOK;
815
816 fibril_mutex_lock(&e1000->rx_lock);
817
818 switch (mode) {
819 case NIC_MULTICAST_BLOCKED:
820 e1000_clear_multicast_receive_addresses(e1000);
821 e1000_disable_multicast_promisc(e1000);
822 nic_report_hw_filtering(nic, -1, 1, -1);
823 break;
824 case NIC_MULTICAST_LIST:
825 e1000_clear_multicast_receive_addresses(e1000);
826 if (addr_cnt > get_free_multicast_address_count(e1000)) {
827 /*
828 * Future work: fill MTA table
829 * Not strictly neccessary, it only saves some compares
830 * in the NIC library.
831 */
832 e1000_enable_multicast_promisc(e1000);
833 nic_report_hw_filtering(nic, -1, 0, -1);
834 } else {
835 e1000_disable_multicast_promisc(e1000);
836 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
837 nic_report_hw_filtering(nic, -1, 1, -1);
838 }
839 break;
840 case NIC_MULTICAST_PROMISC:
841 e1000_enable_multicast_promisc(e1000);
842 e1000_clear_multicast_receive_addresses(e1000);
843 nic_report_hw_filtering(nic, -1, 1, -1);
844 break;
845 default:
846 rc = ENOTSUP;
847 break;
848 }
849
850 fibril_mutex_unlock(&e1000->rx_lock);
851 return rc;
852}
853
854/** Set unicast frames acceptance mode
855 *
856 * @param nic NIC device to update
857 * @param mode Mode to set
858 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
859 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
860 *
861 * @return EOK
862 *
863 */
864static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
865 const nic_address_t *addr, size_t addr_cnt)
866{
867 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
868 int rc = EOK;
869
870 fibril_mutex_lock(&e1000->rx_lock);
871
872 switch (mode) {
873 case NIC_UNICAST_BLOCKED:
874 disable_ra0_address_filter(e1000);
875 e1000_clear_unicast_receive_addresses(e1000);
876 e1000_disable_unicast_promisc(e1000);
877 nic_report_hw_filtering(nic, 1, -1, -1);
878 break;
879 case NIC_UNICAST_DEFAULT:
880 enable_ra0_address_filter(e1000);
881 e1000_clear_unicast_receive_addresses(e1000);
882 e1000_disable_unicast_promisc(e1000);
883 nic_report_hw_filtering(nic, 1, -1, -1);
884 break;
885 case NIC_UNICAST_LIST:
886 enable_ra0_address_filter(e1000);
887 e1000_clear_unicast_receive_addresses(e1000);
888 if (addr_cnt > get_free_unicast_address_count(e1000)) {
889 e1000_enable_unicast_promisc(e1000);
890 nic_report_hw_filtering(nic, 0, -1, -1);
891 } else {
892 e1000_disable_unicast_promisc(e1000);
893 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
894 nic_report_hw_filtering(nic, 1, -1, -1);
895 }
896 break;
897 case NIC_UNICAST_PROMISC:
898 e1000_enable_unicast_promisc(e1000);
899 enable_ra0_address_filter(e1000);
900 e1000_clear_unicast_receive_addresses(e1000);
901 nic_report_hw_filtering(nic, 1, -1, -1);
902 break;
903 default:
904 rc = ENOTSUP;
905 break;
906 }
907
908 fibril_mutex_unlock(&e1000->rx_lock);
909 return rc;
910}
911
912/** Set broadcast frames acceptance mode
913 *
914 * @param nic NIC device to update
915 * @param mode Mode to set
916 *
917 * @return EOK
918 *
919 */
920static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
921{
922 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
923 int rc = EOK;
924
925 fibril_mutex_lock(&e1000->rx_lock);
926
927 switch (mode) {
928 case NIC_BROADCAST_BLOCKED:
929 e1000_disable_broadcast_accept(e1000);
930 break;
931 case NIC_BROADCAST_ACCEPTED:
932 e1000_enable_broadcast_accept(e1000);
933 break;
934 default:
935 rc = ENOTSUP;
936 break;
937 }
938
939 fibril_mutex_unlock(&e1000->rx_lock);
940 return rc;
941}
942
943/** Check if receiving is enabled
944 *
945 * @param e1000 E1000 data structure
946 *
947 * @return true if receiving is enabled
948 *
949 */
950static bool e1000_is_rx_enabled(e1000_t *e1000)
951{
952 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
953 return true;
954
955 return false;
956}
957
958/** Enable receiving
959 *
960 * @param e1000 E1000 data structure
961 *
962 */
963static void e1000_enable_rx(e1000_t *e1000)
964{
965 /* Set Receive Enable Bit */
966 E1000_REG_WRITE(e1000, E1000_RCTL,
967 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
968}
969
970/** Disable receiving
971 *
972 * @param e1000 E1000 data structure
973 *
974 */
975static void e1000_disable_rx(e1000_t *e1000)
976{
977 /* Clear Receive Enable Bit */
978 E1000_REG_WRITE(e1000, E1000_RCTL,
979 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
980}
981
982/** Set VLAN mask
983 *
984 * @param nic NIC device to update
985 * @param vlan_mask VLAN mask
986 *
987 */
988static void e1000_on_vlan_mask_change(nic_t *nic,
989 const nic_vlan_mask_t *vlan_mask)
990{
991 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
992
993 fibril_mutex_lock(&e1000->rx_lock);
994
995 if (vlan_mask) {
996 /*
997 * Disable receiving, so that frame matching
998 * partially written VLAN is not received.
999 */
1000 bool rx_enabled = e1000_is_rx_enabled(e1000);
1001 if (rx_enabled)
1002 e1000_disable_rx(e1000);
1003
1004 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1005 uint32_t bitmap_part =
1006 ((uint32_t) vlan_mask->bitmap[i]) |
1007 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1008 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1009 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1010 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1011 }
1012
1013 e1000_enable_vlan_filter(e1000);
1014 if (rx_enabled)
1015 e1000_enable_rx(e1000);
1016 } else
1017 e1000_disable_vlan_filter(e1000);
1018
1019 fibril_mutex_unlock(&e1000->rx_lock);
1020}
1021
1022/** Set VLAN mask
1023 *
1024 * @param device E1000 device
1025 * @param tag VLAN tag
1026 *
1027 * @return EOK
1028 * @return ENOTSUP
1029 *
1030 */
1031static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
1032 bool strip)
1033{
1034 /* VLAN CFI bit cannot be set */
1035 if (tag & VLANTAG_CFI)
1036 return ENOTSUP;
1037
1038 /*
1039 * CTRL.VME is neccessary for both strip and add
1040 * but CTRL.VME means stripping tags on receive.
1041 */
1042 if (!strip && add)
1043 return ENOTSUP;
1044
1045 e1000_t *e1000 = DRIVER_DATA_DEV(device);
1046
1047 e1000->vlan_tag = tag;
1048 e1000->vlan_tag_add = add;
1049
1050 fibril_mutex_lock(&e1000->ctrl_lock);
1051
1052 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1053 if (strip)
1054 ctrl |= CTRL_VME;
1055 else
1056 ctrl &= ~CTRL_VME;
1057
1058 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1059
1060 fibril_mutex_unlock(&e1000->ctrl_lock);
1061 return EOK;
1062}
1063
1064/** Fill receive descriptor with new empty buffer
1065 *
1066 * Store frame in e1000->rx_frame_phys
1067 *
1068 * @param nic NIC data stricture
1069 * @param offset Receive descriptor offset
1070 *
1071 */
1072static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1073{
1074 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1075
1076 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1077 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1078
1079 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1080 rx_descriptor->length = 0;
1081 rx_descriptor->checksum = 0;
1082 rx_descriptor->status = 0;
1083 rx_descriptor->errors = 0;
1084 rx_descriptor->special = 0;
1085}
1086
1087/** Clear receive descriptor
1088 *
1089 * @param e1000 E1000 data
1090 * @param offset Receive descriptor offset
1091 *
1092 */
1093static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1094{
1095 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1096 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1097
1098 rx_descriptor->length = 0;
1099 rx_descriptor->checksum = 0;
1100 rx_descriptor->status = 0;
1101 rx_descriptor->errors = 0;
1102 rx_descriptor->special = 0;
1103}
1104
1105/** Clear receive descriptor
1106 *
1107 * @param nic NIC data
1108 * @param offset Receive descriptor offset
1109 *
1110 */
1111static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1112{
1113 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1114
1115 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1116 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1117
1118 tx_descriptor->phys_addr = 0;
1119 tx_descriptor->length = 0;
1120 tx_descriptor->checksum_offset = 0;
1121 tx_descriptor->command = 0;
1122 tx_descriptor->status = 0;
1123 tx_descriptor->checksum_start_field = 0;
1124 tx_descriptor->special = 0;
1125}
1126
1127/** Increment tail pointer for receive or transmit ring
1128 *
1129 * @param tail Old Tail
1130 * @param descriptors_count Ring length
1131 *
1132 * @return New tail
1133 *
1134 */
1135static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1136{
1137 if (tail + 1 == descriptors_count)
1138 return 0;
1139 else
1140 return tail + 1;
1141}
1142
1143/** Receive frames
1144 *
1145 * @param nic NIC data
1146 *
1147 */
1148static void e1000_receive_frames(nic_t *nic)
1149{
1150 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1151
1152 fibril_mutex_lock(&e1000->rx_lock);
1153
1154 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1155 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1156
1157 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1158 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1159
1160 while (rx_descriptor->status & 0x01) {
1161 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1162
1163 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1164 if (frame != NULL) {
1165 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1166 nic_received_frame(nic, frame);
1167 } else {
1168 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1169 }
1170
1171 e1000_fill_new_rx_descriptor(nic, next_tail);
1172
1173 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1174 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1175
1176 rx_descriptor = (e1000_rx_descriptor_t *)
1177 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1178 }
1179
1180 fibril_mutex_unlock(&e1000->rx_lock);
1181}
1182
1183/** Enable E1000 interupts
1184 *
1185 * @param e1000 E1000 data structure
1186 *
1187 */
1188static void e1000_enable_interrupts(e1000_t *e1000)
1189{
1190 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1191}
1192
1193/** Disable E1000 interupts
1194 *
1195 * @param e1000 E1000 data structure
1196 *
1197 */
1198static void e1000_disable_interrupts(e1000_t *e1000)
1199{
1200 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1201}
1202
1203/** Interrupt handler implementation
1204 *
1205 * This function is called from e1000_interrupt_handler()
1206 * and e1000_poll()
1207 *
1208 * @param nic NIC data
1209 * @param icr ICR register value
1210 *
1211 */
1212static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1213{
1214 if (icr & ICR_RXT0)
1215 e1000_receive_frames(nic);
1216}
1217
1218/** Handle device interrupt
1219 *
1220 * @param dev E1000 device
1221 * @param iid IPC call id
1222 * @param icall IPC call structure
1223 *
1224 */
1225static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1226 ipc_call_t *icall)
1227{
1228 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1229 nic_t *nic = NIC_DATA_DEV(dev);
1230 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1231
1232 e1000_interrupt_handler_impl(nic, icr);
1233 e1000_enable_interrupts(e1000);
1234}
1235
1236/** Register interrupt handler for the card in the system
1237 *
1238 * Note: The global irq_reg_mutex is locked because of work with global
1239 * structure.
1240 *
1241 * @param nic Driver data
1242 *
1243 * @return EOK if the handler was registered
1244 * @return Negative error code otherwise
1245 *
1246 */
1247inline static int e1000_register_int_handler(nic_t *nic)
1248{
1249 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1250
1251 /* Lock the mutex in whole driver while working with global structure */
1252 fibril_mutex_lock(&irq_reg_mutex);
1253
1254 e1000_irq_code.cmds[0].addr = e1000->reg_base_virt + E1000_ICR;
1255 e1000_irq_code.cmds[2].addr = e1000->reg_base_virt + E1000_IMC;
1256
1257 int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
1258 e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
1259
1260 fibril_mutex_unlock(&irq_reg_mutex);
1261 return rc;
1262}
1263
1264/** Force receiving all frames in the receive buffer
1265 *
1266 * @param nic NIC data
1267 *
1268 */
1269static void e1000_poll(nic_t *nic)
1270{
1271 assert(nic);
1272
1273 e1000_t *e1000 = nic_get_specific(nic);
1274 assert(e1000);
1275
1276 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1277 e1000_interrupt_handler_impl(nic, icr);
1278}
1279
1280/** Calculates ITR register interrupt from timeval structure
1281 *
1282 * @param period Period
1283 *
1284 */
1285static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1286{
1287 // TODO: use also tv_sec
1288 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1289}
1290
1291/** Set polling mode
1292 *
1293 * @param device Device to set
1294 * @param mode Mode to set
1295 * @param period Period for NIC_POLL_PERIODIC
1296 *
1297 * @return EOK if succeed
1298 * @return ENOTSUP if the mode is not supported
1299 *
1300 */
1301static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1302 const struct timeval *period)
1303{
1304 assert(nic);
1305
1306 e1000_t *e1000 = nic_get_specific(nic);
1307 assert(e1000);
1308
1309 switch (mode) {
1310 case NIC_POLL_IMMEDIATE:
1311 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1312 e1000_enable_interrupts(e1000);
1313 break;
1314 case NIC_POLL_ON_DEMAND:
1315 e1000_disable_interrupts(e1000);
1316 break;
1317 case NIC_POLL_PERIODIC:
1318 assert(period);
1319 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1320 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1321 e1000_enable_interrupts(e1000);
1322 break;
1323 default:
1324 return ENOTSUP;
1325 }
1326
1327 return EOK;
1328}
1329
1330/** Initialize receive registers
1331 *
1332 * @param e1000 E1000 data structure
1333 *
1334 */
1335static void e1000_initialize_rx_registers(e1000_t *e1000)
1336{
1337 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1338 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1339
1340 /* It is not posible to let HW use all descriptors */
1341 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1342
1343 /* Set Broadcast Enable Bit */
1344 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1345}
1346
1347/** Initialize receive structure
1348 *
1349 * @param nic NIC data
1350 *
1351 * @return EOK if succeed
1352 * @return Negative error code otherwise
1353 *
1354 */
1355static int e1000_initialize_rx_structure(nic_t *nic)
1356{
1357 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1358 fibril_mutex_lock(&e1000->rx_lock);
1359
1360 int rc = dmamem_map_anonymous(
1361 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1362 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,
1363 &e1000->rx_ring_virt);
1364 if (rc != EOK)
1365 return rc;
1366
1367 E1000_REG_WRITE(e1000, E1000_RDBAH,
1368 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1369 E1000_REG_WRITE(e1000, E1000_RDBAL,
1370 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1371
1372 e1000->rx_frame_phys =
1373 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1374 e1000->rx_frame_virt =
1375 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1376 if (e1000->rx_frame_phys == NULL || e1000->rx_frame_virt == NULL) {
1377 rc = ENOMEM;
1378 goto error;
1379 }
1380
1381 size_t i;
1382 void *frame_virt;
1383 void *frame_phys;
1384
1385 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1386 rc = dmamem_map_anonymous(
1387 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1388 0, &frame_phys, &frame_virt);
1389 if (rc != EOK)
1390 goto error;
1391
1392 e1000->rx_frame_virt[i] = frame_virt;
1393 e1000->rx_frame_phys[i] = frame_phys;
1394 }
1395
1396 /* Write descriptor */
1397 for (i = 0; i < E1000_RX_FRAME_COUNT; i++)
1398 e1000_fill_new_rx_descriptor(nic, i);
1399
1400 e1000_initialize_rx_registers(e1000);
1401
1402 fibril_mutex_unlock(&e1000->rx_lock);
1403 return EOK;
1404error:
1405 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1406 if (e1000->rx_frame_virt[i] != NULL) {
1407 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1408 e1000->rx_frame_virt[i] = NULL;
1409 e1000->rx_frame_phys[i] = NULL;
1410 }
1411 }
1412 if (e1000->rx_frame_phys != NULL) {
1413 free(e1000->rx_frame_phys);
1414 e1000->rx_frame_phys = NULL;
1415 }
1416 if (e1000->rx_frame_virt != NULL) {
1417 free(e1000->rx_frame_virt);
1418 e1000->rx_frame_phys = NULL;
1419 }
1420 return rc;
1421}
1422
1423/** Uninitialize receive structure
1424 *
1425 * @param nic NIC data
1426 *
1427 */
1428static void e1000_uninitialize_rx_structure(nic_t *nic)
1429{
1430 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1431
1432 /* Write descriptor */
1433 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1434 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1435 e1000->rx_frame_virt[offset] = NULL;
1436 e1000->rx_frame_phys[offset] = NULL;
1437 }
1438
1439 free(e1000->rx_frame_virt);
1440 free(e1000->rx_frame_phys);
1441 e1000->rx_frame_virt = NULL;
1442 e1000->rx_frame_phys = NULL;
1443 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1444}
1445
1446/** Clear receive descriptor ring
1447 *
1448 * @param e1000 E1000 data
1449 *
1450 */
1451static void e1000_clear_rx_ring(e1000_t *e1000)
1452{
1453 /* Write descriptor */
1454 for (unsigned int offset = 0;
1455 offset < E1000_RX_FRAME_COUNT;
1456 offset++)
1457 e1000_clear_rx_descriptor(e1000, offset);
1458}
1459
1460/** Initialize filters
1461 *
1462 * @param e1000 E1000 data
1463 *
1464 */
1465static void e1000_initialize_filters(e1000_t *e1000)
1466{
1467 /* Initialize address filter */
1468 e1000->unicast_ra_count = 0;
1469 e1000->multicast_ra_count = 0;
1470 e1000_clear_unicast_receive_addresses(e1000);
1471}
1472
1473/** Initialize VLAN
1474 *
1475 * @param e1000 E1000 data
1476 *
1477 */
1478static void e1000_initialize_vlan(e1000_t *e1000)
1479{
1480 e1000->vlan_tag_add = false;
1481}
1482
1483/** Fill MAC address from EEPROM to RA[0] register
1484 *
1485 * @param e1000 E1000 data
1486 *
1487 */
1488static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1489{
1490 /* MAC address from eeprom to RA[0] */
1491 nic_address_t address;
1492 e1000_eeprom_get_address(e1000, &address);
1493 e1000_write_receive_address(e1000, 0, &address, true);
1494}
1495
1496/** Initialize other registers
1497 *
1498 * @param dev E1000 data.
1499 *
1500 * @return EOK if succeed
1501 * @return Negative error code otherwise
1502 *
1503 */
1504static void e1000_initialize_registers(e1000_t *e1000)
1505{
1506 E1000_REG_WRITE(e1000, E1000_ITR,
1507 e1000_calculate_itr_interval_from_usecs(
1508 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1509 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1510 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1511 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1512 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1513 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1514 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1515}
1516
1517/** Initialize transmit registers
1518 *
1519 * @param e1000 E1000 data.
1520 *
1521 */
1522static void e1000_initialize_tx_registers(e1000_t *e1000)
1523{
1524 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1525 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1526 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1527
1528 E1000_REG_WRITE(e1000, E1000_TIPG,
1529 10 << TIPG_IPGT_SHIFT |
1530 8 << TIPG_IPGR1_SHIFT |
1531 6 << TIPG_IPGR2_SHIFT);
1532
1533 E1000_REG_WRITE(e1000, E1000_TCTL,
1534 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1535 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1536 TCTL_PSP /* Pad Short Packets */);
1537}
1538
1539/** Initialize transmit structure
1540 *
1541 * @param e1000 E1000 data.
1542 *
1543 */
1544static int e1000_initialize_tx_structure(e1000_t *e1000)
1545{
1546 size_t i;
1547
1548 fibril_mutex_lock(&e1000->tx_lock);
1549
1550 e1000->tx_ring_phys = NULL;
1551 e1000->tx_ring_virt = NULL;
1552 e1000->tx_frame_phys = NULL;
1553 e1000->tx_frame_virt = NULL;
1554
1555 int rc = dmamem_map_anonymous(
1556 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1557 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,
1558 &e1000->tx_ring_virt);
1559 if (rc != EOK)
1560 goto error;
1561
1562 bzero(e1000->tx_ring_virt,
1563 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1564
1565 e1000->tx_frame_phys = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1566 e1000->tx_frame_virt = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1567
1568 if (e1000->tx_frame_phys == NULL || e1000->tx_frame_virt == NULL) {
1569 rc = ENOMEM;
1570 goto error;
1571 }
1572
1573 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1574 rc = dmamem_map_anonymous(
1575 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1576 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1577 if (rc != EOK)
1578 goto error;
1579 }
1580
1581 E1000_REG_WRITE(e1000, E1000_TDBAH,
1582 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1583 E1000_REG_WRITE(e1000, E1000_TDBAL,
1584 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1585
1586 e1000_initialize_tx_registers(e1000);
1587
1588 fibril_mutex_unlock(&e1000->tx_lock);
1589 return EOK;
1590
1591error:
1592 if (e1000->tx_ring_virt != NULL) {
1593 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1594 e1000->tx_ring_virt = NULL;
1595 }
1596
1597 if (e1000->tx_frame_phys != NULL && e1000->tx_frame_virt != NULL) {
1598 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1599 if (e1000->tx_frame_virt[i] != NULL) {
1600 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1601 e1000->tx_frame_virt[i] = NULL;
1602 e1000->tx_frame_phys[i] = NULL;
1603 }
1604 }
1605 }
1606
1607 if (e1000->tx_frame_phys != NULL) {
1608 free(e1000->tx_frame_phys);
1609 e1000->tx_frame_phys = NULL;
1610 }
1611
1612 if (e1000->tx_frame_virt != NULL) {
1613 free(e1000->tx_frame_virt);
1614 e1000->tx_frame_phys = NULL;
1615 }
1616
1617 return rc;
1618}
1619
1620/** Uninitialize transmit structure
1621 *
1622 * @param nic NIC data
1623 *
1624 */
1625static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1626{
1627 size_t i;
1628
1629 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1630 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1631 e1000->tx_frame_virt[i] = NULL;
1632 e1000->tx_frame_phys[i] = NULL;
1633 }
1634
1635 if (e1000->tx_frame_phys != NULL) {
1636 free(e1000->tx_frame_phys);
1637 e1000->tx_frame_phys = NULL;
1638 }
1639
1640 if (e1000->tx_frame_virt != NULL) {
1641 free(e1000->tx_frame_virt);
1642 e1000->tx_frame_phys = NULL;
1643 }
1644 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1645}
1646
1647/** Clear transmit descriptor ring
1648 *
1649 * @param nic NIC data
1650 *
1651 */
1652static void e1000_clear_tx_ring(nic_t *nic)
1653{
1654 /* Write descriptor */
1655 for (unsigned int offset = 0;
1656 offset < E1000_TX_FRAME_COUNT;
1657 offset++)
1658 e1000_clear_tx_descriptor(nic, offset);
1659}
1660
1661/** Enable transmit
1662 *
1663 * @param e1000 E1000 data
1664 *
1665 */
1666static void e1000_enable_tx(e1000_t *e1000)
1667{
1668 /* Set Transmit Enable Bit */
1669 E1000_REG_WRITE(e1000, E1000_TCTL,
1670 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1671}
1672
1673/** Disable transmit
1674 *
1675 * @param e1000 E1000 data
1676 *
1677 */
1678static void e1000_disable_tx(e1000_t *e1000)
1679{
1680 /* Clear Transmit Enable Bit */
1681 E1000_REG_WRITE(e1000, E1000_TCTL,
1682 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1683}
1684
1685/** Reset E1000 device
1686 *
1687 * @param e1000 The E1000 data
1688 *
1689 */
1690static int e1000_reset(nic_t *nic)
1691{
1692 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1693
1694 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1695
1696 /* Wait for the reset */
1697 usleep(20);
1698
1699 /* check if RST_BIT cleared */
1700 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1701 return EINVAL;
1702
1703 e1000_initialize_registers(e1000);
1704 e1000_initialize_rx_registers(e1000);
1705 e1000_initialize_tx_registers(e1000);
1706 e1000_fill_mac_from_eeprom(e1000);
1707 e1000_initialize_filters(e1000);
1708 e1000_initialize_vlan(e1000);
1709
1710 return EOK;
1711}
1712
1713/** Activate the device to receive and transmit frames
1714 *
1715 * @param nic NIC driver data
1716 *
1717 * @return EOK if activated successfully
1718 * @return Error code otherwise
1719 *
1720 */
1721static int e1000_on_activating(nic_t *nic)
1722{
1723 assert(nic);
1724
1725 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1726
1727 fibril_mutex_lock(&e1000->rx_lock);
1728 fibril_mutex_lock(&e1000->tx_lock);
1729 fibril_mutex_lock(&e1000->ctrl_lock);
1730
1731 e1000_enable_interrupts(e1000);
1732
1733 nic_enable_interrupt(nic, e1000->irq);
1734
1735 e1000_clear_rx_ring(e1000);
1736 e1000_enable_rx(e1000);
1737
1738 e1000_clear_tx_ring(nic);
1739 e1000_enable_tx(e1000);
1740
1741 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1742 ctrl |= CTRL_SLU;
1743 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1744
1745 fibril_mutex_unlock(&e1000->ctrl_lock);
1746 fibril_mutex_unlock(&e1000->tx_lock);
1747 fibril_mutex_unlock(&e1000->rx_lock);
1748
1749 return EOK;
1750}
1751
1752/** Callback for NIC_STATE_DOWN change
1753 *
1754 * @param nic NIC driver data
1755 *
1756 * @return EOK if succeed
1757 * @return Error code otherwise
1758 *
1759 */
1760static int e1000_on_down_unlocked(nic_t *nic)
1761{
1762 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1763
1764 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1765 ctrl &= ~CTRL_SLU;
1766 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1767
1768 e1000_disable_tx(e1000);
1769 e1000_disable_rx(e1000);
1770
1771 nic_disable_interrupt(nic, e1000->irq);
1772 e1000_disable_interrupts(e1000);
1773
1774 /*
1775 * Wait for the for the end of all data
1776 * transfers to descriptors.
1777 */
1778 usleep(100);
1779
1780 return EOK;
1781}
1782
1783/** Callback for NIC_STATE_DOWN change
1784 *
1785 * @param nic NIC driver data
1786 *
1787 * @return EOK if succeed
1788 * @return Error code otherwise
1789 *
1790 */
1791static int e1000_on_down(nic_t *nic)
1792{
1793 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1794
1795 fibril_mutex_lock(&e1000->rx_lock);
1796 fibril_mutex_lock(&e1000->tx_lock);
1797 fibril_mutex_lock(&e1000->ctrl_lock);
1798
1799 int rc = e1000_on_down_unlocked(nic);
1800
1801 fibril_mutex_unlock(&e1000->ctrl_lock);
1802 fibril_mutex_unlock(&e1000->tx_lock);
1803 fibril_mutex_unlock(&e1000->rx_lock);
1804
1805 return rc;
1806}
1807
1808/** Callback for NIC_STATE_STOPPED change
1809 *
1810 * @param nic NIC driver data
1811 *
1812 * @return EOK if succeed
1813 * @return Error code otherwise
1814 *
1815 */
1816static int e1000_on_stopping(nic_t *nic)
1817{
1818 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1819
1820 fibril_mutex_lock(&e1000->rx_lock);
1821 fibril_mutex_lock(&e1000->tx_lock);
1822 fibril_mutex_lock(&e1000->ctrl_lock);
1823
1824 int rc = e1000_on_down_unlocked(nic);
1825 if (rc == EOK)
1826 rc = e1000_reset(nic);
1827
1828 fibril_mutex_unlock(&e1000->ctrl_lock);
1829 fibril_mutex_unlock(&e1000->tx_lock);
1830 fibril_mutex_unlock(&e1000->rx_lock);
1831
1832 return rc;
1833}
1834
1835/** Create driver data structure
1836 *
1837 * @return Intialized device data structure or NULL
1838 *
1839 */
1840static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1841{
1842 assert(dev);
1843 assert(!dev->driver_data);
1844
1845 nic_t *nic = nic_create_and_bind(dev);
1846 if (!nic)
1847 return NULL;
1848
1849 e1000_t *e1000 = malloc(sizeof(e1000_t));
1850 if (!e1000) {
1851 nic_unbind_and_destroy(dev);
1852 return NULL;
1853 }
1854
1855 bzero(e1000, sizeof(e1000_t));
1856
1857 nic_set_specific(nic, e1000);
1858 nic_set_send_frame_handler(nic, e1000_send_frame);
1859 nic_set_state_change_handlers(nic, e1000_on_activating,
1860 e1000_on_down, e1000_on_stopping);
1861 nic_set_filtering_change_handlers(nic,
1862 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1863 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1864 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1865
1866 fibril_mutex_initialize(&e1000->ctrl_lock);
1867 fibril_mutex_initialize(&e1000->rx_lock);
1868 fibril_mutex_initialize(&e1000->tx_lock);
1869 fibril_mutex_initialize(&e1000->eeprom_lock);
1870
1871 return e1000;
1872}
1873
1874/** Delete driver data structure
1875 *
1876 * @param data E1000 device data structure
1877 *
1878 */
1879inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1880{
1881 assert(dev);
1882
1883 if (dev->driver_data != NULL)
1884 nic_unbind_and_destroy(dev);
1885}
1886
1887/** Clean up the E1000 device structure.
1888 *
1889 * @param dev Device structure.
1890 *
1891 */
1892static void e1000_dev_cleanup(ddf_dev_t *dev)
1893{
1894 assert(dev);
1895
1896 e1000_delete_dev_data(dev);
1897
1898 if (dev->parent_sess != NULL) {
1899 async_hangup(dev->parent_sess);
1900 dev->parent_sess = NULL;
1901 }
1902}
1903
1904/** Fill the irq and io_addr part of device data structure
1905 *
1906 * The hw_resources must be obtained before calling this function
1907 *
1908 * @param dev Device structure
1909 * @param hw_resources Hardware resources obtained from the parent device
1910 *
1911 * @return EOK if succeed
1912 * @return Negative error code otherwise
1913 *
1914 */
1915static int e1000_fill_resource_info(ddf_dev_t *dev,
1916 const hw_res_list_parsed_t *hw_resources)
1917{
1918 assert(dev != NULL);
1919 assert(hw_resources != NULL);
1920 assert(dev->driver_data != NULL);
1921
1922 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1923
1924 if (hw_resources->irqs.count != 1)
1925 return EINVAL;
1926
1927 e1000->irq = hw_resources->irqs.irqs[0];
1928 e1000->reg_base_phys =
1929 MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
1930
1931 return EOK;
1932}
1933
1934/** Obtain information about hardware resources of the device
1935 *
1936 * The device must be connected to the parent
1937 *
1938 * @param dev Device structure
1939 *
1940 * @return EOK if succeed
1941 * @return Negative error code otherwise
1942 *
1943 */
1944static int e1000_get_resource_info(ddf_dev_t *dev)
1945{
1946 assert(dev != NULL);
1947 assert(NIC_DATA_DEV(dev) != NULL);
1948
1949 hw_res_list_parsed_t hw_res_parsed;
1950 hw_res_list_parsed_init(&hw_res_parsed);
1951
1952 /* Get hw resources form parent driver */
1953 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1954 if (rc != EOK)
1955 return rc;
1956
1957 /* Fill resources information to the device */
1958 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1959 hw_res_list_parsed_clean(&hw_res_parsed);
1960
1961 return rc;
1962}
1963
1964/** Initialize the E1000 device structure
1965 *
1966 * @param dev Device information
1967 *
1968 * @return EOK if succeed
1969 * @return Negative error code otherwise
1970 *
1971 */
1972static int e1000_device_initialize(ddf_dev_t *dev)
1973{
1974 /* Allocate driver data for the device. */
1975 e1000_t *e1000 = e1000_create_dev_data(dev);
1976 if (e1000 == NULL) {
1977 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1978 return ENOMEM;
1979 }
1980
1981 /* Obtain and fill hardware resources info */
1982 int rc = e1000_get_resource_info(dev);
1983 if (rc != EOK) {
1984 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
1985 e1000_dev_cleanup(dev);
1986 return rc;
1987 }
1988
1989 uint16_t device_id;
1990 rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
1991 &device_id);
1992 if (rc != EOK) {
1993 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
1994 e1000_dev_cleanup(dev);
1995 return rc;
1996 }
1997
1998 e1000_board_t board;
1999 switch (device_id) {
2000 case 0x100e:
2001 case 0x1015:
2002 case 0x1016:
2003 case 0x1017:
2004 board = E1000_82540;
2005 break;
2006 case 0x1013:
2007 case 0x1018:
2008 case 0x1078:
2009 board = E1000_82541;
2010 break;
2011 case 0x1076:
2012 case 0x1077:
2013 case 0x107c:
2014 board = E1000_82541REV2;
2015 break;
2016 case 0x100f:
2017 case 0x1011:
2018 case 0x1026:
2019 case 0x1027:
2020 case 0x1028:
2021 board = E1000_82545;
2022 break;
2023 case 0x1010:
2024 case 0x1012:
2025 case 0x101d:
2026 case 0x1079:
2027 case 0x107a:
2028 case 0x107b:
2029 board = E1000_82546;
2030 break;
2031 case 0x1019:
2032 case 0x101a:
2033 board = E1000_82547;
2034 break;
2035 case 0x10b9:
2036 board = E1000_82572;
2037 break;
2038 case 0x1096:
2039 board = E1000_80003ES2;
2040 break;
2041 default:
2042 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2043 device_id);
2044 e1000_dev_cleanup(dev);
2045 return ENOTSUP;
2046 }
2047
2048 switch (board) {
2049 case E1000_82540:
2050 case E1000_82541:
2051 case E1000_82541REV2:
2052 case E1000_82545:
2053 case E1000_82546:
2054 case E1000_82572:
2055 e1000->info.eerd_start = 0x01;
2056 e1000->info.eerd_done = 0x10;
2057 e1000->info.eerd_address_offset = 8;
2058 e1000->info.eerd_data_offset = 16;
2059 break;
2060 case E1000_82547:
2061 case E1000_80003ES2:
2062 e1000->info.eerd_start = 0x01;
2063 e1000->info.eerd_done = 0x02;
2064 e1000->info.eerd_address_offset = 2;
2065 e1000->info.eerd_data_offset = 16;
2066 break;
2067 }
2068
2069 return EOK;
2070}
2071
2072/** Enable the I/O ports of the device.
2073 *
2074 * @param dev E1000 device.
2075 *
2076 * @return EOK if successed
2077 * @return Negative error code otherwise
2078 *
2079 */
2080static int e1000_pio_enable(ddf_dev_t *dev)
2081{
2082 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2083
2084 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2085 &e1000->reg_base_virt);
2086 if (rc != EOK)
2087 return EADDRNOTAVAIL;
2088
2089 return EOK;
2090}
2091
2092/** Probe and initialize the newly added device.
2093 *
2094 * @param dev E1000 device.
2095 *
2096 */
2097int e1000_dev_add(ddf_dev_t *dev)
2098{
2099 assert(dev);
2100
2101 /* Initialize device structure for E1000 */
2102 int rc = e1000_device_initialize(dev);
2103 if (rc != EOK)
2104 return rc;
2105
2106 /* Device initialization */
2107 nic_t *nic = dev->driver_data;
2108 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2109
2110 /* Map registers */
2111 rc = e1000_pio_enable(dev);
2112 if (rc != EOK)
2113 goto err_destroy;
2114
2115 e1000_initialize_registers(e1000);
2116 rc = e1000_initialize_tx_structure(e1000);
2117 if (rc != EOK)
2118 goto err_pio;
2119
2120 fibril_mutex_lock(&e1000->rx_lock);
2121
2122 e1000_fill_mac_from_eeprom(e1000);
2123 e1000_initialize_filters(e1000);
2124
2125 fibril_mutex_unlock(&e1000->rx_lock);
2126
2127 e1000_initialize_vlan(e1000);
2128
2129 rc = nic_register_as_ddf_fun(nic, &e1000_dev_ops);
2130 if (rc != EOK)
2131 goto err_tx_structure;
2132
2133 rc = e1000_register_int_handler(nic);
2134 if (rc != EOK)
2135 goto err_tx_structure;
2136
2137 rc = nic_connect_to_services(nic);
2138 if (rc != EOK)
2139 goto err_irq;
2140
2141 rc = e1000_initialize_rx_structure(nic);
2142 if (rc != EOK)
2143 goto err_irq;
2144
2145 nic_address_t e1000_address;
2146 e1000_get_address(e1000, &e1000_address);
2147 rc = nic_report_address(nic, &e1000_address);
2148 if (rc != EOK)
2149 goto err_rx_structure;
2150
2151 struct timeval period;
2152 period.tv_sec = 0;
2153 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2154 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2155 if (rc != EOK)
2156 goto err_rx_structure;
2157
2158 return EOK;
2159
2160err_rx_structure:
2161 e1000_uninitialize_rx_structure(nic);
2162err_irq:
2163 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
2164err_tx_structure:
2165 e1000_uninitialize_tx_structure(e1000);
2166err_pio:
2167 // TODO: e1000_pio_disable(dev);
2168err_destroy:
2169 e1000_dev_cleanup(dev);
2170 return rc;
2171}
2172
2173/** Read 16-bit value from EEPROM of E1000 adapter
2174 *
2175 * Read using the EERD register.
2176 *
2177 * @param device E1000 device
2178 * @param eeprom_address 8-bit EEPROM address
2179 *
2180 * @return 16-bit value from EEPROM
2181 *
2182 */
2183static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2184{
2185 fibril_mutex_lock(&e1000->eeprom_lock);
2186
2187 /* Write address and START bit to EERD register */
2188 uint32_t write_data = e1000->info.eerd_start |
2189 (((uint32_t) eeprom_address) <<
2190 e1000->info.eerd_address_offset);
2191 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2192
2193 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2194 while ((eerd & e1000->info.eerd_done) == 0) {
2195 usleep(1);
2196 eerd = E1000_REG_READ(e1000, E1000_EERD);
2197 }
2198
2199 fibril_mutex_unlock(&e1000->eeprom_lock);
2200
2201 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2202}
2203
2204/** Get MAC address of the E1000 adapter
2205 *
2206 * @param device E1000 device
2207 * @param address Place to store the address
2208 * @param max_len Maximal addresss length to store
2209 *
2210 * @return EOK if succeed
2211 * @return Negative error code otherwise
2212 *
2213 */
2214static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2215{
2216 fibril_mutex_lock(&e1000->rx_lock);
2217
2218 uint8_t *mac0_dest = (uint8_t *) address->address;
2219 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2220 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2221 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2222 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2223 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2224
2225 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2226 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2227
2228 *mac0_dest = (uint8_t) ral;
2229 *mac1_dest = (uint8_t) (ral >> 8);
2230 *mac2_dest = (uint8_t) (ral >> 16);
2231 *mac3_dest = (uint8_t) (ral >> 24);
2232 *mac4_dest = (uint8_t) rah;
2233 *mac5_dest = (uint8_t) (rah >> 8);
2234
2235 fibril_mutex_unlock(&e1000->rx_lock);
2236 return EOK;
2237};
2238
2239/** Set card MAC address
2240 *
2241 * @param device E1000 device
2242 * @param address Address
2243 *
2244 * @return EOK if succeed
2245 * @return Negative error code otherwise
2246 */
2247static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
2248{
2249 nic_t *nic = NIC_DATA_DEV(dev);
2250 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2251
2252 fibril_mutex_lock(&e1000->rx_lock);
2253 fibril_mutex_lock(&e1000->tx_lock);
2254
2255 int rc = nic_report_address(nic, addr);
2256 if (rc == EOK)
2257 e1000_write_receive_address(e1000, 0, addr, false);
2258
2259 fibril_mutex_unlock(&e1000->tx_lock);
2260 fibril_mutex_unlock(&e1000->rx_lock);
2261
2262 return rc;
2263}
2264
2265static void e1000_eeprom_get_address(e1000_t *e1000,
2266 nic_address_t *address)
2267{
2268 uint16_t *mac0_dest = (uint16_t *) address->address;
2269 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2270 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2271
2272 *mac0_dest = e1000_eeprom_read(e1000, 0);
2273 *mac2_dest = e1000_eeprom_read(e1000, 1);
2274 *mac4_dest = e1000_eeprom_read(e1000, 2);
2275}
2276
2277/** Send frame
2278 *
2279 * @param nic NIC driver data structure
2280 * @param data Frame data
2281 * @param size Frame size in bytes
2282 *
2283 * @return EOK if succeed
2284 * @return Error code in the case of error
2285 *
2286 */
2287static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2288{
2289 assert(nic);
2290
2291 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2292 fibril_mutex_lock(&e1000->tx_lock);
2293
2294 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2295 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2296 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2297
2298 bool descriptor_available = false;
2299
2300 /* Descriptor never used */
2301 if (tx_descriptor_addr->length == 0)
2302 descriptor_available = true;
2303
2304 /* Descriptor done */
2305 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2306 descriptor_available = true;
2307
2308 if (!descriptor_available) {
2309 /* Frame lost */
2310 fibril_mutex_unlock(&e1000->tx_lock);
2311 return;
2312 }
2313
2314 memcpy(e1000->tx_frame_virt[tdt], data, size);
2315
2316 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2317 tx_descriptor_addr->length = size;
2318
2319 /*
2320 * Report status to STATUS.DD (descriptor done),
2321 * add ethernet CRC, end of packet.
2322 */
2323 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2324 TXDESCRIPTOR_COMMAND_IFCS |
2325 TXDESCRIPTOR_COMMAND_EOP;
2326
2327 tx_descriptor_addr->checksum_offset = 0;
2328 tx_descriptor_addr->status = 0;
2329 if (e1000->vlan_tag_add) {
2330 tx_descriptor_addr->special = e1000->vlan_tag;
2331 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2332 } else
2333 tx_descriptor_addr->special = 0;
2334
2335 tx_descriptor_addr->checksum_start_field = 0;
2336
2337 tdt++;
2338 if (tdt == E1000_TX_FRAME_COUNT)
2339 tdt = 0;
2340
2341 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2342
2343 fibril_mutex_unlock(&e1000->tx_lock);
2344}
2345
2346int main(void)
2347{
2348 int rc = nic_driver_init(NAME);
2349 if (rc != EOK)
2350 return rc;
2351
2352 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2353 &e1000_nic_iface);
2354
2355 ddf_log_init(NAME, LVL_ERROR);
2356 ddf_msg(LVL_NOTE, "HelenOS E1000 driver started");
2357 return ddf_driver_main(&e1000_driver);
2358}
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