source: mainline/uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c@ 19acf24

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 19acf24 was 19acf24, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

rootamdm37x: Print Core clock and l3 interface clock values.
  • Property mode set to 100644
File size: 17.6 KB
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1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @defgroup root_amdm37x TI AM/DM37x platform driver.
31 * @brief HelenOS TI AM/DM37x platform driver.
32 * @{
33 */
34
35/** @file
36 */
37#define _DDF_DATA_IMPLANT
38
39#define DEBUG_CM 1
40
41#include <ddf/driver.h>
42#include <ddf/log.h>
43#include <errno.h>
44#include <ops/hw_res.h>
45#include <stdio.h>
46#include <ddi.h>
47
48#include "uhh.h"
49#include "usbtll.h"
50
51#include "cm/core.h"
52#include "cm/clock_control.h"
53#include "cm/usbhost.h"
54#include "cm/mpu.h"
55#include "cm/iva2.h"
56
57#include "prm/clock_control.h"
58
59#define NAME "rootamdm37x"
60
61typedef struct {
62 uhh_regs_t *uhh;
63 tll_regs_t *tll;
64 struct {
65 mpu_cm_regs_t *mpu;
66 iva2_cm_regs_t *iva2;
67 core_cm_regs_t *core;
68 clock_control_cm_regs_t *clocks;
69 usbhost_cm_regs_t *usbhost;
70 } cm;
71 struct {
72 clock_control_prm_regs_t *clocks;
73 } prm;
74} amdm37x_t;
75
76static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write)
77{
78 printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ",
79 (place - base) + data, place, val);
80}
81
82static int amdm37x_hw_access_init(amdm37x_t *device)
83{
84 assert(device);
85 int ret = EOK;
86
87 ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
88 (void**)&device->cm.usbhost);
89 if (ret != EOK)
90 return ret;
91
92 ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
93 (void**)&device->cm.core);
94 if (ret != EOK)
95 return ret;
96
97 ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS,
98 CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks);
99 if (ret != EOK)
100 return ret;
101
102 ret = pio_enable((void*)MPU_CM_BASE_ADDRESS,
103 MPU_CM_SIZE, (void**)&device->cm.mpu);
104 if (ret != EOK)
105 return ret;
106
107 ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS,
108 IVA2_CM_SIZE, (void**)&device->cm.iva2);
109 if (ret != EOK)
110 return ret;
111
112 ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS,
113 CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks);
114 if (ret != EOK)
115 return ret;
116
117 ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS,
118 AMDM37x_USBTLL_SIZE, (void**)&device->tll);
119 if (ret != EOK)
120 return ret;
121
122 ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS,
123 AMDM37x_UHH_SIZE, (void**)&device->uhh);
124 if (ret != EOK)
125 return ret;
126
127 if (DEBUG_CM) {
128 pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS);
129 pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS);
130 pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS);
131 pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS);
132 pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS);
133 pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS);
134 pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
135 pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS);
136 }
137 return EOK;
138}
139
140
141
142/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
143 * @param device Register map.
144 *
145 * The idea is to get all DPLLs running and make hw control their power mode,
146 * based on the module requirements (module ICLKs and FCLKs).
147 */
148static void dpll_on_autoidle(amdm37x_t *device)
149{
150 assert(device);
151 /* Get SYS_CLK value, it is used as reference clock by all DPLLs,
152 * NFI who sets this or why it is set to specific value. */
153 const unsigned base_clk = pio_read_32(&device->prm.clocks->clksel)
154 & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
155 const unsigned base_freq = sys_clk_freq_kHz(base_clk);
156 ddf_msg(LVL_DEBUG, "Base frequency: %d.%dMhz",
157 base_freq / 1000, base_freq % 1000);
158
159
160 /* DPLL1 provides MPU(CPU) clock.
161 * It uses SYS_CLK as reference clock and core clock (DPLL3) as
162 * high frequency bypass (MPU then runs on L3 interconnect freq).
163 * It should be setup by fw or u-boot.*/
164 mpu_cm_regs_t *mpu = device->cm.mpu;
165
166 /* Current MPU frequency. */
167 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
168 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
169 /* DPLL active and locked */
170 const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
171 const unsigned multiplier =
172 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
173 >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
174 const unsigned divisor =
175 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
176 >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
177 const unsigned divisor2 =
178 (pio_read_32(&mpu->clksel2_pll)
179 & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
180 if (multiplier && divisor && divisor2) {
181 const unsigned freq =
182 ((base_freq / divisor) * multiplier) / divisor2;
183 ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
184 freq / 1000, freq % 1000);
185 } else {
186 ddf_msg(LVL_WARN, "Frequency divisor and/or "
187 "multiplier value invalid: %d %d %d",
188 multiplier, divisor, divisor2);
189 }
190 } else {
191 /* DPLL in LP bypass mode */
192 const unsigned divisor =
193 MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
194 pio_read_32(&mpu->clksel1_pll));
195 ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
196 " CORE CLK / %d MHz", divisor);
197 }
198 } else {
199 ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
200 }
201 // TODO: Enable this (automatic MPU downclocking):
202#if 0
203 /* Enable low power bypass mode, this will take effect the next lock or
204 * relock sequence. */
205 //TODO: We might need to force re-lock after enabling this
206 pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
207 /* Enable automatic relocking */
208 pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
209#endif
210
211 /* DPLL2 provides IVA(video acceleration) clock.
212 * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
213 * high frequency bypass (IVA runs on L3 freq).
214 */
215 // TODO: We can probably turn this off entirely. IVA is left unused.
216 /* Enable low power bypass mode, this will take effect the next lock or
217 * relock sequence. */
218 //TODO: We might need to force re-lock after enabling this
219 pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
220 /* Enable automatic relocking */
221 pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
222
223 /* DPLL3 provides tons of clocks:
224 * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
225 * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
226 * bypass. It should be setup by fw or u-boot as it controls critical
227 * interconnects.
228 */
229 if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
230 /* DPLL active and locked */
231 const uint32_t reg =
232 pio_read_32(&device->cm.clocks->clksel1_pll);
233 const unsigned multiplier =
234 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
235 const unsigned divisor =
236 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
237 const unsigned divisor2 =
238 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
239 if (multiplier && divisor && divisor2) {
240 const unsigned freq =
241 ((base_freq / divisor) * multiplier) / divisor2;
242 ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
243 freq / 1000, freq % 1000);
244 const unsigned l3_div =
245 pio_read_32(&device->cm.core->clksel)
246 & CORE_CM_CLKSEL_CLKSEL_L3_MASK;
247 if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
248 l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
249 ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
250 (freq / l3_div) / 1000,
251 (freq / l3_div) % 1000);
252 } else {
253 ddf_msg(LVL_WARN,"L3 interface clock divisor is"
254 " invalid: %d", l3_div);
255 }
256 } else {
257 ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
258 "multiplier value invalid: %d %d %d",
259 multiplier, divisor, divisor2);
260 }
261 } else {
262 ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
263 " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
264 }
265
266 /* Set DPLL3 to automatic to save power */
267 pio_change_32(&device->cm.clocks->autoidle_pll,
268 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
269 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
270
271 /* DPLL4 provides peripheral domain clocks:
272 * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
273 * It uses SYS_CLK as reference clock and low frequency bypass.
274 * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
275 * we can probably turn this off entirely (DSS is still non-functional).
276 */
277 /* Set DPLL4 to automatic to save power */
278 pio_change_32(&device->cm.clocks->autoidle_pll,
279 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
280 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
281
282 /* DPLL5 provide peripheral domain clocks: 120M_FCLK.
283 * It uses SYS_CLK as reference clock and low frequency bypass.
284 * 120M clock is used by HS USB and USB TLL.
285 */
286 // TODO setup DPLL5
287 /* Set DPLL5 to automatic to save power */
288 pio_change_32(&device->cm.clocks->autoidle2_pll,
289 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
290 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
291}
292
293/** Enable/disable function and interface clocks for USBTLL and USBHOST.
294 * @param device Register map.
295 * @param on True to swoitch clocks on.
296 */
297static void usb_clocks_enable(amdm37x_t *device, bool on)
298{
299 if (on) {
300 /* Enable interface and function clock for USB TLL */
301 pio_set_32(&device->cm.core->fclken3,
302 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
303 pio_set_32(&device->cm.core->iclken3,
304 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
305
306 /* Enable interface and function clock for USB hosts */
307 pio_set_32(&device->cm.usbhost->fclken,
308 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
309 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
310 pio_set_32(&device->cm.usbhost->iclken,
311 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
312
313 if (DEBUG_CM) {
314 printf("DPLL5 (and everything else) should be on: %"
315 PRIx32" %"PRIx32".\n",
316 pio_read_32(&device->cm.clocks->idlest_ckgen),
317 pio_read_32(&device->cm.clocks->idlest2_ckgen));
318 }
319 } else {
320 /* Disable interface and function clock for USB hosts */
321 pio_clear_32(&device->cm.usbhost->iclken,
322 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
323 pio_clear_32(&device->cm.usbhost->fclken,
324 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
325 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
326
327 /* Disable interface and function clock for USB TLL */
328 pio_clear_32(&device->cm.core->iclken3,
329 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
330 pio_clear_32(&device->cm.core->fclken3,
331 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
332 }
333}
334
335/** Initialize USB TLL port connections.
336 *
337 * Different modes are on page 3312 of the Manual Figure 22-34.
338 * Select mode than can operate in FS/LS.
339 */
340static int usb_tll_init(amdm37x_t *device)
341{
342 /* Reset USB TLL */
343 pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
344 ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
345 while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG));
346 ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
347
348 /* Setup idle mode (smart idle) */
349 pio_change_32(&device->tll->sysconfig,
350 TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
351 TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
352
353 /* Smart idle for UHH */
354 pio_change_32(&device->uhh->sysconfig,
355 UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
356 UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
357
358 /* Set all ports to go through TLL(UTMI)
359 * Direct connection can only work in HS mode */
360 pio_set_32(&device->uhh->hostconfig,
361 UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
362 UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
363 UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
364
365 /* What is this? */
366 pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
367
368 for (unsigned i = 0; i < 3; ++i) {
369 /* Serial mode is the only one capable of FS/LS operation.
370 * Select FS/LS mode, no idea what the difference is
371 * one of bidirectional modes might be good choice
372 * 2 = 3pin bidi phy. */
373 pio_change_32(&device->tll->channel_conf[i],
374 TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
375 TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
376 TLL_CHANNEL_CONF_CHANMODE_MASK |
377 TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
378 }
379 return EOK;
380}
381
382typedef struct {
383 hw_resource_list_t hw_resources;
384} rootamdm37x_fun_t;
385
386#define OHCI_BASE_ADDRESS 0x48064400
387#define OHCI_SIZE 1024
388#define EHCI_BASE_ADDRESS 0x48064800
389#define EHCI_SIZE 1024
390
391static hw_resource_t ohci_res[] = {
392 {
393 .type = MEM_RANGE,
394 /* See amdm37x TRM page. 3316 for these values */
395 .res.io_range = {
396 .address = OHCI_BASE_ADDRESS,
397 .size = OHCI_SIZE,
398 .endianness = LITTLE_ENDIAN
399 },
400 },
401 {
402 .type = INTERRUPT,
403 .res.interrupt = { .irq = 76 },
404 },
405};
406
407static const rootamdm37x_fun_t ohci = {
408 .hw_resources = {
409 .resources = ohci_res,
410 .count = sizeof(ohci_res)/sizeof(ohci_res[0]),
411 }
412};
413
414static hw_resource_t ehci_res[] = {
415 {
416 .type = MEM_RANGE,
417 /* See amdm37x TRM page. 3316 for these values */
418 .res.io_range = {
419 .address = EHCI_BASE_ADDRESS,
420 .size = EHCI_SIZE,
421 .endianness = LITTLE_ENDIAN
422 },
423 },
424 {
425 .type = INTERRUPT,
426 .res.interrupt = { .irq = 77 },
427 },
428};
429
430static const rootamdm37x_fun_t ehci = {
431 .hw_resources = {
432 .resources = ehci_res,
433 .count = sizeof(ehci_res) / sizeof(ehci_res[0]),
434 }
435};
436
437static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode);
438static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun);
439
440static hw_res_ops_t fun_hw_res_ops = {
441 .get_resource_list = &rootamdm37x_get_resources,
442 .enable_interrupt = &rootamdm37x_enable_interrupt,
443};
444
445static ddf_dev_ops_t rootamdm37x_fun_ops =
446{
447 .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops
448};
449
450static bool rootamdm37x_add_fun(ddf_dev_t *dev, const char *name,
451 const char *str_match_id, const rootamdm37x_fun_t *fun)
452{
453 ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name);
454
455 /* Create new device function. */
456 ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, name);
457 if (fnode == NULL)
458 return ENOMEM;
459
460
461 /* Add match id */
462 if (ddf_fun_add_match_id(fnode, str_match_id, 100) != EOK) {
463 ddf_fun_destroy(fnode);
464 return false;
465 }
466
467 /* Set provided operations to the device. */
468 ddf_fun_data_implant(fnode, (void*)fun);
469 ddf_fun_set_ops(fnode, &rootamdm37x_fun_ops);
470
471 /* Register function. */
472 if (ddf_fun_bind(fnode) != EOK) {
473 ddf_msg(LVL_ERROR, "Failed binding function %s.", name);
474 // TODO This will try to free our data!
475 ddf_fun_destroy(fnode);
476 return false;
477 }
478
479 return true;
480}
481
482/** Add the root device.
483 *
484 * @param dev Device which is root of the whole device tree
485 * (both of HW and pseudo devices).
486 *
487 * @return Zero on success, negative error number otherwise.
488 *
489 */
490static int rootamdm37x_dev_add(ddf_dev_t *dev)
491{
492 assert(dev);
493 amdm37x_t *device = ddf_dev_data_alloc(dev, sizeof(amdm37x_t));
494 if (!device)
495 return ENOMEM;
496 int ret = amdm37x_hw_access_init(device);
497 if (ret != EOK) {
498 ddf_msg(LVL_FATAL, "Failed to setup hw access!.\n");
499 return ret;
500 }
501
502 /* Set dplls to ON and automatic */
503 dpll_on_autoidle(device);
504
505 /* Enable function and interface clocks */
506 usb_clocks_enable(device, true);
507
508 /* Init TLL */
509 ret = usb_tll_init(device);
510 if (ret != EOK) {
511 ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n");
512 usb_clocks_enable(device, false);
513 return ret;
514 }
515
516 /* Register functions */
517 if (!rootamdm37x_add_fun(dev, "ohci", "usb/host=ohci", &ohci))
518 ddf_msg(LVL_ERROR, "Failed to add OHCI function for "
519 "BeagleBoard-xM platform.");
520 if (!rootamdm37x_add_fun(dev, "ehci", "usb/host=ehci", &ehci))
521 ddf_msg(LVL_ERROR, "Failed to add EHCI function for "
522 "BeagleBoard-xM platform.");
523
524 return EOK;
525}
526
527/** The root device driver's standard operations. */
528static driver_ops_t rootamdm37x_ops = {
529 .dev_add = &rootamdm37x_dev_add
530};
531
532/** The root device driver structure. */
533static driver_t rootamdm37x_driver = {
534 .name = NAME,
535 .driver_ops = &rootamdm37x_ops
536};
537
538static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode)
539{
540 rootamdm37x_fun_t *fun = ddf_fun_data_get(fnode);
541 assert(fun != NULL);
542 return &fun->hw_resources;
543}
544
545static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun)
546{
547 /* TODO */
548 return false;
549}
550
551int main(int argc, char *argv[])
552{
553 printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME);
554 ddf_log_init(NAME);
555 return ddf_driver_main(&rootamdm37x_driver);
556}
557
558/**
559 * @}
560 */
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