| 1 | /*
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| 2 | * Copyright (c) 2013 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup genarch
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| 29 | * @{
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| 30 | */
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| 31 | /**
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| 32 | * @file
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| 33 | * @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler.
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| 34 | */
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| 35 |
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| 36 | #ifndef AMDM37x_DISPC_REGS_H_
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| 37 | #define AMDM37x_DISPC_REGS_H_
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| 38 |
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| 39 | /* AMDM37x TRM p. 1813 */
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| 40 | #define AMDM37x_DISPC_BASE_ADDRESS 0x48050400
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| 41 | #define AMDM37x_DISPC_SIZE 1024
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| 42 |
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| 43 | #include <macros.h>
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| 44 |
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| 45 | typedef struct {
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| 46 | const ioport32_t revision;
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| 47 | #define AMDM37X_DISPC_REVISION_MASK 0xff
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| 48 |
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| 49 | PADD32[3];
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| 50 | ioport32_t sysconfig;
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| 51 | #define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
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| 52 | #define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
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| 53 | #define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2)
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| 54 | #define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x3
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| 55 | #define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 3
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| 56 | #define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x3
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| 57 | #define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 8
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| 58 | #define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x3
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| 59 | #define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 12
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| 60 |
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| 61 | const ioport32_t sysstatus;
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| 62 | #define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0)
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| 63 |
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| 64 | ioport32_t irqstatus;
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| 65 | ioport32_t irqenable;
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| 66 | #define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0)
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| 67 | #define AMDM37X_DISPC_IRQ_VSYNC_FLAG (1 << 1)
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| 68 | #define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2)
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| 69 | #define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3)
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| 70 | #define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4)
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| 71 | #define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5)
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| 72 | #define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6)
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| 73 | #define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7)
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| 74 | #define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8)
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| 75 | #define AMDM37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9)
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| 76 | #define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10)
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| 77 | #define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11)
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| 78 | #define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12)
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| 79 | #define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13)
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| 80 | #define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14)
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| 81 | #define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15)
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| 82 | #define AMDM37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16)
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| 83 |
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| 84 | PADD32[8];
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| 85 | ioport32_t control;
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| 86 | #define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0)
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| 87 | #define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1)
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| 88 | #define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2)
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| 89 | #define AMDM37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3)
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| 90 | #define AMDM37X_DISPC_CONTROL_M8B_FLAG (1 << 4)
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| 91 | #define AMDM37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5)
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| 92 | #define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6)
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| 93 | #define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7)
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| 94 | #define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK 0x3
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| 95 | #define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8
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| 96 | #define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B 0
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| 97 | #define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B 1
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| 98 | #define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B 2
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| 99 | #define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B 3
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| 100 | #define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11)
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| 101 | #define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12)
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| 102 | #define AMDM37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13)
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| 103 | #define AMDM37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14)
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| 104 | #define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15)
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| 105 | #define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16)
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| 106 | #define AMDM37X_DISPC_CONTROL_HT_MASK 0x7
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| 107 | #define AMDM37X_DISPC_CONTROL_HT_SHIFT 17
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| 108 | #define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20)
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| 109 | #define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3
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| 110 | #define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21
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| 111 | #define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3
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| 112 | #define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23
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| 113 | #define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3
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| 114 | #define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25
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| 115 | #define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27)
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| 116 | #define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28)
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| 117 | #define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29)
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| 118 | #define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3
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| 119 | #define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 30
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| 120 |
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| 121 | ioport32_t config;
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| 122 | #define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0)
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| 123 | #define AMDM37X_DISPC_CONFIG_LOADMODE_MASK 0x3
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| 124 | #define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT 1
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| 125 | #define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0
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| 126 | #define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1
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| 127 | #define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2
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| 128 | #define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3
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| 129 | #define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3)
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| 130 | #define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4)
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| 131 | #define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5)
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| 132 | #define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6)
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| 133 | #define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7)
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| 134 | #define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8)
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| 135 | #define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9)
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| 136 | #define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10)
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| 137 | #define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11)
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| 138 | #define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12)
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| 139 | #define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13)
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| 140 | #define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14)
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| 141 | #define AMDM37X_DISPC_CONFIG_CPR_FLAG (1 << 15)
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| 142 | #define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16)
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| 143 | #define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17)
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| 144 | #define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18)
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| 145 | #define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19)
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| 146 |
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| 147 | PADD32[1];
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| 148 | ioport32_t default_color[2];
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| 149 | ioport32_t trans_color[2];
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| 150 | #define AMDM37X_DISPC_COLOR_MASK 0xffffff
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| 151 |
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| 152 | const ioport32_t line_status;
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| 153 | ioport32_t line_number;
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| 154 | #define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff
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| 155 |
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| 156 | ioport32_t timing_h;
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| 157 | #define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff
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| 158 | #define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0
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| 159 | #define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff
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| 160 | #define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8
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| 161 | #define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff
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| 162 | #define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20
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| 163 |
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| 164 | ioport32_t timing_v;
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| 165 | #define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff
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| 166 | #define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0
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| 167 | #define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff
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| 168 | #define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8
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| 169 | #define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff
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| 170 | #define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20
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| 171 |
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| 172 | ioport32_t pol_freq;
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| 173 | #define AMDM37X_DISPC_POL_FREQ_ACB_MASK 0xff
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| 174 | #define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0
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| 175 | #define AMDM37X_DISPC_POL_FREQ_ACBI_MASK 0xf
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| 176 | #define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8
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| 177 | #define AMDM37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12)
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| 178 | #define AMDM37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13)
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| 179 | #define AMDM37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14)
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| 180 | #define AMDM37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15)
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| 181 | #define AMDM37X_DISPC_POL_FREQ_RF_FLAG (1 << 16)
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| 182 | #define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17)
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| 183 |
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| 184 | ioport32_t divisor;
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| 185 | #define AMDM37X_DISPC_DIVISOR_PCD_MASK 0xff
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| 186 | #define AMDM37X_DISPC_DIVISOR_PCD_SHIFT 0
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| 187 | #define AMDM37X_DISPC_DIVISOR_LCD_MASK 0xff
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| 188 | #define AMDM37X_DISPC_DIVISOR_LCD_SHIFT 16
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| 189 |
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| 190 | ioport32_t global_alpha;
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| 191 | #define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff
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| 192 | #define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0
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| 193 | #define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff
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| 194 | #define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16
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| 195 |
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| 196 | ioport32_t size_dig;
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| 197 | ioport32_t size_lcd;
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| 198 |
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| 199 | struct {
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| 200 | ioport32_t ba[2];
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| 201 | ioport32_t position;
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| 202 | #define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff
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| 203 | #define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0
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| 204 | #define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff
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| 205 | #define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16
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| 206 |
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| 207 | ioport32_t size;
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| 208 | #define AMDM37X_DISPC_SIZE_WIDTH_MASK 0x7ff
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| 209 | #define AMDM37X_DISPC_SIZE_WIDTH_SHIFT 0
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| 210 | #define AMDM37X_DISPC_SIZE_HEIGHT_MASK 0x7ff
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| 211 | #define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT 16
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| 212 |
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| 213 | PADD32[4];
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| 214 | ioport32_t attributes;
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| 215 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0)
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| 216 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf
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| 217 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 1
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| 218 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5
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| 219 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6
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| 220 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x8
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| 221 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9
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| 222 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc
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| 223 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd
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| 224 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe
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| 225 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5)
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| 226 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3
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| 227 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6
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| 228 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8)
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| 229 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9)
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| 230 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10)
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| 231 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11)
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| 232 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3
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| 233 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12
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| 234 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14)
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| 235 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15)
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| 236 | #define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28)
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| 237 |
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| 238 |
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| 239 | ioport32_t fifo_threshold;
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| 240 | const ioport32_t fifo_size_status;
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| 241 | ioport32_t row_inc;
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| 242 | ioport32_t pixel_inc;
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| 243 | ioport32_t window_skip;
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| 244 | ioport32_t table_ba;
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| 245 | } gfx;
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| 246 |
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| 247 | struct {
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| 248 | ioport32_t ba[2];
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| 249 | ioport32_t position;
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| 250 | ioport32_t size;
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| 251 | ioport32_t attributes;
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| 252 | ioport32_t fifo_threshold;
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| 253 | const ioport32_t fifo_size_status;
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| 254 | ioport32_t row_inc;
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| 255 | ioport32_t pixel_inc;
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| 256 | ioport32_t fir;
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| 257 | ioport32_t picture_size;
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| 258 | ioport32_t accui[2];
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| 259 | struct {
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| 260 | ioport32_t hi;
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| 261 | ioport32_t hvi;
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| 262 | } fir_coef[8];
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| 263 | ioport32_t conv_coef[5];
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| 264 | PADD32[2];
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| 265 | } vid[2];
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| 266 | /* 0x1d4 */
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| 267 | ioport32_t data_cycle[3];
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| 268 | /* 0x1e0 */
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| 269 | ioport32_t vid_fir_coef_v[8];
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| 270 | /* 0x200 */
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| 271 | PADD32[8];
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| 272 | /* 0x220 */
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| 273 | ioport32_t cpr_coef_r;
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| 274 | ioport32_t cpr_coef_g;
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| 275 | ioport32_t cpr_coef_b;
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| 276 | ioport32_t gfx_preload;
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| 277 |
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| 278 | /* 0x230 */
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| 279 | ioport32_t vid_preload[2];
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| 280 |
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| 281 | } amdm37x_dispc_regs_t;
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| 282 |
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| 283 |
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| 284 | #endif
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| 285 | /**
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| 286 | * @}
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| 287 | */
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