source: mainline/uspace/drv/fb/amdm37x_dispc/amdm37x_dispc.c@ 4d30bcd9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4d30bcd9 was 7c3fb9b, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix block comment formatting (ccheck).
  • Property mode set to 100644
File size: 9.9 KB
Line 
1/*
2 * Copyright (c) 2013 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amdm37x
30 * @{
31 */
32/**
33 * @file
34 */
35
36#include <align.h>
37#include <assert.h>
38#include <errno.h>
39#include <ddf/log.h>
40#include <ddi.h>
41#include <as.h>
42
43#include "amdm37x_dispc.h"
44
45#ifndef CONFIG_BFB_BPP
46#define CONFIG_BFB_BPP 24
47#endif
48
49#ifndef CONFIG_BFB_WIDTH
50#define CONFIG_BFB_WIDTH 1024
51#endif
52
53#ifndef CONFIG_BFB_HEIGHT
54#define CONFIG_BFB_HEIGHT 768
55#endif
56
57
58static errno_t change_mode(visualizer_t *vis, vslmode_t mode);
59static errno_t handle_damage(visualizer_t *vs,
60 sysarg_t x0, sysarg_t y0, sysarg_t width, sysarg_t height,
61 sysarg_t x_offset, sysarg_t y_offset);
62static errno_t dummy(visualizer_t *vs)
63{
64 return EOK;
65}
66
67static const visualizer_ops_t amdm37x_dispc_vis_ops = {
68 .change_mode = change_mode,
69 .handle_damage = handle_damage,
70 .claim = dummy,
71 .yield = dummy,
72 .suspend = dummy,
73 .wakeup = dummy,
74};
75
76static const struct {
77 unsigned bpp;
78 pixel2visual_t func;
79} pixel2visual_table[] = {
80 [VISUAL_INDIRECT_8] = { .bpp = 1, .func = pixel2bgr_323 },
81 [VISUAL_RGB_5_5_5_LE] = { .bpp = 2, .func = pixel2rgb_555_le },
82 [VISUAL_RGB_5_5_5_BE] = { .bpp = 2, .func = pixel2rgb_555_be },
83 [VISUAL_RGB_5_6_5_LE] = { .bpp = 2, .func = pixel2rgb_565_le },
84 [VISUAL_RGB_5_6_5_BE] = { .bpp = 2, .func = pixel2rgb_565_be },
85 [VISUAL_BGR_8_8_8] = { .bpp = 3, .func = pixel2bgr_888 },
86 [VISUAL_RGB_8_8_8] = { .bpp = 3, .func = pixel2rgb_888 },
87 [VISUAL_BGR_0_8_8_8] = { .bpp = 4, .func = pixel2rgb_0888 },
88 [VISUAL_BGR_8_8_8_0] = { .bpp = 4, .func = pixel2bgr_8880 },
89 [VISUAL_ABGR_8_8_8_8] = { .bpp = 4, .func = pixel2abgr_8888 },
90 [VISUAL_BGRA_8_8_8_8] = { .bpp = 4, .func = pixel2bgra_8888 },
91 [VISUAL_RGB_0_8_8_8] = { .bpp = 4, .func = pixel2rgb_0888 },
92 [VISUAL_RGB_8_8_8_0] = { .bpp = 4, .func = pixel2rgb_8880 },
93 [VISUAL_ARGB_8_8_8_8] = { .bpp = 4, .func = pixel2argb_8888 },
94 [VISUAL_RGBA_8_8_8_8] = { .bpp = 4, .func = pixel2rgba_8888 },
95};
96
97
98
99static void mode_init(vslmode_list_element_t *mode,
100 unsigned width, unsigned height, visual_t visual)
101{
102 mode->mode.index = 0;
103 mode->mode.version = 0;
104 mode->mode.refresh_rate = 0;
105 mode->mode.screen_aspect.width = width;
106 mode->mode.screen_aspect.height = height;
107 mode->mode.screen_width = width;
108 mode->mode.screen_height = height;
109 mode->mode.cell_aspect.width = 1;
110 mode->mode.cell_aspect.height = 1;
111 mode->mode.cell_visual.pixel_visual = visual;
112
113 link_initialize(&mode->link);
114
115}
116
117errno_t amdm37x_dispc_init(amdm37x_dispc_t *instance, visualizer_t *vis)
118{
119 assert(instance);
120 assert(vis);
121
122 instance->fb_data = NULL;
123 instance->size = 0;
124
125 /* Default is 24bpp, use config option if available */
126 visual_t visual = VISUAL_BGR_8_8_8;
127 switch (CONFIG_BFB_BPP) {
128 case 8:
129 visual = VISUAL_INDIRECT_8;
130 break;
131 case 16:
132 visual = VISUAL_RGB_5_6_5_LE;
133 break;
134 case 24:
135 visual = VISUAL_BGR_8_8_8;
136 break;
137 case 32:
138 visual = VISUAL_RGB_8_8_8_0;
139 break;
140 default:
141 return EINVAL;
142 }
143
144 errno_t ret = pio_enable((void *)AMDM37x_DISPC_BASE_ADDRESS,
145 AMDM37x_DISPC_SIZE, (void **)&instance->regs);
146 if (ret != EOK) {
147 return EIO;
148 }
149
150 mode_init(&instance->modes[0],
151 CONFIG_BFB_WIDTH, CONFIG_BFB_HEIGHT, visual);
152
153 /* Handle vis stuff */
154 vis->dev_ctx = instance;
155 vis->def_mode_idx = 0;
156 vis->ops = amdm37x_dispc_vis_ops;
157 list_append(&instance->modes[0].link, &vis->modes);
158
159 return EOK;
160}
161
162errno_t amdm37x_dispc_fini(amdm37x_dispc_t *instance)
163{
164 return EOK;
165}
166
167static errno_t amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
168 unsigned x, unsigned y, unsigned bpp, uint32_t pa)
169{
170 assert(regs);
171 /*
172 * Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
173 * no idea what parts of that work.
174 */
175
176 /* Disable all interrupts */
177 regs->irqenable = 0;
178
179 /* Pixel format specifics*/
180 uint32_t attrib_pixel_format = 0;
181 uint32_t control_data_lanes = 0;
182 switch (bpp) {
183 case 32:
184 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
185 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
186 break;
187 case 24:
188 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
189 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
190 break;
191 case 16:
192 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
193 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
194 break;
195 default:
196 return EINVAL;
197 }
198
199 /* Prepare sizes */
200 const uint32_t size_reg =
201 (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK) <<
202 AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
203 (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK) <<
204 AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
205
206 /* modes taken from u-boot, for 1024x768 */
207 // TODO replace magic values with actual correct values
208#if 0
209 regs->timing_h = 0x1a4024c9;
210 regs->timing_v = 0x02c00509;
211 regs->pol_freq = 0x00007028;
212 regs->divisor = 0x00010001;
213#endif
214
215 /* setup output */
216 regs->size_lcd = size_reg;
217 regs->size_dig = size_reg;
218
219 /* Nice blue default color */
220 regs->default_color[0] = 0x0000ff;
221 regs->default_color[1] = 0x0000ff;
222
223 /* Setup control register */
224 uint32_t control = 0 |
225 AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
226 (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
227 AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
228 AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
229 regs->control = control;
230
231 /* No gamma stuff only data */
232 uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME <<
233 AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
234 regs->config = config;
235
236
237 /* Set framebuffer base address */
238 regs->gfx.ba[0] = pa;
239 regs->gfx.ba[1] = pa;
240 regs->gfx.position = 0;
241
242 /* Setup fb size */
243 regs->gfx.size = size_reg;
244
245 /* Set pixel format */
246 uint32_t attribs = 0 |
247 (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
248 regs->gfx.attributes = attribs;
249
250 /* 0x03ff03c0 is the default */
251 regs->gfx.fifo_threshold = 0x03ff03c0;
252 /*
253 * This value should be stride - width, 1 means next pixel i.e.
254 * stride == width
255 */
256 regs->gfx.row_inc = 1;
257 /* number of bytes to next pixel in BPP multiples */
258 regs->gfx.pixel_inc = 1;
259 /* only used if video is played over fb */
260 regs->gfx.window_skip = 0;
261 /* Gamma and palette table */
262 regs->gfx.table_ba = 0;
263
264 /* enable frame buffer graphics */
265 regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
266 /* Update register values */
267 regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
268 regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
269 /* Enable output */
270 regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
271 regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
272 return EOK;
273}
274
275static errno_t change_mode(visualizer_t *vis, vslmode_t mode)
276{
277 assert(vis);
278 assert(vis->dev_ctx);
279
280 amdm37x_dispc_t *dispc = vis->dev_ctx;
281 const visual_t visual = mode.cell_visual.pixel_visual;
282 assert((size_t)visual < sizeof(pixel2visual_table) / sizeof(pixel2visual_table[0]));
283 const unsigned bpp = pixel2visual_table[visual].bpp;
284 pixel2visual_t p2v = pixel2visual_table[visual].func;
285 const unsigned x = mode.screen_width;
286 const unsigned y = mode.screen_height;
287 ddf_log_note("Setting mode: %ux%ux%u\n", x, y, bpp * 8);
288 const size_t size = ALIGN_UP(x * y * bpp, PAGE_SIZE);
289 uintptr_t pa;
290 void *buffer = AS_AREA_ANY;
291 errno_t ret = dmamem_map_anonymous(size, DMAMEM_4GiB,
292 AS_AREA_READ | AS_AREA_WRITE, 0, &pa, &buffer);
293 if (ret != EOK) {
294 ddf_log_error("Failed to get new FB\n");
295 return ret;
296 }
297 if (dispc->fb_data)
298 dmamem_unmap_anonymous(dispc->fb_data);
299
300 dispc->fb_data = buffer;
301 amdm37x_dispc_setup_fb(dispc->regs, x, y, bpp * 8, (uint32_t)pa);
302 dispc->active_fb.idx = mode.index;
303 dispc->active_fb.width = x;
304 dispc->active_fb.height = y;
305 dispc->active_fb.pitch = 0;
306 dispc->active_fb.bpp = bpp;
307 dispc->active_fb.pixel2visual = p2v;
308 dispc->size = size;
309 assert(mode.index < 1);
310
311 return EOK;
312}
313
314static errno_t handle_damage(visualizer_t *vs,
315 sysarg_t x0, sysarg_t y0, sysarg_t width, sysarg_t height,
316 sysarg_t x_offset, sysarg_t y_offset)
317{
318 assert(vs);
319 assert(vs->dev_ctx);
320 amdm37x_dispc_t *dispc = vs->dev_ctx;
321 pixelmap_t *map = &vs->cells;
322
323#define FB_POS(x, y) \
324 (((y) * (dispc->active_fb.width + dispc->active_fb.pitch) + (x)) \
325 * dispc->active_fb.bpp)
326 if (x_offset == 0 && y_offset == 0) {
327 /* Faster damage routine ignoring offsets. */
328 for (sysarg_t y = y0; y < height + y0; ++y) {
329 pixel_t *pixel = pixelmap_pixel_at(map, x0, y);
330 for (sysarg_t x = x0; x < width + x0; ++x) {
331 dispc->active_fb.pixel2visual(
332 dispc->fb_data + FB_POS(x, y), *pixel++);
333 }
334 }
335 } else {
336 for (sysarg_t y = y0; y < height + y0; ++y) {
337 for (sysarg_t x = x0; x < width + x0; ++x) {
338 dispc->active_fb.pixel2visual(
339 dispc->fb_data + FB_POS(x, y),
340 *pixelmap_pixel_at(map,
341 (x + x_offset) % map->width,
342 (y + y_offset) % map->height));
343 }
344 }
345 }
346
347 return EOK;
348}
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