source: mainline/uspace/drv/ehci-hcd/pci.c@ 109d55c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 109d55c was 109d55c, checked in by Vojtech Horky <vojtechhorky@…>, 15 years ago

Code beautification
  • Property mode set to 100644
File size: 11.1 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/**
29 * @addtogroup drvusbehci
30 * @{
31 */
32/**
33 * @file
34 * PCI related functions needed by the EHCI driver.
35 */
36#include <errno.h>
37#include <str_error.h>
38#include <assert.h>
39#include <as.h>
40#include <devman.h>
41#include <ddi.h>
42#include <libarch/ddi.h>
43#include <device/hw_res.h>
44
45#include <usb/debug.h>
46#include <pci_dev_iface.h>
47
48#include "pci.h"
49
50#define PAGE_SIZE_MASK 0xfffff000
51
52#define HCC_PARAMS_OFFSET 0x8
53#define HCC_PARAMS_EECP_MASK 0xff
54#define HCC_PARAMS_EECP_OFFSET 8
55
56#define CMD_OFFSET 0x0
57#define STS_OFFSET 0x4
58#define INT_OFFSET 0x8
59#define CFG_OFFSET 0x40
60
61#define USBCMD_RUN 1
62#define USBSTS_HALTED (1 << 12)
63
64#define USBLEGSUP_OFFSET 0
65#define USBLEGSUP_BIOS_CONTROL (1 << 16)
66#define USBLEGSUP_OS_CONTROL (1 << 24)
67#define USBLEGCTLSTS_OFFSET 4
68
69#define DEFAULT_WAIT 1000
70#define WAIT_STEP 10
71
72#define PCI_READ(size) \
73do { \
74 const int parent_phone = \
75 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);\
76 if (parent_phone < 0) {\
77 return parent_phone; \
78 } \
79 sysarg_t add = (sysarg_t)address; \
80 sysarg_t val; \
81 const int ret = \
82 async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), \
83 IPC_M_CONFIG_SPACE_READ_##size, add, &val); \
84 assert(value); \
85 *value = val; \
86 async_hangup(parent_phone); \
87 return ret; \
88} while(0)
89
90static int pci_read32(const ddf_dev_t *dev, int address, uint32_t *value)
91{
92 PCI_READ(32);
93}
94static int pci_read16(const ddf_dev_t *dev, int address, uint16_t *value)
95{
96 PCI_READ(16);
97}
98static int pci_read8(const ddf_dev_t *dev, int address, uint8_t *value)
99{
100 PCI_READ(8);
101}
102#define PCI_WRITE(size) \
103do { \
104 const int parent_phone = \
105 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);\
106 if (parent_phone < 0) {\
107 return parent_phone; \
108 } \
109 sysarg_t add = (sysarg_t)address; \
110 sysarg_t val = value; \
111 const int ret = \
112 async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), \
113 IPC_M_CONFIG_SPACE_WRITE_##size, add, val); \
114 async_hangup(parent_phone); \
115 return ret; \
116} while(0)
117
118static int pci_write32(const ddf_dev_t *dev, int address, uint32_t value)
119{
120 PCI_WRITE(32);
121}
122static int pci_write16(const ddf_dev_t *dev, int address, uint16_t value)
123{
124 PCI_WRITE(16);
125}
126static int pci_write8(const ddf_dev_t *dev, int address, uint8_t value)
127{
128 PCI_WRITE(8);
129}
130
131/** Get address of registers and IRQ for given device.
132 *
133 * @param[in] dev Device asking for the addresses.
134 * @param[out] mem_reg_address Base address of the memory range.
135 * @param[out] mem_reg_size Size of the memory range.
136 * @param[out] irq_no IRQ assigned to the device.
137 * @return Error code.
138 */
139int pci_get_my_registers(const ddf_dev_t *dev,
140 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
141{
142 assert(dev != NULL);
143
144 const int parent_phone =
145 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);
146 if (parent_phone < 0) {
147 return parent_phone;
148 }
149
150 int rc;
151
152 hw_resource_list_t hw_resources;
153 rc = hw_res_get_resource_list(parent_phone, &hw_resources);
154 if (rc != EOK) {
155 async_hangup(parent_phone);
156 return rc;
157 }
158
159 uintptr_t mem_address = 0;
160 size_t mem_size = 0;
161 bool mem_found = false;
162
163 int irq = 0;
164 bool irq_found = false;
165
166 size_t i;
167 for (i = 0; i < hw_resources.count; i++) {
168 hw_resource_t *res = &hw_resources.resources[i];
169 switch (res->type)
170 {
171 case INTERRUPT:
172 irq = res->res.interrupt.irq;
173 irq_found = true;
174 usb_log_debug2("Found interrupt: %d.\n", irq);
175 break;
176
177 case MEM_RANGE:
178 if (res->res.mem_range.address != 0
179 && res->res.mem_range.size != 0 ) {
180 mem_address = res->res.mem_range.address;
181 mem_size = res->res.mem_range.size;
182 usb_log_debug2("Found mem: %" PRIxn" %zu.\n",
183 mem_address, mem_size);
184 mem_found = true;
185 }
186 default:
187 break;
188 }
189 }
190
191 if (mem_found && irq_found) {
192 *mem_reg_address = mem_address;
193 *mem_reg_size = mem_size;
194 *irq_no = irq;
195 rc = EOK;
196 } else {
197 rc = ENOENT;
198 }
199
200 async_hangup(parent_phone);
201 return rc;
202}
203/*----------------------------------------------------------------------------*/
204/** Calls the PCI driver with a request to enable interrupts
205 *
206 * @param[in] device Device asking for interrupts
207 * @return Error code.
208 */
209int pci_enable_interrupts(const ddf_dev_t *device)
210{
211 const int parent_phone =
212 devman_parent_device_connect(device->handle, IPC_FLAG_BLOCKING);
213 if (parent_phone < 0) {
214 return parent_phone;
215 }
216 const bool enabled = hw_res_enable_interrupt(parent_phone);
217 async_hangup(parent_phone);
218 return enabled ? EOK : EIO;
219}
220/*----------------------------------------------------------------------------*/
221/** Implements BIOS handoff routine as decribed in EHCI spec
222 *
223 * @param[in] device Device asking for interrupts
224 * @return Error code.
225 */
226int pci_disable_legacy(
227 const ddf_dev_t *device, uintptr_t reg_base, size_t reg_size, int irq)
228{
229 assert(device);
230 (void) pci_read16;
231 (void) pci_read8;
232 (void) pci_write16;
233
234#define CHECK_RET_RETURN(ret, message...) \
235 if (ret != EOK) { \
236 usb_log_error(message); \
237 return ret; \
238 } else (void)0
239
240 /* Map EHCI registers */
241 void *regs = NULL;
242 int ret = pio_enable((void*)reg_base, reg_size, &regs);
243 CHECK_RET_RETURN(ret, "Failed to map registers %p: %s.\n",
244 (void *) reg_base, str_error(ret));
245
246 const uint32_t hcc_params =
247 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
248 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
249
250 /* Read value of EHCI Extended Capabilities Pointer
251 * position of EEC registers (points to PCI config space) */
252 const uint32_t eecp =
253 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
254 usb_log_debug("Value of EECP: %x.\n", eecp);
255
256 /* Read the first EEC. i.e. Legacy Support register */
257 uint32_t usblegsup;
258 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
259 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret));
260 usb_log_debug("USBLEGSUP: %" PRIxn ".\n", usblegsup);
261
262 /* Request control from firmware/BIOS, by writing 1 to highest byte.
263 * (OS Control semaphore)*/
264 usb_log_debug("Requesting OS control.\n");
265 ret = pci_write8(device, eecp + USBLEGSUP_OFFSET + 3, 1);
266 CHECK_RET_RETURN(ret, "Failed to request OS EHCI control: %s.\n",
267 str_error(ret));
268
269 size_t wait = 0;
270 /* Wait for BIOS to release control. */
271 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
272 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
273 async_usleep(WAIT_STEP);
274 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
275 wait += WAIT_STEP;
276 }
277
278
279 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
280 usb_log_info("BIOS released control after %zu usec.\n", wait);
281 } else {
282 /* BIOS failed to hand over control, this should not happen. */
283 usb_log_warning( "BIOS failed to release control after "
284 "%zu usecs, force it.\n", wait);
285 ret = pci_write32(device, eecp + USBLEGSUP_OFFSET,
286 USBLEGSUP_OS_CONTROL);
287 CHECK_RET_RETURN(ret, "Failed to force OS control: %s.\n",
288 str_error(ret));
289 /* Check capability type here, A value of 01h
290 * identifies the capability as Legacy Support.
291 * This extended capability requires one
292 * additional 32-bit register for control/status information,
293 * and this register is located at offset EECP+04h
294 * */
295 if ((usblegsup & 0xff) == 1) {
296 /* Read the second EEC
297 * Legacy Support and Control register */
298 uint32_t usblegctlsts;
299 ret = pci_read32(
300 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
301 CHECK_RET_RETURN(ret,
302 "Failed to get USBLEGCTLSTS: %s.\n", str_error(ret));
303 usb_log_debug("USBLEGCTLSTS: %" PRIxn ".\n",
304 usblegctlsts);
305 /* Zero SMI enables in legacy control register.
306 * It should prevent pre-OS code from interfering. */
307 ret = pci_write32(device, eecp + USBLEGCTLSTS_OFFSET,
308 0xe0000000); /* three upper bits are WC */
309 CHECK_RET_RETURN(ret,
310 "Failed(%d) zero USBLEGCTLSTS.\n", ret);
311 udelay(10);
312 ret = pci_read32(
313 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
314 CHECK_RET_RETURN(ret,
315 "Failed to get USBLEGCTLSTS 2: %s.\n",
316 str_error(ret));
317 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIxn ".\n",
318 usblegctlsts);
319 }
320 }
321
322
323 /* Read again Legacy Support register */
324 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
325 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret));
326 usb_log_debug("USBLEGSUP: %" PRIxn ".\n", usblegsup);
327
328 /*
329 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT
330 */
331
332 /* Get size of capability registers in memory space. */
333 const unsigned operation_offset = *(uint8_t*)regs;
334 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
335
336 /* Zero USBCMD register. */
337 volatile uint32_t *usbcmd =
338 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
339 volatile uint32_t *usbsts =
340 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
341 volatile uint32_t *usbconf =
342 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
343 volatile uint32_t *usbint =
344 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
345 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
346 if (*usbcmd & USBCMD_RUN) {
347 *usbsts = 0x3f; /* ack all interrupts */
348 *usbint = 0; /* disable all interrutps */
349 *usbconf = 0; /* relase control of RH ports */
350
351 *usbcmd = 0;
352 /* Wait until hc is halted */
353 while ((*usbsts & USBSTS_HALTED) == 0);
354 usb_log_info("EHCI turned off.\n");
355 } else {
356 usb_log_info("EHCI was not running.\n");
357 }
358 usb_log_debug("Registers: \n"
359 "\t USBCMD: %x(0x00080000 = at least 1ms between interrupts)\n"
360 "\t USBSTS: %x(0x00001000 = HC halted)\n"
361 "\t USBINT: %x(0x0 = no interrupts).\n"
362 "\t CONFIG: %x(0x0 = ports controlled by companion hc).\n",
363 *usbcmd, *usbsts, *usbint, *usbconf);
364
365 return ret;
366#undef CHECK_RET_RETURN
367}
368/*----------------------------------------------------------------------------*/
369/**
370 * @}
371 */
372
373/**
374 * @}
375 */
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