source: mainline/uspace/drv/ehci-hcd/pci.c@ 0edf7c7

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0edf7c7 was 8855939, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Do not reset EHCI controller (messes with already connected devices).
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/**
29 * @addtogroup drvusbehci
30 * @{
31 */
32/**
33 * @file
34 * PCI related functions needed by the EHCI driver.
35 */
36#include <errno.h>
37#include <assert.h>
38#include <as.h>
39#include <devman.h>
40#include <ddi.h>
41#include <libarch/ddi.h>
42#include <device/hw_res.h>
43
44#include <usb/debug.h>
45#include <pci_dev_iface.h>
46
47#include "pci.h"
48
49#define PAGE_SIZE_MASK 0xfffff000
50
51#define HCC_PARAMS_OFFSET 0x8
52#define HCC_PARAMS_EECP_MASK 0xff
53#define HCC_PARAMS_EECP_OFFSET 8
54
55#define CMD_OFFSET 0x0
56#define STS_OFFSET 0x4
57#define CFG_OFFSET 0x40
58
59#define USBCMD_RUN 1
60
61#define USBLEGSUP_OFFSET 0
62#define USBLEGSUP_BIOS_CONTROL (1 << 16)
63#define USBLEGSUP_OS_CONTROL (1 << 24)
64#define USBLEGCTLSTS_OFFSET 4
65
66#define DEFAULT_WAIT 10000
67#define WAIT_STEP 10
68
69/** Get address of registers and IRQ for given device.
70 *
71 * @param[in] dev Device asking for the addresses.
72 * @param[out] mem_reg_address Base address of the memory range.
73 * @param[out] mem_reg_size Size of the memory range.
74 * @param[out] irq_no IRQ assigned to the device.
75 * @return Error code.
76 */
77int pci_get_my_registers(ddf_dev_t *dev,
78 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
79{
80 assert(dev != NULL);
81
82 int parent_phone = devman_parent_device_connect(dev->handle,
83 IPC_FLAG_BLOCKING);
84 if (parent_phone < 0) {
85 return parent_phone;
86 }
87
88 int rc;
89
90 hw_resource_list_t hw_resources;
91 rc = hw_res_get_resource_list(parent_phone, &hw_resources);
92 if (rc != EOK) {
93 async_hangup(parent_phone);
94 return rc;
95 }
96
97 uintptr_t mem_address = 0;
98 size_t mem_size = 0;
99 bool mem_found = false;
100
101 int irq = 0;
102 bool irq_found = false;
103
104 size_t i;
105 for (i = 0; i < hw_resources.count; i++) {
106 hw_resource_t *res = &hw_resources.resources[i];
107 switch (res->type)
108 {
109 case INTERRUPT:
110 irq = res->res.interrupt.irq;
111 irq_found = true;
112 usb_log_debug2("Found interrupt: %d.\n", irq);
113 break;
114
115 case MEM_RANGE:
116 if (res->res.mem_range.address != 0
117 && res->res.mem_range.size != 0 ) {
118 mem_address = res->res.mem_range.address;
119 mem_size = res->res.mem_range.size;
120 usb_log_debug2("Found mem: %" PRIxn" %zu.\n",
121 mem_address, mem_size);
122 mem_found = true;
123 }
124 default:
125 break;
126 }
127 }
128
129 if (mem_found && irq_found) {
130 *mem_reg_address = mem_address;
131 *mem_reg_size = mem_size;
132 *irq_no = irq;
133 rc = EOK;
134 } else {
135 rc = ENOENT;
136 }
137
138 async_hangup(parent_phone);
139 return rc;
140}
141/*----------------------------------------------------------------------------*/
142/** Calls the PCI driver with a request to enable interrupts
143 *
144 * @param[in] device Device asking for interrupts
145 * @return Error code.
146 */
147int pci_enable_interrupts(ddf_dev_t *device)
148{
149 int parent_phone =
150 devman_parent_device_connect(device->handle, IPC_FLAG_BLOCKING);
151 if (parent_phone < 0) {
152 return parent_phone;
153 }
154 bool enabled = hw_res_enable_interrupt(parent_phone);
155 async_hangup(parent_phone);
156 return enabled ? EOK : EIO;
157}
158/*----------------------------------------------------------------------------*/
159/** Implements BIOS handoff routine as decribed in EHCI spec
160 *
161 * @param[in] device Device asking for interrupts
162 * @return Error code.
163 */
164int pci_disable_legacy(ddf_dev_t *device)
165{
166 assert(device);
167 int parent_phone = devman_parent_device_connect(device->handle,
168 IPC_FLAG_BLOCKING);
169 if (parent_phone < 0) {
170 return parent_phone;
171 }
172
173#define CHECK_RET_HANGUP_RETURN(ret, message...) \
174 if (ret != EOK) { \
175 usb_log_error(message); \
176 async_hangup(parent_phone); \
177 return ret; \
178 } else (void)0
179
180
181 /* read register space BASE BAR */
182 sysarg_t address = 0x10;
183 sysarg_t value;
184
185 int ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
186 IPC_M_CONFIG_SPACE_READ_32, address, &value);
187 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read PCI config space.\n",
188 ret);
189 usb_log_info("Register space BAR at %p:%" PRIxn ".\n",
190 (void *) address, value);
191
192 /* clear lower byte, it's not part of the BASE address */
193 uintptr_t registers = (value & 0xffffff00);
194 usb_log_info("Memory registers BASE address:%p.\n", (void *) registers);
195
196 /* if nothing setup the hc, we don't need to turn it off */
197 if (registers == 0)
198 return ENOTSUP;
199
200 /* map EHCI registers */
201 void *regs = as_get_mappable_page(4096);
202 ret = physmem_map((void*)(registers & PAGE_SIZE_MASK), regs, 1,
203 AS_AREA_READ | AS_AREA_WRITE);
204 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to map registers %p:%p.\n",
205 ret, regs, (void *) registers);
206
207 /* calculate value of BASE */
208 registers = (registers & 0xf00) | (uintptr_t)regs;
209
210 const uint32_t hcc_params =
211 *(uint32_t*)(registers + HCC_PARAMS_OFFSET);
212 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
213
214 /* Read value of EHCI Extended Capabilities Pointer
215 * (points to PCI config space) */
216 uint32_t eecp =
217 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
218 usb_log_debug("Value of EECP: %x.\n", eecp);
219
220 /* Read the second EEC. i.e. Legacy Support and Control register */
221 /* TODO: Check capability type here */
222 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
223 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
224 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGCTLSTS.\n", ret);
225 usb_log_debug("USBLEGCTLSTS: %" PRIxn ".\n", value);
226
227 /* Read the first EEC. i.e. Legacy Support register */
228 /* TODO: Check capability type here */
229 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
230 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
231 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
232 usb_log_debug2("USBLEGSUP: %" PRIxn ".\n", value);
233
234 /* Request control from firmware/BIOS, by writing 1 to highest byte.
235 * (OS Control semaphore)*/
236 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
237 IPC_M_CONFIG_SPACE_WRITE_8, eecp + USBLEGSUP_OFFSET + 3, 1);
238 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to request OS EHCI control.\n",
239 ret);
240
241 size_t wait = 0;
242 /* Wait for BIOS to release control. */
243 while ((wait < DEFAULT_WAIT) && (value & USBLEGSUP_BIOS_CONTROL)) {
244 async_usleep(WAIT_STEP);
245 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
246 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
247 wait += WAIT_STEP;
248 }
249
250
251 if ((value & USBLEGSUP_BIOS_CONTROL) == 0) {
252 usb_log_info("BIOS released control after %zu usec.\n", wait);
253 } else {
254 /* BIOS failed to hand over control, this should not happen. */
255 usb_log_warning( "BIOS failed to release control after "
256 "%zu usecs, force it.\n", wait);
257 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
258 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGSUP_OFFSET,
259 USBLEGSUP_OS_CONTROL);
260 CHECK_RET_HANGUP_RETURN(ret,
261 "Failed(%d) to force OS EHCI control.\n", ret);
262 }
263
264 /* Zero SMI enables in legacy control register.
265 * It would prevent pre-OS code from interfering. */
266 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
267 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET,
268 0xe0000000);
269 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) zero USBLEGCTLSTS.\n", ret);
270
271 /* Read again Legacy Support and Control register */
272 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
273 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
274 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGCTLSTS.\n", ret);
275 usb_log_debug2("USBLEGCTLSTS: %" PRIxn ".\n", value);
276
277 /* Read again Legacy Support register */
278 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
279 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
280 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
281 usb_log_debug2("USBLEGSUP: %" PRIxn ".\n", value);
282
283 /*
284 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT
285 */
286
287 /* Get size of capability registers in memory space. */
288 uint8_t operation_offset = *(uint8_t*)registers;
289 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
290
291 /* Zero USBCMD register. */
292 volatile uint32_t *usbcmd =
293 (uint32_t*)((uint8_t*)registers + operation_offset + CMD_OFFSET);
294 volatile uint32_t *usbsts =
295 (uint32_t*)((uint8_t*)registers + operation_offset + STS_OFFSET);
296 volatile uint32_t *usbconfigured =
297 (uint32_t*)((uint8_t*)registers + operation_offset + CFG_OFFSET);
298 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
299 if (*usbcmd & USBCMD_RUN) {
300 *usbcmd = 0;
301 while (!(*usbsts & (1 << 12))); /*wait until hc is halted */
302 *usbconfigured = 0;
303 usb_log_info("EHCI turned off.\n");
304 } else {
305 usb_log_info("EHCI was not running.\n");
306 }
307 usb_log_debug("Registers: %x(0x00080000):%x(0x00001000):%x(0x0).\n",
308 *usbcmd, *usbsts, *usbconfigured);
309
310 async_hangup(parent_phone);
311 return ret;
312#undef CHECK_RET_HANGUP_RETURN
313}
314/*----------------------------------------------------------------------------*/
315/**
316 * @}
317 */
318
319/**
320 * @}
321 */
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