source: mainline/uspace/drv/ehci-hcd/pci.c@ 89aca2da

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 89aca2da was c060090, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

EHCI fixes

Fix wait for halt condition
Use const wherever possible
  • Property mode set to 100644
File size: 10.9 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/**
29 * @addtogroup drvusbehci
30 * @{
31 */
32/**
33 * @file
34 * PCI related functions needed by the EHCI driver.
35 */
36#include <errno.h>
37#include <assert.h>
38#include <as.h>
39#include <devman.h>
40#include <ddi.h>
41#include <libarch/ddi.h>
42#include <device/hw_res.h>
43
44#include <usb/debug.h>
45#include <pci_dev_iface.h>
46
47#include "pci.h"
48
49#define PAGE_SIZE_MASK 0xfffff000
50
51#define HCC_PARAMS_OFFSET 0x8
52#define HCC_PARAMS_EECP_MASK 0xff
53#define HCC_PARAMS_EECP_OFFSET 8
54
55#define CMD_OFFSET 0x0
56#define STS_OFFSET 0x4
57#define INT_OFFSET 0x8
58#define CFG_OFFSET 0x40
59
60#define USBCMD_RUN 1
61#define USBSTS_HALTED (1 << 12)
62
63#define USBLEGSUP_OFFSET 0
64#define USBLEGSUP_BIOS_CONTROL (1 << 16)
65#define USBLEGSUP_OS_CONTROL (1 << 24)
66#define USBLEGCTLSTS_OFFSET 4
67
68#define DEFAULT_WAIT 1000
69#define WAIT_STEP 10
70
71#define PCI_READ(size) \
72do { \
73 const int parent_phone = \
74 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);\
75 if (parent_phone < 0) {\
76 return parent_phone; \
77 } \
78 sysarg_t add = (sysarg_t)address; \
79 sysarg_t val; \
80 const int ret = \
81 async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), \
82 IPC_M_CONFIG_SPACE_READ_##size, add, &val); \
83 assert(value); \
84 *value = val; \
85 async_hangup(parent_phone); \
86 return ret; \
87} while(0)
88
89static int pci_read32(const ddf_dev_t *dev, int address, uint32_t *value)
90{
91 PCI_READ(32);
92}
93static int pci_read16(const ddf_dev_t *dev, int address, uint16_t *value)
94{
95 PCI_READ(16);
96}
97static int pci_read8(const ddf_dev_t *dev, int address, uint8_t *value)
98{
99 PCI_READ(8);
100}
101#define PCI_WRITE(size) \
102do { \
103 const int parent_phone = \
104 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);\
105 if (parent_phone < 0) {\
106 return parent_phone; \
107 } \
108 sysarg_t add = (sysarg_t)address; \
109 sysarg_t val = value; \
110 const int ret = \
111 async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), \
112 IPC_M_CONFIG_SPACE_WRITE_##size, add, val); \
113 async_hangup(parent_phone); \
114 return ret; \
115} while(0)
116
117static int pci_write32(const ddf_dev_t *dev, int address, uint32_t value)
118{
119 PCI_WRITE(32);
120}
121static int pci_write16(const ddf_dev_t *dev, int address, uint16_t value)
122{
123 PCI_WRITE(16);
124}
125static int pci_write8(const ddf_dev_t *dev, int address, uint8_t value)
126{
127 PCI_WRITE(8);
128}
129
130/** Get address of registers and IRQ for given device.
131 *
132 * @param[in] dev Device asking for the addresses.
133 * @param[out] mem_reg_address Base address of the memory range.
134 * @param[out] mem_reg_size Size of the memory range.
135 * @param[out] irq_no IRQ assigned to the device.
136 * @return Error code.
137 */
138int pci_get_my_registers(const ddf_dev_t *dev,
139 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
140{
141 assert(dev != NULL);
142
143 const int parent_phone =
144 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);
145 if (parent_phone < 0) {
146 return parent_phone;
147 }
148
149 int rc;
150
151 hw_resource_list_t hw_resources;
152 rc = hw_res_get_resource_list(parent_phone, &hw_resources);
153 if (rc != EOK) {
154 async_hangup(parent_phone);
155 return rc;
156 }
157
158 uintptr_t mem_address = 0;
159 size_t mem_size = 0;
160 bool mem_found = false;
161
162 int irq = 0;
163 bool irq_found = false;
164
165 size_t i;
166 for (i = 0; i < hw_resources.count; i++) {
167 hw_resource_t *res = &hw_resources.resources[i];
168 switch (res->type)
169 {
170 case INTERRUPT:
171 irq = res->res.interrupt.irq;
172 irq_found = true;
173 usb_log_debug2("Found interrupt: %d.\n", irq);
174 break;
175
176 case MEM_RANGE:
177 if (res->res.mem_range.address != 0
178 && res->res.mem_range.size != 0 ) {
179 mem_address = res->res.mem_range.address;
180 mem_size = res->res.mem_range.size;
181 usb_log_debug2("Found mem: %" PRIxn" %zu.\n",
182 mem_address, mem_size);
183 mem_found = true;
184 }
185 default:
186 break;
187 }
188 }
189
190 if (mem_found && irq_found) {
191 *mem_reg_address = mem_address;
192 *mem_reg_size = mem_size;
193 *irq_no = irq;
194 rc = EOK;
195 } else {
196 rc = ENOENT;
197 }
198
199 async_hangup(parent_phone);
200 return rc;
201}
202/*----------------------------------------------------------------------------*/
203/** Calls the PCI driver with a request to enable interrupts
204 *
205 * @param[in] device Device asking for interrupts
206 * @return Error code.
207 */
208int pci_enable_interrupts(const ddf_dev_t *device)
209{
210 const int parent_phone =
211 devman_parent_device_connect(device->handle, IPC_FLAG_BLOCKING);
212 if (parent_phone < 0) {
213 return parent_phone;
214 }
215 const bool enabled = hw_res_enable_interrupt(parent_phone);
216 async_hangup(parent_phone);
217 return enabled ? EOK : EIO;
218}
219/*----------------------------------------------------------------------------*/
220/** Implements BIOS handoff routine as decribed in EHCI spec
221 *
222 * @param[in] device Device asking for interrupts
223 * @return Error code.
224 */
225int pci_disable_legacy(
226 const ddf_dev_t *device, uintptr_t reg_base, size_t reg_size, int irq)
227{
228 assert(device);
229 (void) pci_read16;
230 (void) pci_read8;
231 (void) pci_write16;
232
233#define CHECK_RET_RETURN(ret, message...) \
234 if (ret != EOK) { \
235 usb_log_error(message); \
236 return ret; \
237 } else (void)0
238
239 /* Map EHCI registers */
240 void *regs = NULL;
241 int ret = pio_enable((void*)reg_base, reg_size, &regs);
242 CHECK_RET_RETURN(ret, "Failed(%d) to map registers %p.\n",
243 ret, (void *) reg_base);
244
245 const uint32_t hcc_params =
246 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
247 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
248
249 /* Read value of EHCI Extended Capabilities Pointer
250 * position of EEC registers (points to PCI config space) */
251 const uint32_t eecp =
252 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
253 usb_log_debug("Value of EECP: %x.\n", eecp);
254
255 /* Read the first EEC. i.e. Legacy Support register */
256 uint32_t usblegsup;
257 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
258 CHECK_RET_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
259 usb_log_debug("USBLEGSUP: %" PRIxn ".\n", usblegsup);
260
261 /* Request control from firmware/BIOS, by writing 1 to highest byte.
262 * (OS Control semaphore)*/
263 usb_log_debug("Requesting OS control.\n");
264 ret = pci_write8(device, eecp + USBLEGSUP_OFFSET + 3, 1);
265 CHECK_RET_RETURN(ret, "Failed(%d) to request OS EHCI control.\n", ret);
266
267 size_t wait = 0;
268 /* Wait for BIOS to release control. */
269 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
270 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
271 async_usleep(WAIT_STEP);
272 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
273 wait += WAIT_STEP;
274 }
275
276
277 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
278 usb_log_info("BIOS released control after %zu usec.\n", wait);
279 } else {
280 /* BIOS failed to hand over control, this should not happen. */
281 usb_log_warning( "BIOS failed to release control after "
282 "%zu usecs, force it.\n", wait);
283 ret = pci_write32(device, eecp + USBLEGSUP_OFFSET,
284 USBLEGSUP_OS_CONTROL);
285 CHECK_RET_RETURN(ret, "Failed(%d) to force OS control.\n", ret);
286 /* Check capability type here, A value of 01h
287 * identifies the capability as Legacy Support.
288 * This extended capability requires one
289 * additional 32-bit register for control/status information,
290 * and this register is located at offset EECP+04h
291 * */
292 if ((usblegsup & 0xff) == 1) {
293 /* Read the second EEC
294 * Legacy Support and Control register */
295 uint32_t usblegctlsts;
296 ret = pci_read32(
297 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
298 CHECK_RET_RETURN(ret,
299 "Failed(%d) to get USBLEGCTLSTS.\n", ret);
300 usb_log_debug("USBLEGCTLSTS: %" PRIxn ".\n",
301 usblegctlsts);
302 /* Zero SMI enables in legacy control register.
303 * It should prevent pre-OS code from interfering. */
304 ret = pci_write32(device, eecp + USBLEGCTLSTS_OFFSET,
305 0xe0000000); /* three upper bits are WC */
306 CHECK_RET_RETURN(ret,
307 "Failed(%d) zero USBLEGCTLSTS.\n", ret);
308 udelay(10);
309 ret = pci_read32(
310 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
311 CHECK_RET_RETURN(ret,
312 "Failed(%d) to get USBLEGCTLSTS 2.\n", ret);
313 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIxn ".\n",
314 usblegctlsts);
315 }
316 }
317
318
319 /* Read again Legacy Support register */
320 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
321 CHECK_RET_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
322 usb_log_debug("USBLEGSUP: %" PRIxn ".\n", usblegsup);
323
324 /*
325 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT
326 */
327
328 /* Get size of capability registers in memory space. */
329 const unsigned operation_offset = *(uint8_t*)regs;
330 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
331
332 /* Zero USBCMD register. */
333 volatile uint32_t *usbcmd =
334 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
335 volatile uint32_t *usbsts =
336 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
337 volatile uint32_t *usbconf =
338 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
339 volatile uint32_t *usbint =
340 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
341 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
342 if (*usbcmd & USBCMD_RUN) {
343 *usbsts = 0x3f; /* ack all interrupts */
344 *usbint = 0; /* disable all interrutps */
345 *usbconf = 0; /* relase control of RH ports */
346
347 *usbcmd = 0;
348 /* Wait until hc is halted */
349 while ((*usbsts & USBSTS_HALTED) == 0);
350 usb_log_info("EHCI turned off.\n");
351 } else {
352 usb_log_info("EHCI was not running.\n");
353 }
354 usb_log_debug("Registers: \n"
355 "\t USBCMD: %x(0x00080000 = at least 1ms between interrupts)\n"
356 "\t USBSTS: %x(0x00001000 = HC halted)\n"
357 "\t USBINT: %x(0x0 = no interrupts).\n"
358 "\t CONFIG: %x(0x0 = ports controlled by companion hc).\n",
359 *usbcmd, *usbsts, *usbint, *usbconf);
360
361 return ret;
362#undef CHECK_RET_RETURN
363}
364/*----------------------------------------------------------------------------*/
365/**
366 * @}
367 */
368
369/**
370 * @}
371 */
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