source: mainline/uspace/drv/ehci-hcd/pci.c@ 57c0a7e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 57c0a7e was 40a5d40, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

Add EHCI stub and implement BIOS handover.
  • Property mode set to 100644
File size: 8.6 KB
RevLine 
[40a5d40]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/**
29 * @addtogroup drvusbuhci
30 * @{
31 */
32/**
33 * @file
34 * PCI related functions needed by the UHCI driver.
35 */
36#include <errno.h>
37#include <assert.h>
38#include <as.h>
39#include <devman.h>
40#include <ddi.h>
41#include <libarch/ddi.h>
42#include <device/hw_res.h>
43
44#include <usb/debug.h>
45#include <pci_dev_iface.h>
46
47#include "pci.h"
48
49#define PAGE_SIZE_MASK 0xfffff000
50#define HCC_PARAMS_OFFSET 0x8
51#define HCC_PARAMS_EECP_MASK 0xff
52#define HCC_PARAMS_EECP_OFFSET 8
53
54#define USBCMD_RUN 1
55
56#define USBLEGSUP_OFFSET 0
57#define USBLEGSUP_BIOS_CONTROL (1 << 16)
58#define USBLEGSUP_OS_CONTROL (1 << 24)
59#define USBLEGCTLSTS_OFFSET 4
60
61#define DEFAULT_WAIT 10000
62#define WAIT_STEP 10
63
64
65/** Get address of registers and IRQ for given device.
66 *
67 * @param[in] dev Device asking for the addresses.
68 * @param[out] io_reg_address Base address of the I/O range.
69 * @param[out] io_reg_size Size of the I/O range.
70 * @param[out] irq_no IRQ assigned to the device.
71 * @return Error code.
72 */
73int pci_get_my_registers(ddf_dev_t *dev,
74 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
75{
76 assert(dev != NULL);
77
78 int parent_phone = devman_parent_device_connect(dev->handle,
79 IPC_FLAG_BLOCKING);
80 if (parent_phone < 0) {
81 return parent_phone;
82 }
83
84 int rc;
85
86 hw_resource_list_t hw_resources;
87 rc = hw_res_get_resource_list(parent_phone, &hw_resources);
88 if (rc != EOK) {
89 goto leave;
90 }
91
92 uintptr_t mem_address = 0;
93 size_t mem_size = 0;
94 bool mem_found = false;
95
96 int irq = 0;
97 bool irq_found = false;
98
99 size_t i;
100 for (i = 0; i < hw_resources.count; i++) {
101 hw_resource_t *res = &hw_resources.resources[i];
102 switch (res->type) {
103 case INTERRUPT:
104 irq = res->res.interrupt.irq;
105 irq_found = true;
106 usb_log_debug2("Found interrupt: %d.\n", irq);
107 break;
108 case MEM_RANGE:
109 if (res->res.mem_range.address != 0
110 && res->res.mem_range.size != 0 ) {
111 mem_address = res->res.mem_range.address;
112 mem_size = res->res.mem_range.size;
113 usb_log_debug2("Found mem: %llx %zu.\n",
114 res->res.mem_range.address, res->res.mem_range.size);
115 mem_found = true;
116 }
117 break;
118 default:
119 break;
120 }
121 }
122
123 if (!mem_found) {
124 rc = ENOENT;
125 goto leave;
126 }
127
128 if (!irq_found) {
129 rc = ENOENT;
130 goto leave;
131 }
132
133 *mem_reg_address = mem_address;
134 *mem_reg_size = mem_size;
135 *irq_no = irq;
136
137 rc = EOK;
138leave:
139 async_hangup(parent_phone);
140
141 return rc;
142}
143/*----------------------------------------------------------------------------*/
144int pci_enable_interrupts(ddf_dev_t *device)
145{
146 int parent_phone = devman_parent_device_connect(device->handle,
147 IPC_FLAG_BLOCKING);
148 bool enabled = hw_res_enable_interrupt(parent_phone);
149 async_hangup(parent_phone);
150 return enabled ? EOK : EIO;
151}
152/*----------------------------------------------------------------------------*/
153int pci_disable_legacy(ddf_dev_t *device)
154{
155 assert(device);
156 int parent_phone = devman_parent_device_connect(device->handle,
157 IPC_FLAG_BLOCKING);
158 if (parent_phone < 0) {
159 return parent_phone;
160 }
161
162 /* read register space BAR */
163 sysarg_t address = 0x10;
164 sysarg_t value;
165
166 int ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
167 IPC_M_CONFIG_SPACE_READ_32, address, &value);
168 usb_log_info("Register space BAR at %p:%x.\n", address, value);
169
170 /* clear lower byte, it's not part of the address */
171 uintptr_t registers = (value & 0xffffff00);
172 usb_log_info("Mem register address:%p.\n", registers);
173
174 /* if nothing setup the hc, the we don't need to to turn it off */
175 if (registers == 0)
176 return ENOTSUP;
177
178 /* EHCI registers need 20 bytes*/
179 void *regs = as_get_mappable_page(4096);
180 ret = physmem_map((void*)(registers & PAGE_SIZE_MASK), regs, 1,
181 AS_AREA_READ | AS_AREA_WRITE);
182 if (ret != EOK) {
183 usb_log_error("Failed(%d) to map registers %p:%p.\n",
184 ret, regs, registers);
185 }
186 /* calculate value of BASE */
187 registers = (registers & 0xf00) | (uintptr_t)regs;
188
189 uint32_t hcc_params = *(uint32_t*)(registers + HCC_PARAMS_OFFSET);
190
191 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
192 uint32_t eecp = (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
193 usb_log_debug("Value of EECP: %x.\n", eecp);
194
195 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
196 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
197 if (ret != EOK) {
198 usb_log_error("Failed(%d) to read USBLEGCTLSTS.\n", ret);
199 return ret;
200 }
201 usb_log_debug2("USBLEGCTLSTS: %x.\n", value);
202
203 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
204 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
205 if (ret != EOK) {
206 usb_log_error("Failed(%d) to read USBLEGSUP.\n", ret);
207 return ret;
208 }
209 usb_log_debug2("USBLEGSUP: %x.\n", value);
210
211 /* request control from firmware/BIOS, by writing 1 to highest byte */
212 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
213 IPC_M_CONFIG_SPACE_WRITE_8, eecp + USBLEGSUP_OFFSET + 3, 1);
214 if (ret != EOK) {
215 usb_log_error("Failed(%d) request OS EHCI control.\n", ret);
216 return ret;
217 }
218
219 size_t wait = 0; /* might be anything */
220 /* wait for BIOS to release control */
221 while ((wait < DEFAULT_WAIT) && (value & USBLEGSUP_BIOS_CONTROL)) {
222 async_usleep(WAIT_STEP);
223 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
224 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
225 wait += WAIT_STEP;
226 }
227
228 if ((value & USBLEGSUP_BIOS_CONTROL) != 0) {
229 usb_log_warning(
230 "BIOS failed to release control after %d usecs, force it.\n",
231 wait);
232 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
233 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGSUP_OFFSET,
234 USBLEGSUP_OS_CONTROL);
235 if (ret != EOK) {
236 usb_log_error("Failed(%d) to force OS EHCI control.\n", ret);
237 return ret;
238 }
239 } else {
240 usb_log_info("BIOS released control after %d usec.\n",
241 wait);
242 }
243
244
245 /* zero SMI enables in legacy control register */
246 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
247 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET, 0);
248 if (ret != EOK) {
249 usb_log_error("Failed(%d) zero USBLEGCTLSTS.\n", ret);
250 return ret;
251 }
252 usb_log_debug("Zeroed USBLEGCTLSTS register.\n");
253
254 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
255 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
256 if (ret != EOK) {
257 usb_log_error("Failed(%d) to read USBLEGCTLSTS.\n", ret);
258 return ret;
259 }
260 usb_log_debug2("USBLEGCTLSTS: %x.\n", value);
261
262 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
263 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
264 if (ret != EOK) {
265 usb_log_error("Failed(%d) to read USBLEGSUP.\n", ret);
266 return ret;
267 }
268 usb_log_debug2("USBLEGSUP: %x.\n", value);
269
270/*
271 * TURN OFF EHCI FOR NOW, REMOVE IF THE DRIVER IS IMPLEMENTED
272 */
273
274 /* size of capability registers in memory space */
275 uint8_t operation_offset = *(uint8_t*)registers;
276 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
277 /* zero USBCMD register */
278 volatile uint32_t *usbcmd =
279 (uint32_t*)((uint8_t*)registers + operation_offset);
280 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
281 if (*usbcmd & USBCMD_RUN) {
282 *usbcmd = 0;
283 usb_log_info("EHCI turned off.\n");
284 } else {
285 usb_log_info("EHCI was not running.\n");
286 }
287
288
289 async_hangup(parent_phone);
290
291 return ret;
292}
293/*----------------------------------------------------------------------------*/
294/**
295 * @}
296 */
297
298/**
299 * @}
300 */
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