source: mainline/uspace/drv/ehci-hcd/pci.c@ 17d1542

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 17d1542 was 17d1542, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

EHCI reworked
  • Property mode set to 100644
File size: 11.1 KB
RevLine 
[40a5d40]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/**
[0969e45e]29 * @addtogroup drvusbehci
[40a5d40]30 * @{
31 */
32/**
33 * @file
[0969e45e]34 * PCI related functions needed by the EHCI driver.
[40a5d40]35 */
36#include <errno.h>
37#include <assert.h>
38#include <as.h>
39#include <devman.h>
40#include <ddi.h>
41#include <libarch/ddi.h>
42#include <device/hw_res.h>
43
44#include <usb/debug.h>
45#include <pci_dev_iface.h>
46
47#include "pci.h"
48
49#define PAGE_SIZE_MASK 0xfffff000
[13927cf]50
[40a5d40]51#define HCC_PARAMS_OFFSET 0x8
52#define HCC_PARAMS_EECP_MASK 0xff
53#define HCC_PARAMS_EECP_OFFSET 8
54
[0d3167e]55#define CMD_OFFSET 0x0
[a948c23]56#define STS_OFFSET 0x4
[17d1542]57#define INT_OFFSET 0x8
[a948c23]58#define CFG_OFFSET 0x40
[0d3167e]59
[40a5d40]60#define USBCMD_RUN 1
[17d1542]61#define USBSTS_HALTED (1 << 12)
[40a5d40]62
63#define USBLEGSUP_OFFSET 0
64#define USBLEGSUP_BIOS_CONTROL (1 << 16)
65#define USBLEGSUP_OS_CONTROL (1 << 24)
66#define USBLEGCTLSTS_OFFSET 4
67
[17d1542]68#define DEFAULT_WAIT 1000
[40a5d40]69#define WAIT_STEP 10
70
[17d1542]71#define PCI_READ(size) \
72do { \
73 const int parent_phone = \
74 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);\
75 if (parent_phone < 0) {\
76 return parent_phone; \
77 } \
78 sysarg_t add = (sysarg_t)address; \
79 sysarg_t val; \
80 const int ret = \
81 async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), \
82 IPC_M_CONFIG_SPACE_READ_##size, add, &val); \
83 assert(value); \
84 *value = val; \
85 async_hangup(parent_phone); \
86 return ret; \
87} while(0)
88
89static int pci_read32(ddf_dev_t *dev, int address, uint32_t *value)
90{
91 PCI_READ(32);
92}
93static int pci_read16(ddf_dev_t *dev, int address, uint16_t *value)
94{
95 PCI_READ(16);
96}
97static int pci_read8(ddf_dev_t *dev, int address, uint8_t *value)
98{
99 PCI_READ(8);
100}
101#define PCI_WRITE(size) \
102do { \
103 const int parent_phone = \
104 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);\
105 if (parent_phone < 0) {\
106 return parent_phone; \
107 } \
108 sysarg_t add = (sysarg_t)address; \
109 sysarg_t val = value; \
110 const int ret = \
111 async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE), \
112 IPC_M_CONFIG_SPACE_WRITE_##size, add, val); \
113 async_hangup(parent_phone); \
114 return ret; \
115} while(0)
116
117static int pci_write32(ddf_dev_t *dev, int address, uint32_t value)
118{
119 PCI_WRITE(32);
120}
121static int pci_write16(ddf_dev_t *dev, int address, uint16_t value)
122{
123 PCI_WRITE(16);
124}
125static int pci_write8(ddf_dev_t *dev, int address, uint8_t value)
126{
127 PCI_WRITE(8);
128}
129
[40a5d40]130/** Get address of registers and IRQ for given device.
131 *
132 * @param[in] dev Device asking for the addresses.
[13927cf]133 * @param[out] mem_reg_address Base address of the memory range.
134 * @param[out] mem_reg_size Size of the memory range.
[40a5d40]135 * @param[out] irq_no IRQ assigned to the device.
136 * @return Error code.
137 */
138int pci_get_my_registers(ddf_dev_t *dev,
139 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
140{
141 assert(dev != NULL);
142
[17d1542]143 const int parent_phone =
144 devman_parent_device_connect(dev->handle, IPC_FLAG_BLOCKING);
[40a5d40]145 if (parent_phone < 0) {
146 return parent_phone;
147 }
148
149 int rc;
150
151 hw_resource_list_t hw_resources;
152 rc = hw_res_get_resource_list(parent_phone, &hw_resources);
153 if (rc != EOK) {
[4ed80ce8]154 async_hangup(parent_phone);
155 return rc;
[40a5d40]156 }
157
158 uintptr_t mem_address = 0;
159 size_t mem_size = 0;
160 bool mem_found = false;
161
162 int irq = 0;
163 bool irq_found = false;
164
165 size_t i;
166 for (i = 0; i < hw_resources.count; i++) {
167 hw_resource_t *res = &hw_resources.resources[i];
[4ed80ce8]168 switch (res->type)
169 {
170 case INTERRUPT:
171 irq = res->res.interrupt.irq;
172 irq_found = true;
173 usb_log_debug2("Found interrupt: %d.\n", irq);
174 break;
175
176 case MEM_RANGE:
177 if (res->res.mem_range.address != 0
178 && res->res.mem_range.size != 0 ) {
179 mem_address = res->res.mem_range.address;
180 mem_size = res->res.mem_range.size;
[4125b7d]181 usb_log_debug2("Found mem: %" PRIxn" %zu.\n",
[4ed80ce8]182 mem_address, mem_size);
183 mem_found = true;
[40a5d40]184 }
[4ed80ce8]185 default:
186 break;
[40a5d40]187 }
188 }
189
[4ed80ce8]190 if (mem_found && irq_found) {
191 *mem_reg_address = mem_address;
192 *mem_reg_size = mem_size;
193 *irq_no = irq;
194 rc = EOK;
195 } else {
[40a5d40]196 rc = ENOENT;
197 }
198
199 async_hangup(parent_phone);
200 return rc;
201}
202/*----------------------------------------------------------------------------*/
[13927cf]203/** Calls the PCI driver with a request to enable interrupts
204 *
205 * @param[in] device Device asking for interrupts
206 * @return Error code.
207 */
[40a5d40]208int pci_enable_interrupts(ddf_dev_t *device)
209{
[17d1542]210 const int parent_phone =
[4ed80ce8]211 devman_parent_device_connect(device->handle, IPC_FLAG_BLOCKING);
212 if (parent_phone < 0) {
213 return parent_phone;
214 }
[17d1542]215 const bool enabled = hw_res_enable_interrupt(parent_phone);
[40a5d40]216 async_hangup(parent_phone);
217 return enabled ? EOK : EIO;
218}
219/*----------------------------------------------------------------------------*/
[13927cf]220/** Implements BIOS handoff routine as decribed in EHCI spec
221 *
222 * @param[in] device Device asking for interrupts
223 * @return Error code.
224 */
[40a5d40]225int pci_disable_legacy(ddf_dev_t *device)
226{
227 assert(device);
[17d1542]228 (void) pci_read16;
229 (void) pci_read8;
230 (void) pci_write16;
[40a5d40]231
[17d1542]232#define CHECK_RET_RETURN(ret, message...) \
[4ed80ce8]233 if (ret != EOK) { \
234 usb_log_error(message); \
235 return ret; \
236 } else (void)0
237
[17d1542]238 uintptr_t reg_base = 0;
239 size_t reg_size = 0;
240 int irq = 0;
[4ed80ce8]241
[17d1542]242 int ret = pci_get_my_registers(device, &reg_base, &reg_size, &irq);
243 CHECK_RET_RETURN(ret, "Failed(%d) to get EHCI registers.\n", ret);
[40a5d40]244
[17d1542]245 usb_log_info("EHCI: Memory registers:%p size: %zu irq:%d.\n",
246 (void *) reg_base, reg_size, irq);
[40a5d40]247
248
[4ed80ce8]249 /* map EHCI registers */
[17d1542]250 void *regs = NULL;
251 ret = pio_enable((void*)reg_base, reg_size, &regs);
252 CHECK_RET_RETURN(ret, "Failed(%d) to map registers %p.\n",
253 ret, (void *) reg_base);
[40a5d40]254
[4ed80ce8]255 const uint32_t hcc_params =
[17d1542]256 *(uint32_t*)(regs + HCC_PARAMS_OFFSET);
[40a5d40]257 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
[13927cf]258
259 /* Read value of EHCI Extended Capabilities Pointer
[17d1542]260 * position of EEC registers (points to PCI config space) */
261 const uint32_t eecp =
[4ed80ce8]262 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
[40a5d40]263 usb_log_debug("Value of EECP: %x.\n", eecp);
264
[13927cf]265 /* Read the first EEC. i.e. Legacy Support register */
[17d1542]266 uint32_t usblegsup;
267 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
268 CHECK_RET_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
269 usb_log_debug("USBLEGSUP: %" PRIxn ".\n", usblegsup);
[40a5d40]270
[13927cf]271 /* Request control from firmware/BIOS, by writing 1 to highest byte.
272 * (OS Control semaphore)*/
[17d1542]273 usb_log_debug("Requesting OS control.\n");
274 ret = pci_write8(device, eecp + USBLEGSUP_OFFSET + 3, 1);
275 CHECK_RET_RETURN(ret, "Failed(%d) to request OS EHCI control.\n", ret);
[40a5d40]276
[4ed80ce8]277 size_t wait = 0;
[13927cf]278 /* Wait for BIOS to release control. */
[17d1542]279 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
280 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) {
[40a5d40]281 async_usleep(WAIT_STEP);
[17d1542]282 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
[40a5d40]283 wait += WAIT_STEP;
284 }
285
[13927cf]286
[17d1542]287 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) {
[4125b7d]288 usb_log_info("BIOS released control after %zu usec.\n", wait);
[4ed80ce8]289 } else {
[13927cf]290 /* BIOS failed to hand over control, this should not happen. */
[67352d2]291 usb_log_warning( "BIOS failed to release control after "
[4125b7d]292 "%zu usecs, force it.\n", wait);
[17d1542]293 ret = pci_write32(device, eecp + USBLEGSUP_OFFSET,
[40a5d40]294 USBLEGSUP_OS_CONTROL);
[17d1542]295 CHECK_RET_RETURN(ret, "Failed(%d) to force OS control.\n", ret);
296 /* Check capability type here, A value of 01h
297 * identifies the capability as Legacy Support.
298 * This extended capability requires one
299 * additional 32-bit register for control/status information,
300 * and this register is located at offset EECP+04h
301 * */
302 if ((usblegsup & 0xff) == 1) {
303 /* Read the second EEC
304 * Legacy Support and Control register */
305 uint32_t usblegctlsts;
306 ret = pci_read32(
307 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
308 CHECK_RET_RETURN(ret,
309 "Failed(%d) to get USBLEGCTLSTS.\n", ret);
310 usb_log_debug("USBLEGCTLSTS: %" PRIxn ".\n",
311 usblegctlsts);
312 /* Zero SMI enables in legacy control register.
313 * It should prevent pre-OS code from interfering. */
314 ret = pci_write32(device, eecp + USBLEGCTLSTS_OFFSET,
315 0xe0000000); /* three upper bits are WC */
316 CHECK_RET_RETURN(ret,
317 "Failed(%d) zero USBLEGCTLSTS.\n", ret);
318 ret = pci_read32(
319 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts);
320 CHECK_RET_RETURN(ret,
321 "Failed(%d) to get USBLEGCTLSTS 2.\n", ret);
322 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIxn ".\n",
323 usblegctlsts);
324 }
[40a5d40]325 }
326
327
[13927cf]328 /* Read again Legacy Support register */
[17d1542]329 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup);
330 CHECK_RET_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
331 usb_log_debug("USBLEGSUP: %" PRIxn ".\n", usblegsup);
[40a5d40]332
[67352d2]333 /*
334 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT
335 */
[40a5d40]336
[13927cf]337 /* Get size of capability registers in memory space. */
[17d1542]338 const unsigned operation_offset = *(uint8_t*)regs;
[40a5d40]339 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
[13927cf]340
341 /* Zero USBCMD register. */
[40a5d40]342 volatile uint32_t *usbcmd =
[17d1542]343 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET);
[a948c23]344 volatile uint32_t *usbsts =
[17d1542]345 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET);
346 volatile uint32_t *usbconf =
347 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET);
348 volatile uint32_t *usbint =
349 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET);
[40a5d40]350 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
351 if (*usbcmd & USBCMD_RUN) {
352 *usbcmd = 0;
[17d1542]353 /* Wait until hc is halted */
354 while ((*usbsts & USBSTS_HALTED) != 0);
355 *usbsts = 0x3f; /* ack all interrupts */
356 *usbint = 0; /* disable all interrutps */
357 *usbconf = 0; /* relase control of RH ports */
[40a5d40]358 usb_log_info("EHCI turned off.\n");
359 } else {
360 usb_log_info("EHCI was not running.\n");
361 }
[17d1542]362 usb_log_debug("Registers: \n"
363 "\t USBCMD: %x(0x00080000 = at least 1ms between interrupts)\n"
364 "\t USBSTS: %x(0x00001000 = HC halted)\n"
365 "\t USBINT: %x(0x0 = no interrupts).\n"
366 "\t CONFIG: %x(0x0 = ports controlled by companion hc).\n",
367 *usbcmd, *usbsts, *usbint, *usbconf);
[40a5d40]368
[4ed80ce8]369 return ret;
[17d1542]370#undef CHECK_RET_RETURN
[40a5d40]371}
372/*----------------------------------------------------------------------------*/
373/**
374 * @}
375 */
376
377/**
378 * @}
379 */
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