source: mainline/uspace/drv/bus/usb/xhci/transfers.h@ f92f6b1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f92f6b1 was 708d8fcd, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: rewritten isochronous transfers

There was a fundamental problem with relying on hardware to send
RING_OVERRUN/UNDERRUN events, which QEMU (and possibly others) do not
send. That resulted in not knowing if the transfer is still on schedule,
and having to ring the doorbell every time. That is not feasible,
because then the transfer can be more frequent than it should be.
Furthermore, it ignored the fact that isochronous TRBs are to be
scheduled not too late, but also not too soon (see 4.11.2.5 of the xHCI
spec).

Now, scheduling the TRBs to hardware is called feeding, and can be
delayed by setting a timer. Ring overruns/underruns are detected also at
the end of handling an event.

  • Property mode set to 100644
File size: 2.3 KB
RevLine 
[e9e24f2]1/*
2 * Copyright (c) 2017 Michal Staruch
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller transfer ring management
34 */
35
[5fd9c30]36#ifndef XHCI_TRANSFERS_H
37#define XHCI_TRANSFERS_H
38
39#include <usb/host/usb_transfer_batch.h>
40
[2cf28b9]41#include "hw_struct/context.h"
[e9e24f2]42#include "trb_ring.h"
43
[2cf28b9]44typedef struct xhci_hc xhci_hc_t;
45
[e9e24f2]46typedef struct {
[5fd9c30]47 usb_transfer_batch_t batch;
[e9e24f2]48 link_t link;
49
50 uint8_t direction;
51
[b80c1ab]52 dma_buffer_t hc_buffer;
[5fd9c30]53
54 uintptr_t interrupt_trb_phys;
[e9e24f2]55} xhci_transfer_t;
56
[eb928c4]57usb_transfer_batch_t* xhci_transfer_create(endpoint_t *);
[a4e26882]58int xhci_transfer_schedule(xhci_hc_t *, usb_transfer_batch_t *);
59int xhci_handle_transfer_event(xhci_hc_t *, xhci_trb_t *);
[eb928c4]60void xhci_transfer_destroy(usb_transfer_batch_t *);
[1252e81]61
[5fd9c30]62static inline xhci_transfer_t *xhci_transfer_from_batch(usb_transfer_batch_t *batch)
63{
64 assert(batch);
65 return (xhci_transfer_t *) batch;
66}
67
68/**
69 * @}
70 */
71#endif
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