source: mainline/uspace/drv/bus/usb/xhci/test/reg-ops.c@ f92f6b1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f92f6b1 was 8fcd8cf, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: missing tests
  • Property mode set to 100644
File size: 4.6 KB
Line 
1#include <pcut/pcut.h>
2#include "../hw_struct/regs.h"
3
4PCUT_INIT
5
6static struct {
7 uint32_t field32;
8 uint16_t field16;
9 uint8_t field8;
10} regs[1];
11
12#define REG_8_FLAG field8, 8, FLAG, 3
13#define REG_8_RANGE field8, 8, RANGE, 6, 2
14#define REG_8_FIELD field8, 8, FIELD
15#define REG_16_FLAG field16, 16, FLAG, 8
16#define REG_16_RANGE field16, 16, RANGE, 11, 4
17#define REG_16_FIELD field16, 16, FIELD
18#define REG_32_FLAG field32, 32, FLAG, 16
19#define REG_32_RANGE field32, 32, RANGE, 23, 8
20#define REG_32_FIELD field32, 32, FIELD
21
22#define RESET memset(regs, 0, sizeof(regs[0]))
23#define EQ(exp, act) PCUT_ASSERT_INT_EQUALS((exp), (act))
24
25PCUT_TEST(ops_8_field) {
26 RESET;
27 EQ(0, XHCI_REG_RD(regs, REG_8_FIELD));
28
29 XHCI_REG_WR(regs, REG_8_FIELD, 0x55);
30 EQ(0x55, XHCI_REG_RD(regs, REG_8_FIELD));
31 EQ(0x55, regs->field8);
32
33 RESET;
34 XHCI_REG_SET(regs, REG_8_FIELD, 0x55);
35 EQ(0x55, XHCI_REG_RD(regs, REG_8_FIELD));
36 EQ(0x55, regs->field8);
37
38 XHCI_REG_CLR(regs, REG_8_FIELD, 0x5);
39 EQ(0x50, XHCI_REG_RD(regs, REG_8_FIELD));
40 EQ(0x50, regs->field8);
41}
42
43PCUT_TEST(ops_8_range) {
44 RESET;
45 EQ(0, XHCI_REG_RD(regs, REG_8_RANGE));
46
47 XHCI_REG_WR(regs, REG_8_RANGE, 0x55);
48 EQ(0x15, XHCI_REG_RD(regs, REG_8_RANGE));
49 EQ(0x54, regs->field8);
50
51 XHCI_REG_SET(regs, REG_8_RANGE, 0x2);
52 EQ(0x17, XHCI_REG_RD(regs, REG_8_RANGE));
53 EQ(0x5c, regs->field8);
54
55 XHCI_REG_CLR(regs, REG_8_RANGE, 0x2);
56 EQ(0x15, XHCI_REG_RD(regs, REG_8_RANGE));
57 EQ(0x54, regs->field8);
58}
59
60PCUT_TEST(ops_8_flag) {
61 RESET;
62 EQ(0, XHCI_REG_RD(regs, REG_8_FLAG));
63
64 XHCI_REG_WR(regs, REG_8_FLAG, 1);
65 EQ(1, XHCI_REG_RD(regs, REG_8_FLAG));
66 EQ(8, regs->field8);
67
68 RESET;
69 XHCI_REG_SET(regs, REG_8_FLAG, 1);
70 EQ(1, XHCI_REG_RD(regs, REG_8_FLAG));
71 EQ(8, regs->field8);
72
73 XHCI_REG_CLR(regs, REG_8_FLAG, 1);
74 EQ(0, XHCI_REG_RD(regs, REG_8_FLAG));
75 EQ(0, regs->field8);
76}
77
78PCUT_TEST(ops_16_field) {
79 RESET;
80 EQ(0, XHCI_REG_RD(regs, REG_16_FIELD));
81
82 XHCI_REG_WR(regs, REG_16_FIELD, 0x5555);
83 EQ(0x5555, XHCI_REG_RD(regs, REG_16_FIELD));
84 EQ(0x5555, xhci2host(16, regs->field16));
85
86 XHCI_REG_SET(regs, REG_16_FIELD, 0x00aa);
87 EQ(0x55ff, XHCI_REG_RD(regs, REG_16_FIELD));
88 EQ(0x55ff, xhci2host(16, regs->field16));
89
90 XHCI_REG_CLR(regs, REG_16_FIELD, 0x055a);
91 EQ(0x50a5, XHCI_REG_RD(regs, REG_16_FIELD));
92 EQ(0x50a5, xhci2host(16, regs->field16));
93}
94
95PCUT_TEST(ops_16_range) {
96 RESET;
97 EQ(0, XHCI_REG_RD(regs, REG_16_RANGE));
98
99 XHCI_REG_WR(regs, REG_16_RANGE, 0x5a5a);
100 EQ(0x5a, XHCI_REG_RD(regs, REG_16_RANGE));
101 EQ(0x05a0, xhci2host(16, regs->field16));
102
103 XHCI_REG_SET(regs, REG_16_RANGE, 0xa5);
104 EQ(0xff, XHCI_REG_RD(regs, REG_16_RANGE));
105 EQ(0x0ff0, xhci2host(16, regs->field16));
106
107 XHCI_REG_CLR(regs, REG_16_RANGE, 0x5a);
108 EQ(0xa5, XHCI_REG_RD(regs, REG_16_RANGE));
109 EQ(0x0a50, xhci2host(16, regs->field16));
110}
111
112PCUT_TEST(ops_16_flag) {
113 RESET;
114 EQ(0, XHCI_REG_RD(regs, REG_16_FLAG));
115
116 XHCI_REG_WR(regs, REG_16_FLAG, 1);
117 EQ(1, XHCI_REG_RD(regs, REG_16_FLAG));
118 EQ(0x100, xhci2host(16, regs->field16));
119
120 RESET;
121 XHCI_REG_SET(regs, REG_16_FLAG, 1);
122 EQ(1, XHCI_REG_RD(regs, REG_16_FLAG));
123 EQ(0x100, xhci2host(16, regs->field16));
124
125 XHCI_REG_CLR(regs, REG_16_FLAG, 1);
126 EQ(0, XHCI_REG_RD(regs, REG_16_FLAG));
127 EQ(0, xhci2host(16, regs->field16));
128}
129
130PCUT_TEST(ops_32_field) {
131 RESET;
132 EQ(0, XHCI_REG_RD(regs, REG_32_FIELD));
133
134 XHCI_REG_WR(regs, REG_32_FIELD, 0xffaa5500);
135 EQ(0xffaa5500, XHCI_REG_RD(regs, REG_32_FIELD));
136 EQ(0xffaa5500, xhci2host(32, regs->field32));
137
138 XHCI_REG_SET(regs, REG_32_FIELD, 0x0055aa00);
139 EQ(0xffffff00, XHCI_REG_RD(regs, REG_32_FIELD));
140 EQ(0xffffff00, xhci2host(32, regs->field32));
141
142 XHCI_REG_CLR(regs, REG_32_FIELD, 0x00aa55ff);
143 EQ(0xff55aa00, XHCI_REG_RD(regs, REG_32_FIELD));
144 EQ(0xff55aa00, xhci2host(32, regs->field32));
145}
146
147PCUT_TEST(ops_32_range) {
148 RESET;
149 EQ(0, XHCI_REG_RD(regs, REG_32_RANGE));
150
151 XHCI_REG_WR(regs, REG_32_RANGE, 0xff5a0);
152 EQ(0xf5a0, XHCI_REG_RD(regs, REG_32_RANGE));
153 EQ(0x00f5a000, xhci2host(32, regs->field32));
154
155 XHCI_REG_SET(regs, REG_32_RANGE, 0xffa50);
156 EQ(0xfff0, XHCI_REG_RD(regs, REG_32_RANGE));
157 EQ(0x00fff000, xhci2host(32, regs->field32));
158
159 XHCI_REG_CLR(regs, REG_32_RANGE, 0xf05af);
160 EQ(0xfa50, XHCI_REG_RD(regs, REG_32_RANGE));
161 EQ(0x00fa5000, xhci2host(32, regs->field32));
162}
163
164PCUT_TEST(ops_32_flag) {
165 RESET;
166 EQ(0, XHCI_REG_RD(regs, REG_32_FLAG));
167
168 XHCI_REG_WR(regs, REG_32_FLAG, 1);
169 EQ(1, XHCI_REG_RD(regs, REG_32_FLAG));
170 EQ(0x10000, xhci2host(32, regs->field32));
171
172 RESET;
173 XHCI_REG_SET(regs, REG_32_FLAG, 1);
174 EQ(1, XHCI_REG_RD(regs, REG_32_FLAG));
175 EQ(0x10000, xhci2host(32, regs->field32));
176
177 XHCI_REG_CLR(regs, REG_32_FLAG, 1);
178 EQ(0, XHCI_REG_RD(regs, REG_32_FLAG));
179 EQ(0, xhci2host(32, regs->field32));
180}
181PCUT_MAIN();
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