source: mainline/uspace/drv/bus/usb/xhci/test/reg-ops.c@ b277bef

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b277bef was 3bacee1, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Make ccheck-fix again and commit more good files.
  • Property mode set to 100644
File size: 4.6 KB
Line 
1#include <pcut/pcut.h>
2#include "../hw_struct/regs.h"
3
4PCUT_INIT;
5
6static struct {
7 uint32_t field32;
8 uint16_t field16;
9 uint8_t field8;
10} regs[1];
11
12#define REG_8_FLAG field8, 8, FLAG, 3
13#define REG_8_RANGE field8, 8, RANGE, 6, 2
14#define REG_8_FIELD field8, 8, FIELD
15#define REG_16_FLAG field16, 16, FLAG, 8
16#define REG_16_RANGE field16, 16, RANGE, 11, 4
17#define REG_16_FIELD field16, 16, FIELD
18#define REG_32_FLAG field32, 32, FLAG, 16
19#define REG_32_RANGE field32, 32, RANGE, 23, 8
20#define REG_32_FIELD field32, 32, FIELD
21
22#define RESET memset(regs, 0, sizeof(regs[0]))
23#define EQ(exp, act) PCUT_ASSERT_INT_EQUALS((exp), (act))
24
25PCUT_TEST(ops_8_field)
26{
27 RESET;
28 EQ(0, XHCI_REG_RD(regs, REG_8_FIELD));
29
30 XHCI_REG_WR(regs, REG_8_FIELD, 0x55);
31 EQ(0x55, XHCI_REG_RD(regs, REG_8_FIELD));
32 EQ(0x55, regs->field8);
33
34 RESET;
35 XHCI_REG_SET(regs, REG_8_FIELD, 0x55);
36 EQ(0x55, XHCI_REG_RD(regs, REG_8_FIELD));
37 EQ(0x55, regs->field8);
38
39 XHCI_REG_CLR(regs, REG_8_FIELD, 0x5);
40 EQ(0x50, XHCI_REG_RD(regs, REG_8_FIELD));
41 EQ(0x50, regs->field8);
42}
43
44PCUT_TEST(ops_8_range)
45{
46 RESET;
47 EQ(0, XHCI_REG_RD(regs, REG_8_RANGE));
48
49 XHCI_REG_WR(regs, REG_8_RANGE, 0x55);
50 EQ(0x15, XHCI_REG_RD(regs, REG_8_RANGE));
51 EQ(0x54, regs->field8);
52
53 XHCI_REG_SET(regs, REG_8_RANGE, 0x2);
54 EQ(0x17, XHCI_REG_RD(regs, REG_8_RANGE));
55 EQ(0x5c, regs->field8);
56
57 XHCI_REG_CLR(regs, REG_8_RANGE, 0x2);
58 EQ(0x15, XHCI_REG_RD(regs, REG_8_RANGE));
59 EQ(0x54, regs->field8);
60}
61
62PCUT_TEST(ops_8_flag)
63{
64 RESET;
65 EQ(0, XHCI_REG_RD(regs, REG_8_FLAG));
66
67 XHCI_REG_WR(regs, REG_8_FLAG, 1);
68 EQ(1, XHCI_REG_RD(regs, REG_8_FLAG));
69 EQ(8, regs->field8);
70
71 RESET;
72 XHCI_REG_SET(regs, REG_8_FLAG, 1);
73 EQ(1, XHCI_REG_RD(regs, REG_8_FLAG));
74 EQ(8, regs->field8);
75
76 XHCI_REG_CLR(regs, REG_8_FLAG, 1);
77 EQ(0, XHCI_REG_RD(regs, REG_8_FLAG));
78 EQ(0, regs->field8);
79}
80
81PCUT_TEST(ops_16_field)
82{
83 RESET;
84 EQ(0, XHCI_REG_RD(regs, REG_16_FIELD));
85
86 XHCI_REG_WR(regs, REG_16_FIELD, 0x5555);
87 EQ(0x5555, XHCI_REG_RD(regs, REG_16_FIELD));
88 EQ(0x5555, xhci2host(16, regs->field16));
89
90 XHCI_REG_SET(regs, REG_16_FIELD, 0x00aa);
91 EQ(0x55ff, XHCI_REG_RD(regs, REG_16_FIELD));
92 EQ(0x55ff, xhci2host(16, regs->field16));
93
94 XHCI_REG_CLR(regs, REG_16_FIELD, 0x055a);
95 EQ(0x50a5, XHCI_REG_RD(regs, REG_16_FIELD));
96 EQ(0x50a5, xhci2host(16, regs->field16));
97}
98
99PCUT_TEST(ops_16_range)
100{
101 RESET;
102 EQ(0, XHCI_REG_RD(regs, REG_16_RANGE));
103
104 XHCI_REG_WR(regs, REG_16_RANGE, 0x5a5a);
105 EQ(0x5a, XHCI_REG_RD(regs, REG_16_RANGE));
106 EQ(0x05a0, xhci2host(16, regs->field16));
107
108 XHCI_REG_SET(regs, REG_16_RANGE, 0xa5);
109 EQ(0xff, XHCI_REG_RD(regs, REG_16_RANGE));
110 EQ(0x0ff0, xhci2host(16, regs->field16));
111
112 XHCI_REG_CLR(regs, REG_16_RANGE, 0x5a);
113 EQ(0xa5, XHCI_REG_RD(regs, REG_16_RANGE));
114 EQ(0x0a50, xhci2host(16, regs->field16));
115}
116
117PCUT_TEST(ops_16_flag)
118{
119 RESET;
120 EQ(0, XHCI_REG_RD(regs, REG_16_FLAG));
121
122 XHCI_REG_WR(regs, REG_16_FLAG, 1);
123 EQ(1, XHCI_REG_RD(regs, REG_16_FLAG));
124 EQ(0x100, xhci2host(16, regs->field16));
125
126 RESET;
127 XHCI_REG_SET(regs, REG_16_FLAG, 1);
128 EQ(1, XHCI_REG_RD(regs, REG_16_FLAG));
129 EQ(0x100, xhci2host(16, regs->field16));
130
131 XHCI_REG_CLR(regs, REG_16_FLAG, 1);
132 EQ(0, XHCI_REG_RD(regs, REG_16_FLAG));
133 EQ(0, xhci2host(16, regs->field16));
134}
135
136PCUT_TEST(ops_32_field)
137{
138 RESET;
139 EQ(0, XHCI_REG_RD(regs, REG_32_FIELD));
140
141 XHCI_REG_WR(regs, REG_32_FIELD, 0xffaa5500);
142 EQ(0xffaa5500, XHCI_REG_RD(regs, REG_32_FIELD));
143 EQ(0xffaa5500, xhci2host(32, regs->field32));
144
145 XHCI_REG_SET(regs, REG_32_FIELD, 0x0055aa00);
146 EQ(0xffffff00, XHCI_REG_RD(regs, REG_32_FIELD));
147 EQ(0xffffff00, xhci2host(32, regs->field32));
148
149 XHCI_REG_CLR(regs, REG_32_FIELD, 0x00aa55ff);
150 EQ(0xff55aa00, XHCI_REG_RD(regs, REG_32_FIELD));
151 EQ(0xff55aa00, xhci2host(32, regs->field32));
152}
153
154PCUT_TEST(ops_32_range)
155{
156 RESET;
157 EQ(0, XHCI_REG_RD(regs, REG_32_RANGE));
158
159 XHCI_REG_WR(regs, REG_32_RANGE, 0xff5a0);
160 EQ(0xf5a0, XHCI_REG_RD(regs, REG_32_RANGE));
161 EQ(0x00f5a000, xhci2host(32, regs->field32));
162
163 XHCI_REG_SET(regs, REG_32_RANGE, 0xffa50);
164 EQ(0xfff0, XHCI_REG_RD(regs, REG_32_RANGE));
165 EQ(0x00fff000, xhci2host(32, regs->field32));
166
167 XHCI_REG_CLR(regs, REG_32_RANGE, 0xf05af);
168 EQ(0xfa50, XHCI_REG_RD(regs, REG_32_RANGE));
169 EQ(0x00fa5000, xhci2host(32, regs->field32));
170}
171
172PCUT_TEST(ops_32_flag)
173{
174 RESET;
175 EQ(0, XHCI_REG_RD(regs, REG_32_FLAG));
176
177 XHCI_REG_WR(regs, REG_32_FLAG, 1);
178 EQ(1, XHCI_REG_RD(regs, REG_32_FLAG));
179 EQ(0x10000, xhci2host(32, regs->field32));
180
181 RESET;
182 XHCI_REG_SET(regs, REG_32_FLAG, 1);
183 EQ(1, XHCI_REG_RD(regs, REG_32_FLAG));
184 EQ(0x10000, xhci2host(32, regs->field32));
185
186 XHCI_REG_CLR(regs, REG_32_FLAG, 1);
187 EQ(0, XHCI_REG_RD(regs, REG_32_FLAG));
188 EQ(0, xhci2host(32, regs->field32));
189}
190PCUT_MAIN();
Note: See TracBrowser for help on using the repository browser.