source: mainline/uspace/drv/bus/usb/xhci/hw_struct/trb.h@ 5fe3f954

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5fe3f954 was 8033f89, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: cstyle
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1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * TRB-related structures of the xHC.
34 *
35 * This file contains all the types of TRB and the TRB ring handling.
36 */
37
38#ifndef XHCI_TRB_H
39#define XHCI_TRB_H
40
41#include "common.h"
42#include <libarch/barrier.h>
43
44/**
45 * TRB types: section 6.4.6, table 139
46 */
47enum xhci_trb_type {
48 XHCI_TRB_TYPE_RESERVED = 0,
49
50// Transfer ring:
51 XHCI_TRB_TYPE_NORMAL,
52 XHCI_TRB_TYPE_SETUP_STAGE,
53 XHCI_TRB_TYPE_DATA_STAGE,
54 XHCI_TRB_TYPE_STATUS_STAGE,
55 XHCI_TRB_TYPE_ISOCH,
56 XHCI_TRB_TYPE_LINK,
57 XHCI_TRB_TYPE_EVENT_DATA,
58 XHCI_TRB_TYPE_NO_OP,
59
60// Command ring:
61 XHCI_TRB_TYPE_ENABLE_SLOT_CMD,
62 XHCI_TRB_TYPE_DISABLE_SLOT_CMD,
63 XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD,
64 XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD,
65 XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD,
66 XHCI_TRB_TYPE_RESET_ENDPOINT_CMD,
67 XHCI_TRB_TYPE_STOP_ENDPOINT_CMD,
68 XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD,
69 XHCI_TRB_TYPE_RESET_DEVICE_CMD,
70 XHCI_TRB_TYPE_FORCE_EVENT_CMD,
71 XHCI_TRB_TYPE_NEGOTIATE_BANDWIDTH_CMD,
72 XHCI_TRB_TYPE_SET_LATENCY_TOLERANCE_VALUE_CMD,
73 XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD,
74 XHCI_TRB_TYPE_FORCE_HEADER_CMD,
75 XHCI_TRB_TYPE_NO_OP_CMD,
76// Reserved: 24-31
77
78// Event ring:
79 XHCI_TRB_TYPE_TRANSFER_EVENT = 32,
80 XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT,
81 XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT,
82 XHCI_TRB_TYPE_BANDWIDTH_REQUEST_EVENT,
83 XHCI_TRB_TYPE_DOORBELL_EVENT,
84 XHCI_TRB_TYPE_HOST_CONTROLLER_EVENT,
85 XHCI_TRB_TYPE_DEVICE_NOTIFICATION_EVENT,
86 XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT,
87
88 XHCI_TRB_TYPE_MAX
89};
90
91/**
92 * TRB template: section 4.11.1
93 */
94typedef struct xhci_trb {
95 xhci_qword_t parameter;
96 xhci_dword_t status;
97 xhci_dword_t control;
98} __attribute__((packed)) __attribute__((aligned(16))) xhci_trb_t;
99
100#define TRB_TYPE(trb) XHCI_DWORD_EXTRACT((trb).control, 15, 10)
101#define TRB_CYCLE(trb) XHCI_DWORD_EXTRACT((trb).control, 0, 0)
102#define TRB_LINK_TC(trb) XHCI_DWORD_EXTRACT((trb).control, 1, 1)
103#define TRB_IOC(trb) XHCI_DWORD_EXTRACT((trb).control, 5, 5)
104#define TRB_EVENT_DATA(trb) XHCI_DWORD_EXTRACT((trb).control, 2, 2)
105
106#define TRB_TRANSFER_LENGTH(trb) XHCI_DWORD_EXTRACT((trb).status, 23, 0)
107#define TRB_COMPLETION_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
108
109#define TRB_LINK_SET_TC(trb, val) \
110 xhci_dword_set_bits(&(trb).control, val, 1, 1)
111#define TRB_SET_CYCLE(trb, val) \
112 xhci_dword_set_bits(&(trb).control, val, 0, 0)
113
114#define TRB_CTRL_SET_SETUP_WLENGTH(trb, val) \
115 xhci_qword_set_bits(&(trb).parameter, val, 63, 48)
116#define TRB_CTRL_SET_SETUP_WINDEX(trb, val) \
117 xhci_qword_set_bits(&(trb).parameter, val, 47, 32)
118#define TRB_CTRL_SET_SETUP_WVALUE(trb, val) \
119 xhci_qword_set_bits(&(trb).parameter, val, 31, 16)
120#define TRB_CTRL_SET_SETUP_BREQ(trb, val) \
121 xhci_qword_set_bits(&(trb).parameter, val, 15, 8)
122#define TRB_CTRL_SET_SETUP_BMREQTYPE(trb, val) \
123 xhci_qword_set_bits(&(trb).parameter, val, 7, 0)
124
125#define TRB_CTRL_SET_TD_SIZE(trb, val) \
126 xhci_dword_set_bits(&(trb).status, val, 21, 17)
127#define TRB_CTRL_SET_XFER_LEN(trb, val) \
128 xhci_dword_set_bits(&(trb).status, val, 16, 0)
129
130#define TRB_CTRL_SET_ENT(trb, val) \
131 xhci_dword_set_bits(&(trb).control, val, 1, 1)
132#define TRB_CTRL_SET_ISP(trb, val) \
133 xhci_dword_set_bits(&(trb).control, val, 2, 2)
134#define TRB_CTRL_SET_NS(trb, val) \
135 xhci_dword_set_bits(&(trb).control, val, 3, 3)
136#define TRB_CTRL_SET_CHAIN(trb, val) \
137 xhci_dword_set_bits(&(trb).control, val, 4, 4)
138#define TRB_CTRL_SET_IOC(trb, val) \
139 xhci_dword_set_bits(&(trb).control, val, 5, 5)
140#define TRB_CTRL_SET_IDT(trb, val) \
141 xhci_dword_set_bits(&(trb).control, val, 6, 6)
142
143#define TRB_CTRL_SET_TRB_TYPE(trb, val) \
144 xhci_dword_set_bits(&(trb).control, val, 15, 10)
145#define TRB_CTRL_SET_DIR(trb, val) \
146 xhci_dword_set_bits(&(trb).control, val, 16, 16)
147#define TRB_CTRL_SET_TRT(trb, val) \
148 xhci_dword_set_bits(&(trb).control, val, 17, 16)
149
150#define TRB_ISOCH_SET_TBC(trb, val) \
151 xhci_dword_set_bits(&(trb).control, val, 8, 7)
152#define TRB_ISOCH_SET_TLBPC(trb, val) \
153 xhci_dword_set_bits(&(trb).control, val, 19, 16)
154#define TRB_ISOCH_SET_FRAMEID(trb, val) \
155 xhci_dword_set_bits(&(trb).control, val, 30, 20)
156#define TRB_ISOCH_SET_SIA(trb, val) \
157 xhci_dword_set_bits(&(trb).control, val, 31, 31)
158
159/**
160 * The Chain bit is valid only in specific TRB types.
161 */
162static inline bool xhci_trb_is_chained(xhci_trb_t *trb) {
163 const int type = TRB_TYPE(*trb);
164 const bool chain_bit = XHCI_DWORD_EXTRACT(trb->control, 4, 4);
165
166 return chain_bit &&
167 (type == XHCI_TRB_TYPE_NORMAL
168 || type == XHCI_TRB_TYPE_DATA_STAGE
169 || type == XHCI_TRB_TYPE_STATUS_STAGE
170 || type == XHCI_TRB_TYPE_ISOCH);
171}
172
173static inline void xhci_trb_link_fill(xhci_trb_t *trb, uintptr_t next_phys)
174{
175 // TRBs require 16-byte alignment
176 assert((next_phys & 0xf) == 0);
177
178 xhci_dword_set_bits(&trb->control, XHCI_TRB_TYPE_LINK, 15, 10);
179 xhci_qword_set(&trb->parameter, next_phys);
180}
181
182static inline void xhci_trb_copy_to_pio(xhci_trb_t *dst, xhci_trb_t *src)
183{
184 /*
185 * As we do not know, whether our architecture is capable of copying 16
186 * bytes atomically, let's copy the fields one by one.
187 */
188 dst->parameter = src->parameter;
189 dst->status = src->status;
190
191 write_barrier();
192
193 dst->control = src->control;
194}
195
196static inline void xhci_trb_clean(xhci_trb_t *trb)
197{
198 memset(trb, 0, sizeof(*trb));
199}
200
201/**
202 * Event Ring Segment Table: section 6.5
203 */
204typedef struct xhci_erst_entry {
205 xhci_qword_t rs_base_ptr; /* 64B aligned */
206 xhci_dword_t size; /* only low 16 bits, the rest is RsvdZ */
207 xhci_dword_t _reserved;
208} xhci_erst_entry_t;
209
210static inline void xhci_fill_erst_entry(xhci_erst_entry_t *entry,
211 uintptr_t phys, int segments)
212{
213 xhci_qword_set(&entry->rs_base_ptr, phys);
214 xhci_dword_set_bits(&entry->size, segments, 16, 0);
215}
216
217typedef enum xhci_trb_completion_code {
218 XHCI_TRBC_INVALID = 0,
219 XHCI_TRBC_SUCCESS,
220 XHCI_TRBC_DATA_BUFFER_ERROR,
221 XHCI_TRBC_BABBLE_DETECTED_ERROR,
222 XHCI_TRBC_USB_TRANSACTION_ERROR,
223 XHCI_TRBC_TRB_ERROR,
224 XHCI_TRBC_STALL_ERROR,
225 XHCI_TRBC_RESOURCE_ERROR,
226 XHCI_TRBC_BANDWIDTH_ERROR,
227 XHCI_TRBC_NO_SLOTS_ERROR,
228 XHCI_TRBC_INVALID_STREAM_ERROR,
229 XHCI_TRBC_SLOT_NOT_ENABLED_ERROR,
230 XHCI_TRBC_EP_NOT_ENABLED_ERROR,
231 XHCI_TRBC_SHORT_PACKET,
232 XHCI_TRBC_RING_UNDERRUN,
233 XHCI_TRBC_RING_OVERRUN,
234 XHCI_TRBC_VF_EVENT_RING_FULL,
235 XHCI_TRBC_PARAMETER_ERROR,
236 XHCI_TRBC_BANDWIDTH_OVERRUN_ERROR,
237 XHCI_TRBC_CONTEXT_STATE_ERROR,
238 XHCI_TRBC_NO_PING_RESPONSE_ERROR,
239 XHCI_TRBC_EVENT_RING_FULL_ERROR,
240 XHCI_TRBC_INCOMPATIBLE_DEVICE_ERROR,
241 XHCI_TRBC_MISSED_SERVICE_ERROR,
242 XHCI_TRBC_COMMAND_RING_STOPPED,
243 XHCI_TRBC_COMMAND_ABORTED,
244 XHCI_TRBC_STOPPED,
245 XHCI_TRBC_STOPPED_LENGTH_INVALID,
246 XHCI_TRBC_STOPPED_SHORT_PACKET,
247 XHCI_TRBC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR,
248 /* 30 reserved */
249 XHCI_TRBC_ISOCH_BUFFER_OVERRUN = 31,
250 XHCI_TRBC_EVENT_LOST_ERROR,
251 XHCI_TRBC_UNDEFINED_ERROR,
252 XHCI_TRBC_INVALID_STREAM_ID_ERROR,
253 XHCI_TRBC_SECONDARY_BANDWIDTH_ERROR,
254 XHCI_TRBC_SPLIT_TRANSACTION_ERROR,
255 XHCI_TRBC_MAX
256 /**
257 * 37 - 191 reserved
258 * 192 - 223 vendor defined error
259 * 224 - 255 vendor defined info
260 */
261} xhci_trb_completion_code_t;
262
263#endif
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