| 1 | /*
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| 2 | * Copyright (c) 2017 Ondrej Hlavaty
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * TRB-related structures of the xHC.
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| 34 | *
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| 35 | * This file contains all the types of TRB and the TRB ring handling.
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| 36 | */
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| 37 |
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| 38 | #ifndef XHCI_TRB_H
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| 39 | #define XHCI_TRB_H
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| 40 |
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| 41 | #include "common.h"
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| 42 | #include <libarch/barrier.h>
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| 43 |
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| 44 | /**
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| 45 | * TRB types: section 6.4.6, table 139
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| 46 | */
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| 47 | enum xhci_trb_type {
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| 48 | XHCI_TRB_TYPE_RESERVED = 0,
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| 49 |
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| 50 | // Transfer ring:
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| 51 | XHCI_TRB_TYPE_NORMAL,
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| 52 | XHCI_TRB_TYPE_SETUP_STAGE,
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| 53 | XHCI_TRB_TYPE_DATA_STAGE,
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| 54 | XHCI_TRB_TYPE_STATUS_STAGE,
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| 55 | XHCI_TRB_TYPE_ISOCH,
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| 56 | XHCI_TRB_TYPE_LINK,
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| 57 | XHCI_TRB_TYPE_EVENT_DATA,
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| 58 | XHCI_TRB_TYPE_NO_OP,
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| 59 |
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| 60 | // Command ring:
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| 61 | XHCI_TRB_TYPE_ENABLE_SLOT_CMD,
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| 62 | XHCI_TRB_TYPE_DISABLE_SLOT_CMD,
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| 63 | XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD,
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| 64 | XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD,
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| 65 | XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD,
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| 66 | XHCI_TRB_TYPE_RESET_ENDPOINT_CMD,
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| 67 | XHCI_TRB_TYPE_STOP_ENDPOINT_CMD,
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| 68 | XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD,
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| 69 | XHCI_TRB_TYPE_RESET_DEVICE_CMD,
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| 70 | XHCI_TRB_TYPE_FORCE_EVENT_CMD,
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| 71 | XHCI_TRB_TYPE_NEGOTIATE_BANDWIDTH_CMD,
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| 72 | XHCI_TRB_TYPE_SET_LATENCY_TOLERANCE_VALUE_CMD,
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| 73 | XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD,
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| 74 | XHCI_TRB_TYPE_FORCE_HEADER_CMD,
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| 75 | XHCI_TRB_TYPE_NO_OP_CMD,
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| 76 | // Reserved: 24-31
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| 77 |
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| 78 | // Event ring:
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| 79 | XHCI_TRB_TYPE_TRANSFER_EVENT = 32,
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| 80 | XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT,
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| 81 | XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT,
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| 82 | XHCI_TRB_TYPE_BANDWIDTH_REQUEST_EVENT,
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| 83 | XHCI_TRB_TYPE_DOORBELL_EVENT,
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| 84 | XHCI_TRB_TYPE_HOST_CONTROLLER_EVENT,
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| 85 | XHCI_TRB_TYPE_DEVICE_NOTIFICATION_EVENT,
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| 86 | XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT,
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| 87 |
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| 88 | XHCI_TRB_TYPE_MAX
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| 89 | };
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| 90 |
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| 91 | /**
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| 92 | * TRB template: section 4.11.1
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| 93 | */
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| 94 | typedef struct xhci_trb {
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| 95 | xhci_qword_t parameter;
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| 96 | xhci_dword_t status;
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| 97 | xhci_dword_t control;
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| 98 | } __attribute__((packed)) xhci_trb_t;
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| 99 |
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| 100 | #define TRB_TYPE(trb) XHCI_DWORD_EXTRACT((trb).control, 15, 10)
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| 101 | #define TRB_CYCLE(trb) XHCI_DWORD_EXTRACT((trb).control, 0, 0)
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| 102 | #define TRB_LINK_TC(trb) XHCI_DWORD_EXTRACT((trb).control, 1, 1)
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| 103 | #define TRB_IOC(trb) XHCI_DWORD_EXTRACT((trb).control, 5, 5)
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| 104 |
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| 105 | #define TRB_TRANSFER_LENGTH(trb) XHCI_DWORD_EXTRACT((trb).status, 23, 0)
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| 106 | #define TRB_COMPLETION_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
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| 107 |
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| 108 | #define TRB_LINK_SET_TC(trb, val) \
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| 109 | xhci_dword_set_bits(&(trb).control, val, 1, 1)
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| 110 | #define TRB_SET_CYCLE(trb, val) \
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| 111 | xhci_dword_set_bits(&(trb).control, val, 0, 0)
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| 112 |
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| 113 | #define TRB_CTRL_SET_SETUP_WLENGTH(trb, val) \
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| 114 | xhci_qword_set_bits(&(trb).parameter, val, 63, 48)
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| 115 | #define TRB_CTRL_SET_SETUP_WINDEX(trb, val) \
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| 116 | xhci_qword_set_bits(&(trb).parameter, val, 47, 32)
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| 117 | #define TRB_CTRL_SET_SETUP_WVALUE(trb, val) \
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| 118 | xhci_qword_set_bits(&(trb).parameter, val, 31, 16)
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| 119 | #define TRB_CTRL_SET_SETUP_BREQ(trb, val) \
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| 120 | xhci_qword_set_bits(&(trb).parameter, val, 15, 8)
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| 121 | #define TRB_CTRL_SET_SETUP_BMREQTYPE(trb, val) \
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| 122 | xhci_qword_set_bits(&(trb).parameter, val, 7, 0)
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| 123 |
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| 124 | #define TRB_CTRL_SET_TD_SIZE(trb, val) \
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| 125 | xhci_dword_set_bits(&(trb).status, val, 21, 17)
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| 126 | #define TRB_CTRL_SET_XFER_LEN(trb, val) \
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| 127 | xhci_dword_set_bits(&(trb).status, val, 16, 0)
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| 128 |
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| 129 | #define TRB_CTRL_SET_ENT(trb, val) \
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| 130 | xhci_dword_set_bits(&(trb).control, val, 1, 1)
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| 131 | #define TRB_CTRL_SET_ISP(trb, val) \
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| 132 | xhci_dword_set_bits(&(trb).control, val, 2, 2)
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| 133 | #define TRB_CTRL_SET_NS(trb, val) \
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| 134 | xhci_dword_set_bits(&(trb).control, val, 3, 3)
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| 135 | #define TRB_CTRL_SET_CHAIN(trb, val) \
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| 136 | xhci_dword_set_bits(&(trb).control, val, 4, 4)
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| 137 | #define TRB_CTRL_SET_IOC(trb, val) \
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| 138 | xhci_dword_set_bits(&(trb).control, val, 5, 5)
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| 139 | #define TRB_CTRL_SET_IDT(trb, val) \
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| 140 | xhci_dword_set_bits(&(trb).control, val, 6, 6)
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| 141 |
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| 142 | #define TRB_CTRL_SET_TRB_TYPE(trb, val) \
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| 143 | xhci_dword_set_bits(&(trb).control, val, 15, 10)
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| 144 | #define TRB_CTRL_SET_DIR(trb, val) \
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| 145 | xhci_dword_set_bits(&(trb).control, val, 16, 16)
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| 146 | #define TRB_CTRL_SET_TRT(trb, val) \
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| 147 | xhci_dword_set_bits(&(trb).control, val, 17, 16)
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| 148 |
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| 149 | #define TRB_CTRL_SET_TBC(trb, val) \
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| 150 | xhci_dword_set_bits(&(trb).control, val, 8, 7)
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| 151 | #define TRB_CTRL_SET_TLBPC(trb, val) \
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| 152 | xhci_dword_set_bits(&(trb).control, val, 19, 16)
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| 153 | #define TRB_CTRL_SET_SIA(trb, val) \
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| 154 | xhci_dword_set_bits(&(trb).control, val, 31, 31)
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| 155 |
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| 156 | /**
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| 157 | * The Chain bit is valid only in specific TRB types.
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| 158 | */
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| 159 | static inline bool xhci_trb_is_chained(xhci_trb_t *trb) {
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| 160 | const int type = TRB_TYPE(*trb);
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| 161 | const bool chain_bit = XHCI_DWORD_EXTRACT(trb->control, 4, 4);
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| 162 |
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| 163 | return chain_bit &&
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| 164 | (type == XHCI_TRB_TYPE_NORMAL
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| 165 | || type == XHCI_TRB_TYPE_DATA_STAGE
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| 166 | || type == XHCI_TRB_TYPE_STATUS_STAGE
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| 167 | || type == XHCI_TRB_TYPE_ISOCH);
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| 168 | }
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| 169 |
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| 170 | static inline void xhci_trb_link_fill(xhci_trb_t *trb, uintptr_t next_phys)
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| 171 | {
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| 172 | // TRBs require 16-byte alignment
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| 173 | assert((next_phys & 0xf) == 0);
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| 174 |
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| 175 | xhci_dword_set_bits(&trb->control, XHCI_TRB_TYPE_LINK, 15, 10);
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| 176 | xhci_qword_set(&trb->parameter, next_phys);
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| 177 | }
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| 178 |
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| 179 | static inline void xhci_trb_copy_to_pio(xhci_trb_t *dst, xhci_trb_t *src)
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| 180 | {
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| 181 | /*
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| 182 | * As we do not know, whether our architecture is capable of copying 16
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| 183 | * bytes atomically, let's copy the fields one by one.
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| 184 | */
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| 185 | dst->parameter = src->parameter;
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| 186 | dst->status = src->status;
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| 187 |
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| 188 | write_barrier();
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| 189 |
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| 190 | dst->control = src->control;
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| 191 | }
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| 192 |
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| 193 | static inline void xhci_trb_clean(xhci_trb_t *trb)
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| 194 | {
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| 195 | memset(trb, 0, sizeof(*trb));
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| 196 | }
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| 197 |
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| 198 | /**
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| 199 | * Event Ring Segment Table: section 6.5
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| 200 | */
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| 201 | typedef struct xhci_erst_entry {
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| 202 | xhci_qword_t rs_base_ptr; /* 64B aligned */
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| 203 | xhci_dword_t size; /* only low 16 bits, the rest is RsvdZ */
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| 204 | xhci_dword_t _reserved;
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| 205 | } xhci_erst_entry_t;
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| 206 |
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| 207 | static inline void xhci_fill_erst_entry(xhci_erst_entry_t *entry, uintptr_t phys, int segments)
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| 208 | {
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| 209 | xhci_qword_set(&entry->rs_base_ptr, phys);
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| 210 | xhci_dword_set_bits(&entry->size, segments, 16, 0);
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| 211 | }
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| 212 |
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| 213 | enum xhci_trb_completion_code {
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| 214 | XHCI_TRBC_INVALID = 0,
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| 215 | XHCI_TRBC_SUCCESS,
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| 216 | XHCI_TRBC_DATA_BUFFER_ERROR,
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| 217 | XHCI_TRBC_BABBLE_DETECTED_ERROR,
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| 218 | XHCI_TRBC_USB_TRANSACTION_ERROR,
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| 219 | XHCI_TRBC_TRB_ERROR,
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| 220 | XHCI_TRBC_STALL_ERROR,
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| 221 | XHCI_TRBC_RESOURCE_ERROR,
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| 222 | XHCI_TRBC_BANDWIDTH_ERROR,
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| 223 | XHCI_TRBC_NO_SLOTS_ERROR,
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| 224 | XHCI_TRBC_INVALID_STREAM_ERROR,
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| 225 | XHCI_TRBC_SLOT_NOT_ENABLED_ERROR,
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| 226 | XHCI_TRBC_EP_NOT_ENABLED_ERROR,
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| 227 | XHCI_TRBC_SHORT_PACKET,
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| 228 | XHCI_TRBC_RING_UNDERRUN,
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| 229 | XHCI_TRBC_RING_OVERRUN,
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| 230 | XHCI_TRBC_VF_EVENT_RING_FULL,
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| 231 | XHCI_TRBC_PARAMETER_ERROR,
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| 232 | XHCI_TRBC_BANDWIDTH_OVERRUN_ERROR,
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| 233 | XHCI_TRBC_CONTEXT_STATE_ERROR,
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| 234 | XHCI_TRBC_NO_PING_RESPONSE_ERROR,
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| 235 | XHCI_TRBC_EVENT_RING_FULL_ERROR,
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| 236 | XHCI_TRBC_INCOMPATIBLE_DEVICE_ERROR,
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| 237 | XHCI_TRBC_MISSED_SERVICE_ERROR,
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| 238 | XHCI_TRBC_COMMAND_RING_STOPPED,
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| 239 | XHCI_TRBC_COMMAND_ABORTED,
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| 240 | XHCI_TRBC_STOPPED,
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| 241 | XHCI_TRBC_STOPPED_LENGTH_INVALID,
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| 242 | XHCI_TRBC_STOPPED_SHORT_PACKET,
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| 243 | XHCI_TRBC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR,
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| 244 | /* 30 reserved */
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| 245 | XHCI_TRBC_ISOCH_BUFFER_OVERRUN = 31,
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| 246 | XHCI_TRBC_EVENT_LOST_ERROR,
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| 247 | XHCI_TRBC_UNDEFINED_ERROR,
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| 248 | XHCI_TRBC_INVALID_STREAM_ID_ERROR,
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| 249 | XHCI_TRBC_SECONDARY_BANDWIDTH_ERROR,
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| 250 | XHCI_TRBC_SPLIT_TRANSACTION_ERROR,
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| 251 | XHCI_TRBC_MAX
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| 252 | /**
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| 253 | * 37 - 191 reserved
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| 254 | * 192 - 223 vendor defined error
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| 255 | * 224 - 255 vendor defined info
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| 256 | */
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| 257 | };
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| 258 |
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| 259 | #endif
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