| 1 | /*
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| 2 | * Copyright (c) 2017 Ondrej Hlavaty
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * Memory-mapped register structures of the xHC.
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| 34 | *
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| 35 | * The main pr
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| 36 | */
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| 37 |
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| 38 | #ifndef XHCI_REGS_H
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| 39 | #define XHCI_REGS_H
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| 40 |
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| 41 | #include <macros.h>
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| 42 | #include <ddi.h>
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| 43 | #include "common.h"
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| 44 |
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| 45 | #define XHCI_PIO_CHANGE_UDELAY 5
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| 46 |
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| 47 | /*
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| 48 | * These four are the main macros to be used.
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| 49 | * Semantics is usual - READ reads value, WRITE changes value, SET sets
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| 50 | * selected bits, CLEAR clears selected bits to 0.
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| 51 | *
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| 52 | * The key thing here is the order of macro expansion, expanding the reg_spec
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| 53 | * argument as more arguments (comma delimited) for the inner macro.
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| 54 | */
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| 55 | #define XHCI_REG_RD(reg_set, reg_spec) XHCI_REG_RD_INNER(reg_set, reg_spec)
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| 56 | #define XHCI_REG_WR(reg_set, reg_spec, value) XHCI_REG_WR_INNER(reg_set, value, reg_spec)
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| 57 | #define XHCI_REG_SET(reg_set, reg_spec, value) XHCI_REG_SET_INNER(reg_set, value, reg_spec)
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| 58 | #define XHCI_REG_CLR(reg_set, reg_spec, value) XHCI_REG_CLR_INNER(reg_set, value, reg_spec)
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| 59 | #define XHCI_REG_MASK(reg_spec) XHCI_REG_MASK_INNER(reg_spec)
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| 60 | #define XHCI_REG_SHIFT(reg_spec) XHCI_REG_SHIFT_INNER(reg_spec)
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| 61 |
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| 62 | /*
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| 63 | * These take a pointer to the field, and selects the type-specific macro.
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| 64 | */
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| 65 | #define XHCI_REG_RD_INNER(reg_set, field, size, type, ...) \
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| 66 | XHCI_REG_RD_##type(&((reg_set)->field), size, ##__VA_ARGS__)
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| 67 |
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| 68 | #define XHCI_REG_WR_INNER(reg_set, value, field, size, type, ...) \
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| 69 | XHCI_REG_WR_##type(&(reg_set)->field, value, size, ##__VA_ARGS__)
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| 70 |
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| 71 | #define XHCI_REG_SET_INNER(reg_set, value, field, size, type, ...) \
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| 72 | XHCI_REG_SET_##type(&(reg_set)->field, value, size, ##__VA_ARGS__)
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| 73 |
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| 74 | #define XHCI_REG_CLR_INNER(reg_set, value, field, size, type, ...) \
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| 75 | XHCI_REG_CLR_##type(&(reg_set)->field, value, size, ##__VA_ARGS__)
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| 76 |
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| 77 | #define XHCI_REG_MASK_INNER(field, size, type, ...) \
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| 78 | XHCI_REG_MASK_##type(size, ##__VA_ARGS__)
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| 79 |
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| 80 | #define XHCI_REG_SHIFT_INNER(field, size, type, ...) \
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| 81 | XHCI_REG_SHIFT_##type(size, ##__VA_ARGS__)
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| 82 |
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| 83 | /*
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| 84 | * Field handling is the easiest. Just do it with whole field.
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| 85 | */
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| 86 | #define XHCI_REG_RD_FIELD(ptr, size) \
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| 87 | xhci2host(size, pio_read_##size((ptr)))
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| 88 | #define XHCI_REG_WR_FIELD(ptr, value, size) \
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| 89 | pio_write_##size((ptr), host2xhci(size, value))
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| 90 | #define XHCI_REG_SET_FIELD(ptr, value, size) \
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| 91 | pio_set_##size((ptr), host2xhci(size, value), XHCI_PIO_CHANGE_UDELAY);
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| 92 | #define XHCI_REG_CLR_FIELD(ptr, value, size) \
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| 93 | pio_clear_##size((ptr), host2xhci(size, value), XHCI_PIO_CHANGE_UDELAY);
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| 94 | #define XHCI_REG_MASK_FIELD(size) (~((uint##size##_t) 0))
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| 95 | #define XHCI_REG_SHIFT_FIELD(size) (0)
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| 96 |
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| 97 | /*
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| 98 | * Flags are just trivial case of ranges.
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| 99 | */
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| 100 | #define XHCI_REG_RD_FLAG(ptr, size, offset) \
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| 101 | XHCI_REG_RD_RANGE((ptr), size, (offset), (offset))
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| 102 | #define XHCI_REG_WR_FLAG(ptr, value, size, offset) \
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| 103 | XHCI_REG_WR_RANGE((ptr), (value), size, (offset), (offset))
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| 104 | #define XHCI_REG_SET_FLAG(ptr, value, size, offset) \
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| 105 | XHCI_REG_SET_RANGE((ptr), (value), size, (offset), (offset))
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| 106 | #define XHCI_REG_CLR_FLAG(ptr, value, size, offset) \
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| 107 | XHCI_REG_CLR_RANGE((ptr), (value), size, (offset), (offset))
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| 108 | #define XHCI_REG_MASK_FLAG(size, offset) BIT_V(uint##size##_t, offset)
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| 109 | #define XHCI_REG_SHIFT_FLAG(size, offset) (offset)
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| 110 |
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| 111 | /*
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| 112 | * Ranges are the most difficult. We need to play around with bitmasks.
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| 113 | */
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| 114 | #define XHCI_REG_RD_RANGE(ptr, size, hi, lo) \
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| 115 | BIT_RANGE_EXTRACT(uint##size##_t, (hi), (lo), XHCI_REG_RD_FIELD((ptr), size))
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| 116 |
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| 117 | #define XHCI_REG_WR_RANGE(ptr, value, size, hi, lo) \
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| 118 | pio_change_##size((ptr), host2xhci(size, BIT_RANGE_INSERT(uint##size##_t, \
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| 119 | (hi), (lo), (value))), \
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| 120 | host2xhci(size, BIT_RANGE(uint##size##_t, (hi), (lo))), \
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| 121 | XHCI_PIO_CHANGE_UDELAY);
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| 122 |
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| 123 | #define XHCI_REG_SET_RANGE(ptr, value, size, hi, lo) \
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| 124 | pio_set_##size((ptr), host2xhci(size, BIT_RANGE_INSERT(uint##size##_t, \
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| 125 | (hi), (lo), (value))), \
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| 126 | XHCI_PIO_CHANGE_UDELAY);
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| 127 |
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| 128 | #define XHCI_REG_CLR_RANGE(ptr, value, size, hi, lo) \
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| 129 | pio_clear_##size((ptr), host2xhci(size, BIT_RANGE_INSERT(uint##size##_t, \
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| 130 | (hi), (lo), (value))), \
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| 131 | XHCI_PIO_CHANGE_UDELAY);
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| 132 |
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| 133 | #define XHCI_REG_MASK_RANGE(size, hi, lo) BIT_RANGE(uint##size##_t, hi, lo)
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| 134 | #define XHCI_REG_SHIFT_RANGE(size, hi, lo) (lo)
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| 135 |
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| 136 | /** HC capability registers: section 5.3 */
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| 137 | typedef const struct xhci_cap_regs {
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| 138 |
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| 139 | /* Size of this structure, offset for the operation registers */
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| 140 | const ioport8_t caplength;
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| 141 |
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| 142 | const PADD8;
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| 143 |
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| 144 | /* BCD of specification version */
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| 145 | const ioport16_t hciversion;
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| 146 |
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| 147 | /*
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| 148 | * 7:0 - MaxSlots
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| 149 | * 18:8 - MaxIntrs
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| 150 | * 31:24 - MaxPorts
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| 151 | */
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| 152 | const ioport32_t hcsparams1;
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| 153 |
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| 154 | /*
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| 155 | * 3:0 - IST
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| 156 | * 7:4 - ERST Max
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| 157 | * 25:21 - Max Scratchpad Bufs Hi
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| 158 | * 26 - SPR
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| 159 | * 31:27 - Max Scratchpad Bufs Lo
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| 160 | */
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| 161 | const ioport32_t hcsparams2;
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| 162 |
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| 163 | /*
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| 164 | * 7:0 - U1 Device Exit Latency
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| 165 | * 31:16 - U2 Device Exit Latency
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| 166 | */
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| 167 | const ioport32_t hcsparams3;
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| 168 |
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| 169 | /*
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| 170 | * 11 10 9 8 7 6 5 4 3 2 1 0
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| 171 | * 11:0 - CFC SEC SPC PAE NSS LTC C PIND PPC CSZ BNC AC64
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| 172 | * 15:12 - MaxPSASize
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| 173 | * 31:16 - xECP
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| 174 | */
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| 175 | const ioport32_t hccparams1;
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| 176 |
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| 177 | /*
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| 178 | * 31:2 - Doorbell Array Offset
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| 179 | */
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| 180 | const ioport32_t dboff;
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| 181 |
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| 182 | /*
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| 183 | * 31:5 - Runtime Register Space Offset
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| 184 | */
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| 185 | const ioport32_t rtsoff;
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| 186 |
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| 187 | /*
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| 188 | * 5 4 3 2 1 0
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| 189 | * 5:0 - Flags: CIC LEC CTC FSC CMC U3C
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| 190 | */
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| 191 | const ioport32_t hccparams2;
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| 192 |
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| 193 | // the rest to operational registers is reserved
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| 194 | } xhci_cap_regs_t;
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| 195 |
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| 196 | /*
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| 197 | * The register specifiers are to be used as the reg_spec argument.
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| 198 | *
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| 199 | * The values are field, bitsize, type, (type specific args)
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| 200 | * When the type is RANGE: hi, lo
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| 201 | */
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| 202 | #define XHCI_CAP_LENGTH caplength, 8, FIELD
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| 203 | #define XHCI_CAP_VERSION hciversion, 16, FIELD
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| 204 | #define XHCI_CAP_MAX_SLOTS hcsparams1, 32, RANGE, 7, 0
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| 205 | #define XHCI_CAP_MAX_INTRS hcsparams1, 32, RANGE, 18, 8
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| 206 | #define XHCI_CAP_MAX_PORTS hcsparams1, 32, RANGE, 31, 24
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| 207 | #define XHCI_CAP_IST hcsparams2, 32, RANGE, 3, 0
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| 208 | #define XHCI_CAP_ERST_MAX hcsparams2, 32, RANGE, 7, 4
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| 209 | #define XHCI_CAP_MAX_SPBUF_HI hcsparams2, 32, RANGE, 25, 21
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| 210 | #define XHCI_CAP_SPR hcsparams2, 32, FLAG, 26
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| 211 | #define XHCI_CAP_MAX_SPBUF_LO hcsparams2, 32, RANGE, 31, 27
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| 212 | #define XHCI_CAP_U1EL hcsparams3, 32, RANGE, 7, 0
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| 213 | #define XHCI_CAP_U2EL hcsparams3, 32, RANGE, 31, 16
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| 214 | #define XHCI_CAP_AC64 hccparams1, 32, FLAG, 0
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| 215 | #define XHCI_CAP_BNC hccparams1, 32, FLAG, 1
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| 216 | #define XHCI_CAP_CSZ hccparams1, 32, FLAG, 2
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| 217 | #define XHCI_CAP_PPC hccparams1, 32, FLAG, 3
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| 218 | #define XHCI_CAP_PIND hccparams1, 32, FLAG, 4
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| 219 | #define XHCI_CAP_C hccparams1, 32, FLAG, 5
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| 220 | #define XHCI_CAP_LTC hccparams1, 32, FLAG, 6
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| 221 | #define XHCI_CAP_NSS hccparams1, 32, FLAG, 7
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| 222 | #define XHCI_CAP_PAE hccparams1, 32, FLAG, 8
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| 223 | #define XHCI_CAP_SPC hccparams1, 32, FLAG, 9
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| 224 | #define XHCI_CAP_SEC hccparams1, 32, FLAG, 10
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| 225 | #define XHCI_CAP_CFC hccparams1, 32, FLAG, 11
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| 226 | #define XHCI_CAP_MAX_PSA_SIZE hccparams1, 32, RANGE, 15, 12
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| 227 | #define XHCI_CAP_XECP hccparams1, 32, RANGE, 31, 16
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| 228 | #define XHCI_CAP_DBOFF dboff, 32, FIELD
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| 229 | #define XHCI_CAP_RTSOFF rtsoff, 32, FIELD
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| 230 | #define XHCI_CAP_U3C hccparams2, 32, FLAG, 0
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| 231 | #define XHCI_CAP_CMC hccparams2, 32, FLAG, 1
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| 232 | #define XHCI_CAP_FSC hccparams2, 32, FLAG, 2
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| 233 | #define XHCI_CAP_CTC hccparams2, 32, FLAG, 3
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| 234 | #define XHCI_CAP_LEC hccparams2, 32, FLAG, 4
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| 235 | #define XHCI_CAP_CIC hccparams2, 32, FLAG, 5
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| 236 |
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| 237 | static inline unsigned xhci_get_max_spbuf(xhci_cap_regs_t *cap_regs) {
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| 238 | return XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_HI) << 5
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| 239 | | XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_LO);
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| 240 | }
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| 241 |
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| 242 | /**
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| 243 | * XHCI Port Register Set: section 5.4, table 32
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| 244 | */
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| 245 | typedef struct xhci_port_regs {
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| 246 | /*
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| 247 | * 4 3 2 1 0
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| 248 | * 4:0 - PR OCA Z PED CCS
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| 249 | * 8:5 - PLS
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| 250 | * 9 - PP
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| 251 | * 13:10 - Port Speed
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| 252 | * 15:14 - PIC
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| 253 | * 27 26 25 24 23 22 21 20 19 18 17 16
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| 254 | * 27:16 - WOE WDE WCE CAS CEC PLC PRC OCC WRC PEC CSC LWS
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| 255 | * 30 - DR
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| 256 | * 31 - WPR
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| 257 | */
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| 258 | ioport32_t portsc;
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| 259 |
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| 260 | /*
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| 261 | * Contents of this fields depends on the protocol supported by the port.
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| 262 | * USB3:
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| 263 | * 7:0 - U1 Timeout
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| 264 | * 15:8 - U2 Timeout
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| 265 | * 16 - Force Link PM Accept
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| 266 | * USB2:
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| 267 | * 2:0 - L1S
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| 268 | * 3 - RWE
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| 269 | * 7:4 - BESL
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| 270 | * 15:8 - L1 Device Slot
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| 271 | * 16 - HLE
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| 272 | * 31:28 - Test Mode
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| 273 | */
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| 274 | ioport32_t portpmsc;
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| 275 |
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| 276 | /*
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| 277 | * This field is valid only for USB3 ports.
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| 278 | * 15:0 - Link Error Count
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| 279 | * 19:16 - RLC
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| 280 | * 23:20 - TLC
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| 281 | */
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| 282 | ioport32_t portli;
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| 283 |
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| 284 | /*
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| 285 | * This field is valid only for USB2 ports.
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| 286 | * 1:0 - HIRDM
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| 287 | * 9:2 - L1 Timeout
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| 288 | * 13:10 - BESLD
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| 289 | */
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| 290 | ioport32_t porthlpmc;
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| 291 | } xhci_port_regs_t;
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| 292 |
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| 293 | #define XHCI_PORT_CCS portsc, 32, FLAG, 0
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| 294 | #define XHCI_PORT_PED portsc, 32, FLAG, 1
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| 295 | #define XHCI_PORT_OCA portsc, 32, FLAG, 3
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| 296 | #define XHCI_PORT_PR portsc, 32, FLAG, 4
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| 297 | #define XHCI_PORT_PLS portsc, 32, RANGE, 8, 5
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| 298 | #define XHCI_PORT_PP portsc, 32, FLAG, 9
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| 299 | #define XHCI_PORT_PS portsc, 32, RANGE, 13, 10
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| 300 | #define XHCI_PORT_PIC portsc, 32, RANGE, 15, 14
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| 301 | #define XHCI_PORT_LWS portsc, 32, FLAG, 16
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| 302 | #define XHCI_PORT_CSC portsc, 32, FLAG, 17
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| 303 | #define XHCI_PORT_PEC portsc, 32, FLAG, 18
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| 304 | #define XHCI_PORT_WRC portsc, 32, FLAG, 19
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| 305 | #define XHCI_PORT_OCC portsc, 32, FLAG, 20
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| 306 | #define XHCI_PORT_PRC portsc, 32, FLAG, 21
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| 307 | #define XHCI_PORT_PLC portsc, 32, FLAG, 22
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| 308 | #define XHCI_PORT_CEC portsc, 32, FLAG, 23
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| 309 | #define XHCI_PORT_CAS portsc, 32, FLAG, 24
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| 310 | #define XHCI_PORT_WCE portsc, 32, FLAG, 25
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| 311 | #define XHCI_PORT_WDE portsc, 32, FLAG, 26
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| 312 | #define XHCI_PORT_WOE portsc, 32, FLAG, 27
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| 313 | #define XHCI_PORT_DR portsc, 32, FLAG, 30
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| 314 | #define XHCI_PORT_WPR portsc, 32, FLAG, 31
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| 315 |
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| 316 | #define XHCI_PORT_USB3_U1TO portpmsc, 32, RANGE, 7, 0
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| 317 | #define XHCI_PORT_USB3_U2TO portpmsc, 32, RANGE, 15, 8
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| 318 | #define XHCI_PORT_USB3_FLPMA portpmsc, 32, FLAG, 16
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| 319 | #define XHCI_PORT_USB3_LEC portli, 32, RANGE, 15, 0
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| 320 | #define XHCI_PORT_USB3_RLC portli, 32, RANGE, 19, 16
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| 321 | #define XHCI_PORT_USB3_TLC portli, 32, RANGE, 23, 20
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| 322 |
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| 323 | #define XHCI_PORT_USB2_L1S portpmsc, 32, RANGE, 2, 0
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| 324 | #define XHCI_PORT_USB2_RWE portpmsc, 32, FLAG, 3
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| 325 | #define XHCI_PORT_USB2_BESL portpmsc, 32, RANGE, 7, 4
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| 326 | #define XHCI_PORT_USB2_L1DS portpmsc, 32, RANGE, 15, 8
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| 327 | #define XHCI_PORT_USB2_HLE portpmsc, 32, FLAG, 16
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| 328 | #define XHCI_PORT_USB2_TM portpmsc, 32, RANGE, 31, 28
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| 329 | #define XHCI_PORT_USB2_HIRDM porthlpmc, 32, RANGE, 1, 0
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| 330 | #define XHCI_PORT_USB2_L1TO porthlpmc, 32, RANGE, 9, 2
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| 331 | #define XHCI_PORT_USB2_BESLD porthlpmc, 32, RANGE, 13, 10
|
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| 332 |
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| 333 | /**
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| 334 | * XHCI Operational Registers: section 5.4
|
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| 335 | */
|
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| 336 | typedef struct xhci_op_regs {
|
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| 337 |
|
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| 338 | /*
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| 339 | * 3 2 1 0
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| 340 | * 3:0 - HSEE INTE HCRST R/S
|
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| 341 | *
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| 342 | * 11 10 9 8 7
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| 343 | * 11:7 - EU3S EWE CRS CSS LHCRST
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| 344 | * 13 - CME
|
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| 345 | */
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| 346 | ioport32_t usbcmd;
|
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| 347 |
|
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| 348 | /*
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| 349 | * 4 3 2 1 0
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| 350 | * 4:0 - PCD EINT HSE _ HCH
|
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| 351 | *
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| 352 | * 12 11 10 9 8
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| 353 | * 12:8 - HCE CNR SRE RSS SSS
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| 354 | */
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| 355 | ioport32_t usbsts;
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| 356 |
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| 357 | /*
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| 358 | * Bitmask of page sizes supported: 128M .. 4K
|
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| 359 | */
|
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| 360 | ioport32_t pagesize;
|
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| 361 |
|
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| 362 | PADD32[2];
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| 363 |
|
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| 364 | /*
|
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| 365 | * 15:0 - Notification enable
|
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| 366 | */
|
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| 367 | ioport32_t dnctrl;
|
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| 368 |
|
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| 369 | /* 3 2 1 0
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| 370 | * 3:0 - CRR CA CS RCS
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| 371 | * 64:6 - Command Ring Pointer
|
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| 372 | */
|
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| 373 | ioport32_t crcr_lo;
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| 374 | ioport32_t crcr_hi;
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| 375 |
|
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| 376 | PADD32[4];
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| 377 |
|
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| 378 | ioport32_t dcbaap_lo;
|
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| 379 | ioport32_t dcbaap_hi;
|
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| 380 |
|
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| 381 | /*
|
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| 382 | * 7:0 - MaxSlotsEn
|
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| 383 | * 8 - U3E
|
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| 384 | * 9 - CIE
|
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| 385 | */
|
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| 386 | ioport32_t config;
|
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| 387 |
|
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| 388 | /* Offset of portrs from op_regs addr is 0x400. */
|
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| 389 | PADD32[241];
|
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| 390 |
|
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| 391 | /*
|
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| 392 | * Individual ports register sets
|
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| 393 | */
|
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| 394 | xhci_port_regs_t portrs[256];
|
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| 395 | } xhci_op_regs_t;
|
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| 396 |
|
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| 397 | #define XHCI_OP_RS usbcmd, 32, FLAG, 0
|
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| 398 | #define XHCI_OP_HCRST usbcmd, 32, FLAG, 1
|
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| 399 | #define XHCI_OP_INTE usbcmd, 32, FLAG, 2
|
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| 400 | #define XHCI_OP_HSEE usbcmd, 32, FLAG, 3
|
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| 401 | #define XHCI_OP_LHCRST usbcmd, 32, FLAG, 7
|
|---|
| 402 | #define XHCI_OP_CSS usbcmd, 32, FLAG, 8
|
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| 403 | #define XHCI_OP_CRS usbcmd, 32, FLAG, 9
|
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| 404 | #define XHCI_OP_EWE usbcmd, 32, FLAG, 10
|
|---|
| 405 | #define XHCI_OP_EU3S usbcmd, 32, FLAG, 11
|
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| 406 | #define XHCI_OP_CME usbcmd, 32, FLAG, 13
|
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| 407 | #define XHCI_OP_HCH usbsts, 32, FLAG, 0
|
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| 408 | #define XHCI_OP_HSE usbsts, 32, FLAG, 2
|
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| 409 | #define XHCI_OP_EINT usbsts, 32, FLAG, 3
|
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| 410 | #define XHCI_OP_PCD usbsts, 32, FLAG, 4
|
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| 411 | #define XHCI_OP_SSS usbsts, 32, FLAG, 8
|
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| 412 | #define XHCI_OP_RSS usbsts, 32, FLAG, 9
|
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| 413 | #define XHCI_OP_SRE usbsts, 32, FLAG, 10
|
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| 414 | #define XHCI_OP_CNR usbsts, 32, FLAG, 11
|
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| 415 | #define XHCI_OP_HCE usbsts, 32, FLAG, 12
|
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| 416 | #define XHCI_OP_PAGESIZE pagesize, 32, FIELD
|
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| 417 | #define XHCI_OP_NOTIFICATION dnctrl, 32, RANGE, 15, 0
|
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| 418 | #define XHCI_OP_RCS crcr_lo, 32, FLAG, 0
|
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| 419 | #define XHCI_OP_CS crcr_lo, 32, FLAG, 1
|
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| 420 | #define XHCI_OP_CA crcr_lo, 32, FLAG, 2
|
|---|
| 421 | #define XHCI_OP_CRR crcr_lo, 32, FLAG, 3
|
|---|
| 422 | /*
|
|---|
| 423 | * This shall be RANGE, 6, 0, but the value containing CR pointer and RCS flag
|
|---|
| 424 | * must be written at once.
|
|---|
| 425 | */
|
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| 426 | #define XHCI_OP_CRCR_LO crcr_lo, 32, FIELD
|
|---|
| 427 | #define XHCI_OP_CRCR_HI crcr_hi, 32, FIELD
|
|---|
| 428 | #define XHCI_OP_DCBAAP_LO dcbaap_lo, 32, FIELD
|
|---|
| 429 | #define XHCI_OP_DCBAAP_HI dcbaap_hi, 32, FIELD
|
|---|
| 430 | #define XHCI_OP_MAX_SLOTS_EN config, 32, RANGE, 7, 0
|
|---|
| 431 | #define XHCI_OP_U3E config, 32, FLAG, 8
|
|---|
| 432 | #define XHCI_OP_CIE config, 32, FLAG, 9
|
|---|
| 433 |
|
|---|
| 434 | /* Aggregating field to read & write whole status at once */
|
|---|
| 435 | #define XHCI_OP_STATUS usbsts, 32, RANGE, 12, 0
|
|---|
| 436 |
|
|---|
| 437 | /* RW1C fields in usbsts */
|
|---|
| 438 | #define XHCI_STATUS_ACK_MASK 0x41C
|
|---|
| 439 |
|
|---|
| 440 | /**
|
|---|
| 441 | * Interrupter Register Set: section 5.5.2
|
|---|
| 442 | */
|
|---|
| 443 | typedef struct xhci_interrupter_regs {
|
|---|
| 444 | /*
|
|---|
| 445 | * 0 - Interrupt Pending
|
|---|
| 446 | * 1 - Interrupt Enable
|
|---|
| 447 | */
|
|---|
| 448 | ioport32_t iman;
|
|---|
| 449 |
|
|---|
| 450 | /*
|
|---|
| 451 | * 15:0 - Interrupt Moderation Interval
|
|---|
| 452 | * 31:16 - Interrupt Moderation Counter
|
|---|
| 453 | */
|
|---|
| 454 | ioport32_t imod;
|
|---|
| 455 |
|
|---|
| 456 | ioport32_t erstsz;
|
|---|
| 457 |
|
|---|
| 458 | PADD32;
|
|---|
| 459 |
|
|---|
| 460 | ioport32_t erstba_lo;
|
|---|
| 461 | ioport32_t erstba_hi;
|
|---|
| 462 |
|
|---|
| 463 | /*
|
|---|
| 464 | * 2:0 - Dequeue ERST Segment Index
|
|---|
| 465 | * 3 - Event Handler Busy
|
|---|
| 466 | * 63:4 - Event Ring Dequeue Pointer
|
|---|
| 467 | */
|
|---|
| 468 | ioport32_t erdp_lo;
|
|---|
| 469 | ioport32_t erdp_hi;
|
|---|
| 470 | } xhci_interrupter_regs_t;
|
|---|
| 471 |
|
|---|
| 472 | #define XHCI_INTR_IP iman, 32, FLAG, 0
|
|---|
| 473 | #define XHCI_INTR_IE iman, 32, FLAG, 1
|
|---|
| 474 | #define XHCI_INTR_IMI imod, 32, RANGE, 15, 0
|
|---|
| 475 | #define XHCI_INTR_IMC imod, 32, RANGE, 31, 16
|
|---|
| 476 | #define XHCI_INTR_ERSTSZ erstsz, 32, FIELD
|
|---|
| 477 | #define XHCI_INTR_ERSTBA_LO erstba_lo, 32, FIELD
|
|---|
| 478 | #define XHCI_INTR_ERSTBA_HI erstba_hi, 32, FIELD
|
|---|
| 479 | #define XHCI_INTR_ERDP_ESI erdp_lo, 32, RANGE, 2, 0
|
|---|
| 480 | #define XHCI_INTR_ERDP_EHB erdp_lo, 32, FLAG, 3
|
|---|
| 481 | #define XHCI_INTR_ERDP_LO erdp_lo, 32, FIELD
|
|---|
| 482 | #define XHCI_INTR_ERDP_HI erdp_hi, 32, FIELD
|
|---|
| 483 |
|
|---|
| 484 | /**
|
|---|
| 485 | * XHCI Runtime registers: section 5.5
|
|---|
| 486 | */
|
|---|
| 487 | typedef struct xhci_rt_regs {
|
|---|
| 488 | ioport32_t mfindex;
|
|---|
| 489 |
|
|---|
| 490 | PADD32 [7];
|
|---|
| 491 |
|
|---|
| 492 | xhci_interrupter_regs_t ir [];
|
|---|
| 493 | } xhci_rt_regs_t;
|
|---|
| 494 |
|
|---|
| 495 | #define XHCI_RT_MFINDEX mfindex, 32, RANGE, 13, 0
|
|---|
| 496 | #define XHCI_MFINDEX_MAX (1 << 14)
|
|---|
| 497 |
|
|---|
| 498 | /**
|
|---|
| 499 | * XHCI Doorbell Registers: section 5.6
|
|---|
| 500 | *
|
|---|
| 501 | * These registers are to be written as a whole field.
|
|---|
| 502 | */
|
|---|
| 503 | typedef ioport32_t xhci_doorbell_t;
|
|---|
| 504 |
|
|---|
| 505 | enum xhci_plt {
|
|---|
| 506 | XHCI_PSI_PLT_SYMM,
|
|---|
| 507 | XHCI_PSI_PLT_RSVD,
|
|---|
| 508 | XHCI_PSI_PLT_RX,
|
|---|
| 509 | XHCI_PSI_PLT_TX
|
|---|
| 510 | };
|
|---|
| 511 |
|
|---|
| 512 | /**
|
|---|
| 513 | * Protocol speed ID: section 7.2.1
|
|---|
| 514 | */
|
|---|
| 515 | typedef struct xhci_psi {
|
|---|
| 516 | xhci_dword_t psi;
|
|---|
| 517 | } xhci_psi_t;
|
|---|
| 518 |
|
|---|
| 519 | #define XHCI_PSI_PSIV psi, 32, RANGE, 3, 0
|
|---|
| 520 | #define XHCI_PSI_PSIE psi, 32, RANGE, 5, 4
|
|---|
| 521 | #define XHCI_PSI_PLT psi, 32, RANGE, 7, 6
|
|---|
| 522 | #define XHCI_PSI_PFD psi, 32, FLAG, 8
|
|---|
| 523 | #define XHCI_PSI_PSIM psi, 32, RANGE, 31, 16
|
|---|
| 524 |
|
|---|
| 525 | enum xhci_extcap_type {
|
|---|
| 526 | XHCI_EC_RESERVED = 0,
|
|---|
| 527 | XHCI_EC_USB_LEGACY,
|
|---|
| 528 | XHCI_EC_SUPPORTED_PROTOCOL,
|
|---|
| 529 | XHCI_EC_EXTENDED_POWER_MANAGEMENT,
|
|---|
| 530 | XHCI_EC_IOV,
|
|---|
| 531 | XHCI_EC_MSI,
|
|---|
| 532 | XHCI_EC_LOCALMEM,
|
|---|
| 533 | XHCI_EC_DEBUG = 10,
|
|---|
| 534 | XHCI_EC_MSIX = 17,
|
|---|
| 535 | XHCI_EC_MAX = 255
|
|---|
| 536 | };
|
|---|
| 537 |
|
|---|
| 538 | /**
|
|---|
| 539 | * xHCI Extended Capability: section 7
|
|---|
| 540 | */
|
|---|
| 541 | typedef struct xhci_extcap {
|
|---|
| 542 | xhci_dword_t header;
|
|---|
| 543 | xhci_dword_t cap_specific[];
|
|---|
| 544 | } xhci_extcap_t;
|
|---|
| 545 |
|
|---|
| 546 | #define XHCI_EC_CAP_ID header, 32, RANGE, 7, 0
|
|---|
| 547 | #define XHCI_EC_SIZE header, 32, RANGE, 15, 8
|
|---|
| 548 |
|
|---|
| 549 | /* Supported protocol */
|
|---|
| 550 | #define XHCI_EC_SP_MINOR header, 32, RANGE, 23, 16
|
|---|
| 551 | #define XHCI_EC_SP_MAJOR header, 32, RANGE, 31, 24
|
|---|
| 552 | #define XHCI_EC_SP_NAME cap_specific[0], 32, FIELD
|
|---|
| 553 | #define XHCI_EC_SP_CP_OFF cap_specific[1], 32, RANGE, 7, 0
|
|---|
| 554 | #define XHCI_EC_SP_CP_COUNT cap_specific[1], 32, RANGE, 15, 8
|
|---|
| 555 | #define XHCI_EC_SP_PSIC cap_specific[1], 32, RANGE, 31, 28
|
|---|
| 556 | #define XHCI_EC_SP_SLOT_TYPE cap_specific[2], 32, RANGE, 4, 0
|
|---|
| 557 |
|
|---|
| 558 | typedef union {
|
|---|
| 559 | char str [4];
|
|---|
| 560 | uint32_t packed;
|
|---|
| 561 | } xhci_sp_name_t;
|
|---|
| 562 |
|
|---|
| 563 | static const xhci_sp_name_t xhci_name_usb = {
|
|---|
| 564 | .str = "USB "
|
|---|
| 565 | };
|
|---|
| 566 |
|
|---|
| 567 | static inline xhci_extcap_t *xhci_extcap_next(const xhci_extcap_t *cur)
|
|---|
| 568 | {
|
|---|
| 569 | unsigned dword_offset = XHCI_REG_RD(cur, XHCI_EC_SIZE);
|
|---|
| 570 | if (!dword_offset)
|
|---|
| 571 | return NULL;
|
|---|
| 572 | return (xhci_extcap_t *) (((xhci_dword_t *) cur) + dword_offset);
|
|---|
| 573 | }
|
|---|
| 574 |
|
|---|
| 575 | static inline xhci_psi_t *xhci_extcap_psi(const xhci_extcap_t *ec, unsigned psid)
|
|---|
| 576 | {
|
|---|
| 577 | assert(XHCI_REG_RD(ec, XHCI_EC_CAP_ID) == XHCI_EC_SUPPORTED_PROTOCOL);
|
|---|
| 578 | assert(XHCI_REG_RD(ec, XHCI_EC_SP_PSIC) > psid);
|
|---|
| 579 |
|
|---|
| 580 | unsigned dword_offset = 4 + psid;
|
|---|
| 581 | return (xhci_psi_t *) (((xhci_dword_t *) ec) + dword_offset);
|
|---|
| 582 | }
|
|---|
| 583 |
|
|---|
| 584 | /**
|
|---|
| 585 | * USB Legacy Support: section 7.1
|
|---|
| 586 | *
|
|---|
| 587 | * Legacy support have an exception from dword-access, because it needs to be
|
|---|
| 588 | * byte-accessed.
|
|---|
| 589 | */
|
|---|
| 590 | typedef struct xhci_extcap_legsup {
|
|---|
| 591 | ioport8_t cap_id;
|
|---|
| 592 | ioport8_t size; /**< Next Capability Pointer */
|
|---|
| 593 | ioport8_t sem_bios;
|
|---|
| 594 | ioport8_t sem_os;
|
|---|
| 595 |
|
|---|
| 596 | /** USB Legacy Support Control/Status - RW for BIOS, RO for OS */
|
|---|
| 597 | xhci_dword_t usblegctlsts;
|
|---|
| 598 | } xhci_legsup_t;
|
|---|
| 599 |
|
|---|
| 600 | #define XHCI_LEGSUP_SEM_BIOS sem_bios, 8, FLAG, 0
|
|---|
| 601 | #define XHCI_LEGSUP_SEM_OS sem_os, 8, FLAG, 0
|
|---|
| 602 |
|
|---|
| 603 | /* 4.22.1 BIOS may take up to 1 second to release the device */
|
|---|
| 604 | #define XHCI_LEGSUP_BIOS_TIMEOUT_US 1000000
|
|---|
| 605 | #define XHCI_LEGSUP_POLLING_DELAY_1MS 1000
|
|---|
| 606 |
|
|---|
| 607 | #endif
|
|---|
| 608 | /**
|
|---|
| 609 | * @}
|
|---|
| 610 | */
|
|---|
