source: mainline/uspace/drv/bus/usb/xhci/hw_struct/context.h@ e439f468

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e439f468 was 6fa91e4c, checked in by Michal Staruch <salmelu@…>, 8 years ago

Added macros for device initialization for roothub.
  • Property mode set to 100644
File size: 7.2 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty <aearsis@eideo.cz>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * Context data structures of the xHC.
34 *
35 * Most of them are to be initialized to zero and passed ownership to the HC,
36 * so they are mostly read-only.
37 *
38 * Feel free to write a setter when in need.
39 */
40
41#ifndef XHCI_CONTEXT_H
42#define XHCI_CONTEXT_H
43
44#include <stdint.h>
45#include "common.h"
46
47/**
48 * Endpoint context: section 6.2.3
49 */
50typedef struct xhci_endpoint_ctx {
51 xhci_dword_t data[5];
52 xhci_dword_t reserved[3];
53
54#define XHCI_EP_TYPE_ISOCH_OUT 1
55#define XHCI_EP_TYPE_BULK_OUT 2
56#define XHCI_EP_TYPE_INTERRUPT_OUT 3
57#define XHCI_EP_TYPE_CONTROL 4
58#define XHCI_EP_TYPE_ISOCH_IN 5
59#define XHCI_EP_TYPE_BULK_IN 6
60#define XHCI_EP_TYPE_INTERRUPT_IN 7
61
62#define XHCI_EP_TYPE_SET(ctx, val) \
63 xhci_dword_set_bits(&(ctx).data[1], val, 5, 3)
64#define XHCI_EP_MAX_PACKET_SIZE_SET(ctx, val) \
65 xhci_dword_set_bits(&(ctx).data[1], val, 31, 16)
66#define XHCI_EP_MAX_BURST_SIZE_SET(ctx, val) \
67 xhci_dword_set_bits(&(ctx).data[1], val, 15, 8)
68#define XHCI_EP_TR_DPTR_SET(ctx, val) \
69 xhci_dword_set_bits(&(ctx).data[2], (val >> 4), 63, 4)
70#define XHCI_EP_DCS_SET(ctx, val) \
71 xhci_dword_set_bits(&(ctx).data[2], val, 0, 0)
72#define XHCI_EP_INTERVAL_SET(ctx, val) \
73 xhci_dword_set_bits(&(ctx).data[0], val, 23, 16)
74#define XHCI_EP_MAX_P_STREAMS_SET(ctx, val) \
75 xhci_dword_set_bits(&(ctx).data[0], val, 14, 10)
76#define XHCI_EP_MULT_SET(ctx, val) \
77 xhci_dword_set_bits(&(ctx).data[0], val, 9, 8)
78#define XHCI_EP_ERROR_COUNT_SET(ctx, val) \
79 xhci_dword_set_bits(&(ctx).data[1], val, 2, 1)
80
81#define XHCI_EP_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 2, 0)
82#define XHCI_EP_MULT(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 9, 8)
83#define XHCI_EP_MAX_P_STREAMS(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 14, 10)
84#define XHCI_EP_LSA(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 15, 15)
85#define XHCI_EP_INTERVAL(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 23, 16)
86
87#define XHCI_EP_ERROR_COUNT(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 2, 1)
88#define XHCI_EP_TYPE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 5, 3)
89#define XHCI_EP_HID(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 7, 7)
90#define XHCI_EP_MAX_BURST_SIZE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 15, 8)
91#define XHCI_EP_MAX_PACKET_SIZE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 31, 16)
92
93#define XHCI_EP_DCS(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 0, 0)
94#define XHCI_EP_TR_DPTR(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 63, 4)
95
96} __attribute__((packed)) xhci_ep_ctx_t;
97
98/**
99 * Slot context: section 6.2.2
100 */
101typedef struct xhci_slot_ctx {
102 xhci_dword_t data [4];
103 xhci_dword_t reserved [4];
104
105#define XHCI_SLOT_ROOT_HUB_PORT_SET(ctx, val) \
106 xhci_dword_set_bits(&(ctx).data[1], val, 23, 16)
107#define XHCI_SLOT_CTX_ENTRIES_SET(ctx, val) \
108 xhci_dword_set_bits(&(ctx).data[0], val, 31, 27)
109
110#define XHCI_SLOT_ROUTE_STRING(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 19, 0)
111#define XHCI_SLOT_SPEED(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 23, 20)
112#define XHCI_SLOT_MTT(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 25, 25)
113#define XHCI_SLOT_CTX_ENTRIES(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 31, 27)
114
115#define XHCI_SLOT_MAX_EXIT_LATENCY(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 15, 0)
116#define XHCI_SLOT_ROOT_HUB_PORT(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 23, 16)
117#define XHCI_SLOT_NUM_OF_PORTS(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 31, 24)
118
119#define XHCI_SLOT_TT_HUB_SLOT_ID(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 7, 0)
120#define XHCI_SLOT_TT_PORT_NUM(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 15, 8)
121#define XHCI_SLOT_TT_THINK_TIME(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 17, 16)
122#define XHCI_SLOT_INTERRUPTER(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 31, 22)
123
124#define XHCI_SLOT_DEVICE_ADDRESS(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 7, 0)
125#define XHCI_SLOT_SLOT_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 31, 27)
126
127} __attribute__((packed)) xhci_slot_ctx_t;
128
129/**
130 * Device context: section 6.2.1
131 */
132typedef struct xhci_device_ctx {
133 xhci_slot_ctx_t slot_ctx;
134 xhci_ep_ctx_t endpoint_ctx [31];
135} __attribute__((packed)) xhci_device_ctx_t;
136
137/**
138 * Stream context: section 6.2.4 {
139 */
140typedef struct xhci_stream_ctx {
141 uint64_t data [2];
142#define XHCI_STREAM_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 0, 0)
143#define XHCI_STREAM_SCT(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 3, 1)
144#define XHCI_STREAM_DEQ_PTR(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4)
145#define XHCI_STREAM_EDTLA(ctx) XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0)
146} __attribute__((packed)) xhci_stream_ctx_t;
147
148/**
149 * Input control context: section 6.2.5.1
150 * Note: According to section 6.2.5.1 figure 78,
151 * the context size register value in hccparams1
152 * dictates whether input control context shall have
153 * 32 or 64 bytes, but in any case only dwords 0, 1 and 7
154 * are used, the rest are reserved.
155 */
156typedef struct xhci_input_ctrl_ctx {
157 uint32_t data [16];
158#define XHCI_INPUT_CTRL_CTX_DROP(ctx, idx) \
159 XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx))
160
161#define XHCI_INPUT_CTRL_CTX_DROP_SET(ctx, idx) (ctx).data[0] |= (1 << (idx))
162
163#define XHCI_INPUT_CTRL_CTX_ADD(ctx, idx) \
164 XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx))
165
166#define XHCI_INPUT_CTRL_CTX_ADD_SET(ctx, idx) (ctx).data[1] |= (1 << (idx))
167
168#define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 7, 0)
169#define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 15, 8)
170#define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16)
171} __attribute__((packed)) xhci_input_ctrl_ctx_t;
172
173/**
174 * Input context: section 6.2.5
175 */
176typedef struct xhci_input_ctx {
177 xhci_input_ctrl_ctx_t ctrl_ctx;
178 xhci_slot_ctx_t slot_ctx;
179 xhci_ep_ctx_t endpoint_ctx [31];
180} __attribute__((packed)) xhci_input_ctx_t;
181
182#endif
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