source: mainline/uspace/drv/bus/usb/xhci/hw_struct/context.h@ a1f83a3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a1f83a3 was ef1a3a8, checked in by Petr Manek <petr.manek@…>, 8 years ago

Added memory structure for stream TRB rings. Implemented their initialization. Fixed white space.
  • Property mode set to 100644
File size: 8.6 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty <aearsis@eideo.cz>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * Context data structures of the xHC.
34 *
35 * Most of them are to be initialized to zero and passed ownership to the HC,
36 * so they are mostly read-only.
37 *
38 * Feel free to write a setter when in need.
39 */
40
41#ifndef XHCI_CONTEXT_H
42#define XHCI_CONTEXT_H
43
44#include <stdint.h>
45#include "common.h"
46
47/**
48 * Endpoint context: section 6.2.3
49 */
50typedef struct xhci_endpoint_ctx {
51 xhci_dword_t data[2];
52 xhci_qword_t data2;
53 xhci_dword_t data3;
54 xhci_dword_t reserved[3];
55
56#define XHCI_EP_COUNT 31
57
58#define XHCI_EP_TYPE_ISOCH_OUT 1
59#define XHCI_EP_TYPE_BULK_OUT 2
60#define XHCI_EP_TYPE_INTERRUPT_OUT 3
61#define XHCI_EP_TYPE_CONTROL 4
62#define XHCI_EP_TYPE_ISOCH_IN 5
63#define XHCI_EP_TYPE_BULK_IN 6
64#define XHCI_EP_TYPE_INTERRUPT_IN 7
65
66#define XHCI_EP_TYPE_SET(ctx, val) \
67 xhci_dword_set_bits(&(ctx).data[1], val, 5, 3)
68#define XHCI_EP_MAX_PACKET_SIZE_SET(ctx, val) \
69 xhci_dword_set_bits(&(ctx).data[1], val, 31, 16)
70#define XHCI_EP_MAX_BURST_SIZE_SET(ctx, val) \
71 xhci_dword_set_bits(&(ctx).data[1], val, 15, 8)
72#define XHCI_EP_TR_DPTR_SET(ctx, val) \
73 xhci_qword_set_bits(&(ctx).data2, (val >> 4), 63, 4)
74#define XHCI_EP_DCS_SET(ctx, val) \
75 xhci_qword_set_bits(&(ctx).data2, val, 0, 0)
76#define XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(ctx, val) \
77 xhci_dword_set_bits(&(ctx).data3, val, 31, 16)
78#define XHCI_EP_INTERVAL_SET(ctx, val) \
79 xhci_dword_set_bits(&(ctx).data[0], val, 23, 16)
80#define XHCI_EP_MAX_P_STREAMS_SET(ctx, val) \
81 xhci_dword_set_bits(&(ctx).data[0], val, 14, 10)
82#define XHCI_EP_LSA_SET(ctx, val) \
83 xhci_dword_set_bits(&(ctx).data[0], val, 15, 15)
84#define XHCI_EP_MULT_SET(ctx, val) \
85 xhci_dword_set_bits(&(ctx).data[0], val, 9, 8)
86#define XHCI_EP_ERROR_COUNT_SET(ctx, val) \
87 xhci_dword_set_bits(&(ctx).data[1], val, 2, 1)
88
89#define XHCI_EP_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 2, 0)
90#define XHCI_EP_MULT(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 9, 8)
91#define XHCI_EP_MAX_P_STREAMS(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 14, 10)
92#define XHCI_EP_LSA(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 15, 15)
93#define XHCI_EP_INTERVAL(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 23, 16)
94
95#define XHCI_EP_ERROR_COUNT(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 2, 1)
96#define XHCI_EP_TYPE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 5, 3)
97#define XHCI_EP_HID(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 7, 7)
98#define XHCI_EP_MAX_BURST_SIZE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 15, 8)
99#define XHCI_EP_MAX_PACKET_SIZE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 31, 16)
100
101#define XHCI_EP_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data2, 0, 0)
102#define XHCI_EP_TR_DPTR(ctx) XHCI_QWORD_EXTRACT((ctx).data2, 63, 4)
103
104#define XHCI_EP_MAX_ESIT_PAYLOAD_LO(ctx) XHCI_DWORD_EXTRACT((ctx).data3, 31, 16)
105
106} __attribute__((packed)) xhci_ep_ctx_t;
107
108/**
109 * Slot context: section 6.2.2
110 */
111typedef struct xhci_slot_ctx {
112 xhci_dword_t data [4];
113 xhci_dword_t reserved [4];
114
115#define XHCI_SLOT_ROUTE_STRING_SET(ctx, val) \
116 xhci_dword_set_bits(&(ctx).data[0], (val & 0xFFFFF), 19, 0)
117#define XHCI_SLOT_SPEED_SET(ctx, val) \
118 xhci_dword_set_bits(&(ctx).data[0], (val & 0xF), 23, 20)
119#define XHCI_SLOT_MTT_SET(ctx, val) \
120 xhci_dword_set_bits(&(ctx).data[0], !!val, 25, 25)
121#define XHCI_SLOT_CTX_ENTRIES_SET(ctx, val) \
122 xhci_dword_set_bits(&(ctx).data[0], val, 31, 27)
123
124#define XHCI_SLOT_ROOT_HUB_PORT_SET(ctx, val) \
125 xhci_dword_set_bits(&(ctx).data[1], val, 23, 16)
126
127#define XHCI_SLOT_TT_HUB_SLOT_ID_SET(ctx, val) \
128 xhci_dword_set_bits(&(ctx).data[2], (val & 0xFF), 7, 0)
129#define XHCI_SLOT_TT_HUB_PORT_SET(ctx, val) \
130 xhci_dword_set_bits(&(ctx).data[2], (val & 0xFF), 15, 8)
131
132#define XHCI_SLOT_ROUTE_STRING(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 19, 0)
133#define XHCI_SLOT_SPEED(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 23, 20)
134#define XHCI_SLOT_MTT(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 25, 25)
135#define XHCI_SLOT_CTX_ENTRIES(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 31, 27)
136
137#define XHCI_SLOT_MAX_EXIT_LATENCY(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 15, 0)
138#define XHCI_SLOT_ROOT_HUB_PORT(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 23, 16)
139#define XHCI_SLOT_NUM_OF_PORTS(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 31, 24)
140
141#define XHCI_SLOT_TT_HUB_SLOT_ID(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 7, 0)
142#define XHCI_SLOT_TT_PORT_NUM(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 15, 8)
143#define XHCI_SLOT_TT_THINK_TIME(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 17, 16)
144#define XHCI_SLOT_INTERRUPTER(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 31, 22)
145
146#define XHCI_SLOT_DEVICE_ADDRESS(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 7, 0)
147#define XHCI_SLOT_SLOT_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 31, 27)
148
149} __attribute__((packed)) xhci_slot_ctx_t;
150
151/**
152 * Device context: section 6.2.1
153 */
154typedef struct xhci_device_ctx {
155 xhci_slot_ctx_t slot_ctx;
156 xhci_ep_ctx_t endpoint_ctx[XHCI_EP_COUNT];
157} __attribute__((packed)) xhci_device_ctx_t;
158
159/**
160 * Stream context: section 6.2.4 {
161 */
162typedef struct xhci_stream_ctx {
163 uint64_t data [2];
164#define XHCI_STREAM_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 0, 0)
165#define XHCI_STREAM_SCT(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 3, 1)
166#define XHCI_STREAM_DEQ_PTR(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4)
167#define XHCI_STREAM_EDTLA(ctx) XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0)
168
169#define XHCI_STREAM_SCT_SET(ctx, val) \
170 xhci_qword_set_bits(&(ctx).data[0], val, 3, 1)
171#define XHCI_STREAM_DEQ_PTR_SET(ctx, val) \
172 xhci_qword_set_bits(&(ctx).data[0], (val >> 4), 63, 4)
173} __attribute__((packed)) xhci_stream_ctx_t;
174
175/**
176 * Input control context: section 6.2.5.1
177 * Note: According to section 6.2.5.1 figure 78,
178 * the context size register value in hccparams1
179 * dictates whether input control context shall have
180 * 32 or 64 bytes, but in any case only dwords 0, 1 and 7
181 * are used, the rest are reserved.
182 */
183typedef struct xhci_input_ctrl_ctx {
184 uint32_t data [8];
185#define XHCI_INPUT_CTRL_CTX_DROP(ctx, idx) \
186 XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx))
187
188#define XHCI_INPUT_CTRL_CTX_DROP_SET(ctx, idx) (ctx).data[0] |= (1 << (idx))
189#define XHCI_INPUT_CTRL_CTX_DROP_CLEAR(ctx, idx) (ctx).data[0] &= ~(1 << (idx))
190
191#define XHCI_INPUT_CTRL_CTX_ADD(ctx, idx) \
192 XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx))
193
194#define XHCI_INPUT_CTRL_CTX_ADD_SET(ctx, idx) (ctx).data[1] |= (1 << (idx))
195#define XHCI_INPUT_CTRL_CTX_ADD_CLEAR(ctx, idx) (ctx).data[1] &= ~(1 << (idx))
196
197#define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 7, 0)
198#define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 15, 8)
199#define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16)
200} __attribute__((packed)) xhci_input_ctrl_ctx_t;
201
202/**
203 * Input context: section 6.2.5
204 */
205typedef struct xhci_input_ctx {
206 xhci_input_ctrl_ctx_t ctrl_ctx;
207 xhci_slot_ctx_t slot_ctx;
208 xhci_ep_ctx_t endpoint_ctx[XHCI_EP_COUNT];
209} __attribute__((packed)) xhci_input_ctx_t;
210
211/**
212 * Port bandwidth context: section 6.2.6
213 * The number of ports depends on the amount of ports available to the hub.
214 */
215typedef struct xhci_port_bandwidth_ctx {
216 uint8_t reserved;
217 uint8_t ports [];
218} __attribute__((packed)) xhci_port_bandwidth_ctx_t;
219
220#endif
Note: See TracBrowser for help on using the repository browser.