source: mainline/uspace/drv/bus/usb/xhci/hw_struct/context.h@ 861b5d6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 861b5d6 was 861b5d6, checked in by Jenda <jenda.jzqk73@…>, 8 years ago

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1/*
2 * Copyright (c) 2017 Ondrej Hlavaty <aearsis@eideo.cz>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * Context data structures of the xHC.
34 *
35 * Most of them are to be initialized to zero and passed ownership to the HC,
36 * so they are mostly read-only.
37 *
38 * Feel free to write a setter when in need.
39 */
40
41#ifndef XHCI_CONTEXT_H
42#define XHCI_CONTEXT_H
43
44#include <stdint.h>
45#include "common.h"
46
47/**
48 * Endpoint context: section 6.2.3
49 */
50typedef struct xhci_endpoint_ctx {
51 xhci_dword_t data[2];
52 xhci_qword_t data2;
53 xhci_dword_t data3;
54 xhci_dword_t reserved[3];
55
56#define XHCI_EP_COUNT 31
57
58#define XHCI_EP_TYPE_ISOCH_OUT 1
59#define XHCI_EP_TYPE_BULK_OUT 2
60#define XHCI_EP_TYPE_INTERRUPT_OUT 3
61#define XHCI_EP_TYPE_CONTROL 4
62#define XHCI_EP_TYPE_ISOCH_IN 5
63#define XHCI_EP_TYPE_BULK_IN 6
64#define XHCI_EP_TYPE_INTERRUPT_IN 7
65
66#define XHCI_EP_TYPE_SET(ctx, val) \
67 xhci_dword_set_bits(&(ctx).data[1], val, 5, 3)
68#define XHCI_EP_MAX_PACKET_SIZE_SET(ctx, val) \
69 xhci_dword_set_bits(&(ctx).data[1], val, 31, 16)
70#define XHCI_EP_MAX_BURST_SIZE_SET(ctx, val) \
71 xhci_dword_set_bits(&(ctx).data[1], val, 15, 8)
72#define XHCI_EP_TR_DPTR_SET(ctx, val) \
73 xhci_qword_set_bits(&(ctx).data2, (val >> 4), 63, 4)
74#define XHCI_EP_DCS_SET(ctx, val) \
75 xhci_qword_set_bits(&(ctx).data2, val, 0, 0)
76#define XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(ctx, val) \
77 xhci_dword_set_bits(&(ctx).data3, val, 31, 16)
78#define XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(ctx, val) \
79 xhci_dword_set_bits(&(ctx).data[0], val, 31, 24)
80#define XHCI_EP_INTERVAL_SET(ctx, val) \
81 xhci_dword_set_bits(&(ctx).data[0], val, 23, 16)
82#define XHCI_EP_MAX_P_STREAMS_SET(ctx, val) \
83 xhci_dword_set_bits(&(ctx).data[0], val, 14, 10)
84#define XHCI_EP_LSA_SET(ctx, val) \
85 xhci_dword_set_bits(&(ctx).data[0], val, 15, 15)
86#define XHCI_EP_MULT_SET(ctx, val) \
87 xhci_dword_set_bits(&(ctx).data[0], val, 9, 8)
88#define XHCI_EP_ERROR_COUNT_SET(ctx, val) \
89 xhci_dword_set_bits(&(ctx).data[1], val, 2, 1)
90
91#define XHCI_EP_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 2, 0)
92#define XHCI_EP_MULT(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 9, 8)
93#define XHCI_EP_MAX_P_STREAMS(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 14, 10)
94#define XHCI_EP_LSA(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 15, 15)
95#define XHCI_EP_INTERVAL(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 23, 16)
96
97#define XHCI_EP_ERROR_COUNT(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 2, 1)
98#define XHCI_EP_TYPE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 5, 3)
99#define XHCI_EP_HID(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 7, 7)
100#define XHCI_EP_MAX_BURST_SIZE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 15, 8)
101#define XHCI_EP_MAX_PACKET_SIZE(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 31, 16)
102
103#define XHCI_EP_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data2, 0, 0)
104#define XHCI_EP_TR_DPTR(ctx) XHCI_QWORD_EXTRACT((ctx).data2, 63, 4)
105
106#define XHCI_EP_MAX_ESIT_PAYLOAD_LO(ctx) XHCI_DWORD_EXTRACT((ctx).data3, 31, 16)
107#define XHCI_EP_MAX_ESIT_PAYLOAD_HI(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 31, 24)
108
109} __attribute__((packed)) xhci_ep_ctx_t;
110
111enum {
112 EP_STATE_DISABLED = 0,
113 EP_STATE_RUNNING = 1,
114 EP_STATE_HALTED = 2,
115 EP_STATE_STOPPED = 3,
116 EP_STATE_ERROR = 4,
117};
118
119/**
120 * Slot context: section 6.2.2
121 */
122typedef struct xhci_slot_ctx {
123 xhci_dword_t data [4];
124 xhci_dword_t reserved [4];
125
126#define XHCI_SLOT_ROUTE_STRING_SET(ctx, val) \
127 xhci_dword_set_bits(&(ctx).data[0], (val & 0xFFFFF), 19, 0)
128#define XHCI_SLOT_SPEED_SET(ctx, val) \
129 xhci_dword_set_bits(&(ctx).data[0], (val & 0xF), 23, 20)
130#define XHCI_SLOT_MTT_SET(ctx, val) \
131 xhci_dword_set_bits(&(ctx).data[0], !!val, 25, 25)
132#define XHCI_SLOT_CTX_ENTRIES_SET(ctx, val) \
133 xhci_dword_set_bits(&(ctx).data[0], val, 31, 27)
134
135#define XHCI_SLOT_ROOT_HUB_PORT_SET(ctx, val) \
136 xhci_dword_set_bits(&(ctx).data[1], val, 23, 16)
137
138#define XHCI_SLOT_TT_HUB_SLOT_ID_SET(ctx, val) \
139 xhci_dword_set_bits(&(ctx).data[2], (val & 0xFF), 7, 0)
140#define XHCI_SLOT_TT_HUB_PORT_SET(ctx, val) \
141 xhci_dword_set_bits(&(ctx).data[2], (val & 0xFF), 15, 8)
142
143#define XHCI_SLOT_ROUTE_STRING(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 19, 0)
144#define XHCI_SLOT_SPEED(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 23, 20)
145#define XHCI_SLOT_MTT(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 25, 25)
146#define XHCI_SLOT_CTX_ENTRIES(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 31, 27)
147
148#define XHCI_SLOT_MAX_EXIT_LATENCY(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 15, 0)
149#define XHCI_SLOT_ROOT_HUB_PORT(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 23, 16)
150#define XHCI_SLOT_NUM_OF_PORTS(ctx) XHCI_DWORD_EXTRACT((ctx).data[1], 31, 24)
151
152#define XHCI_SLOT_TT_HUB_SLOT_ID(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 7, 0)
153#define XHCI_SLOT_TT_PORT_NUM(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 15, 8)
154#define XHCI_SLOT_TT_THINK_TIME(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 17, 16)
155#define XHCI_SLOT_INTERRUPTER(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 31, 22)
156
157#define XHCI_SLOT_DEVICE_ADDRESS(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 7, 0)
158#define XHCI_SLOT_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 31, 27)
159
160} __attribute__((packed)) xhci_slot_ctx_t;
161
162enum {
163 SLOT_STATE_DISABLED = 0,
164 SLOT_STATE_DEFAULT = 1,
165 SLOT_STATE_ADDRESS = 2,
166 SLOT_STATE_CONFIGURED = 3,
167};
168
169/**
170 * Device context: section 6.2.1
171 */
172typedef struct xhci_device_ctx {
173 xhci_slot_ctx_t slot_ctx;
174 xhci_ep_ctx_t endpoint_ctx[XHCI_EP_COUNT];
175} __attribute__((packed)) xhci_device_ctx_t;
176
177/**
178 * Stream context: section 6.2.4 {
179 */
180typedef struct xhci_stream_ctx {
181 uint64_t data [2];
182#define XHCI_STREAM_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 0, 0)
183#define XHCI_STREAM_SCT(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 3, 1)
184#define XHCI_STREAM_DEQ_PTR(ctx) (XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4) << 4)
185#define XHCI_STREAM_EDTLA(ctx) XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0)
186
187#define XHCI_STREAM_SCT_SET(ctx, val) \
188 xhci_qword_set_bits(&(ctx).data[0], val, 3, 1)
189#define XHCI_STREAM_DEQ_PTR_SET(ctx, val) \
190 xhci_qword_set_bits(&(ctx).data[0], (val >> 4), 63, 4)
191} __attribute__((packed)) xhci_stream_ctx_t;
192
193/**
194 * Input control context: section 6.2.5.1
195 * Note: According to section 6.2.5.1 figure 78,
196 * the context size register value in hccparams1
197 * dictates whether input control context shall have
198 * 32 or 64 bytes, but in any case only dwords 0, 1 and 7
199 * are used, the rest are reserved.
200 */
201typedef struct xhci_input_ctrl_ctx {
202 uint32_t data [8];
203#define XHCI_INPUT_CTRL_CTX_DROP(ctx, idx) \
204 XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx))
205
206#define XHCI_INPUT_CTRL_CTX_DROP_SET(ctx, idx) (ctx).data[0] |= (1 << (idx))
207#define XHCI_INPUT_CTRL_CTX_DROP_CLEAR(ctx, idx) (ctx).data[0] &= ~(1 << (idx))
208
209#define XHCI_INPUT_CTRL_CTX_ADD(ctx, idx) \
210 XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx))
211
212#define XHCI_INPUT_CTRL_CTX_ADD_SET(ctx, idx) (ctx).data[1] |= (1 << (idx))
213#define XHCI_INPUT_CTRL_CTX_ADD_CLEAR(ctx, idx) (ctx).data[1] &= ~(1 << (idx))
214
215#define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 7, 0)
216#define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 15, 8)
217#define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16)
218} __attribute__((packed)) xhci_input_ctrl_ctx_t;
219
220/**
221 * Input context: section 6.2.5
222 */
223typedef struct xhci_input_ctx {
224 xhci_input_ctrl_ctx_t ctrl_ctx;
225 xhci_slot_ctx_t slot_ctx;
226 xhci_ep_ctx_t endpoint_ctx[XHCI_EP_COUNT];
227} __attribute__((packed)) xhci_input_ctx_t;
228
229/**
230 * Port bandwidth context: section 6.2.6
231 * The number of ports depends on the amount of ports available to the hub.
232 */
233typedef struct xhci_port_bandwidth_ctx {
234 uint8_t reserved;
235 uint8_t ports [];
236} __attribute__((packed)) xhci_port_bandwidth_ctx_t;
237
238#endif
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