source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 56db65d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 56db65d was b724494, checked in by Petr Manek <petr.manek@…>, 8 years ago

Moved some code from RH to HC. Simplified device address process. Issuing deconfigure device command.
  • Property mode set to 100644
File size: 21.1 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/endpoint.h>
40#include <usb/host/utils/malloc32.h>
41#include "debug.h"
42#include "hc.h"
43#include "rh.h"
44#include "hw_struct/trb.h"
45#include "commands.h"
46#include "transfers.h"
47#include "trb_ring.h"
48
49/**
50 * Default USB Speed ID mapping: Table 157
51 */
52#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53#define PORT_SPEED(mjr, psie, psim) { \
54 .name = "USB ", \
55 .major = mjr, \
56 .minor = 0, \
57 .rx_bps = PSI_TO_BPS(psie, psim), \
58 .tx_bps = PSI_TO_BPS(psie, psim) \
59}
60static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 2, 12);
61static const xhci_port_speed_t ps_default_low = PORT_SPEED(2, 1, 1500);
62static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 2, 480);
63static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 3, 5);
64
65/**
66 * Walk the list of extended capabilities.
67 */
68static int hc_parse_ec(xhci_hc_t *hc)
69{
70 unsigned psic, major, minor;
71 xhci_sp_name_t name;
72
73 xhci_port_speed_t *speeds = hc->rh.speeds;
74
75 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
76 xhci_dump_extcap(ec);
77 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
78 case XHCI_EC_USB_LEGACY:
79 assert(hc->legsup == NULL);
80 hc->legsup = (xhci_legsup_t *) ec;
81 break;
82 case XHCI_EC_SUPPORTED_PROTOCOL:
83 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
84 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
85 minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
86 name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
87
88 if (name.packed != xhci_name_usb.packed) {
89 /**
90 * The detection of such protocol would work,
91 * but the rest of the implementation is made
92 * for the USB protocol only.
93 */
94 usb_log_error("Unknown protocol %.4s.", name.str);
95 return ENOTSUP;
96 }
97
98 // "Implied" speed
99 if (psic == 0) {
100 assert(minor == 0);
101
102 if (major == 2) {
103 speeds[1] = ps_default_full;
104 speeds[2] = ps_default_low;
105 speeds[3] = ps_default_high;
106 } else if (major == 3) {
107 speeds[4] = ps_default_super;
108 } else {
109 return EINVAL;
110 }
111
112 usb_log_debug2("Implied speed of USB %u.0 set up.", major);
113 } else {
114 for (unsigned i = 0; i < psic; i++) {
115 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
116 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
117 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
118 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
119 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
120
121 speeds[psiv].major = major;
122 speeds[psiv].minor = minor;
123 str_ncpy(speeds[psiv].name, 4, name.str, 4);
124
125 uint64_t bps = PSI_TO_BPS(psie, psim);
126
127 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
128 speeds[psiv].rx_bps = bps;
129 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
130 speeds[psiv].tx_bps = bps;
131 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, speeds[psiv].tx_bps);
132 }
133 }
134 }
135 }
136 }
137 return EOK;
138}
139
140int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
141{
142 int err;
143
144 if (hw_res->mem_ranges.count != 1) {
145 usb_log_error("Unexpected MMIO area, bailing out.");
146 return EINVAL;
147 }
148
149 hc->mmio_range = hw_res->mem_ranges.ranges[0];
150
151 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
152 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
153
154 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
155 return EOVERFLOW;
156
157 void *base;
158 if ((err = pio_enable_range(&hc->mmio_range, &base)))
159 return err;
160
161 hc->reg_base = base;
162 hc->cap_regs = (xhci_cap_regs_t *) base;
163 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
164 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
165 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
166
167 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
168 if (xec_offset > 0)
169 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
170
171 usb_log_debug2("Initialized MMIO reg areas:");
172 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
173 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
174 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
175 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
176
177 xhci_dump_cap_regs(hc->cap_regs);
178
179 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
180 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
181
182 if ((err = hc_parse_ec(hc))) {
183 pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
184 return err;
185 }
186
187 return EOK;
188}
189
190int hc_init_memory(xhci_hc_t *hc, ddf_dev_t *device)
191{
192 int err;
193
194 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(uint64_t));
195 if (!hc->dcbaa)
196 return ENOMEM;
197
198 if ((err = xhci_trb_ring_init(&hc->command_ring)))
199 goto err_dcbaa;
200
201 if ((err = xhci_event_ring_init(&hc->event_ring)))
202 goto err_cmd_ring;
203
204 if ((err = xhci_scratchpad_alloc(hc)))
205 goto err_event_ring;
206
207 if ((err = xhci_init_commands(hc)))
208 goto err_scratch;
209
210 if ((err = xhci_rh_init(&hc->rh, hc, device)))
211 goto err_cmd;
212
213 if ((err = xhci_bus_init(&hc->bus, hc)))
214 goto err_rh;
215
216
217 return EOK;
218
219err_rh:
220 xhci_rh_fini(&hc->rh);
221err_cmd:
222 xhci_fini_commands(hc);
223err_scratch:
224 xhci_scratchpad_free(hc);
225err_event_ring:
226 xhci_event_ring_fini(&hc->event_ring);
227err_cmd_ring:
228 xhci_trb_ring_fini(&hc->command_ring);
229err_dcbaa:
230 free32(hc->dcbaa);
231 return err;
232}
233
234/*
235 * Pseudocode:
236 * ip = read(intr[0].iman)
237 * if (ip) {
238 * status = read(usbsts)
239 * assert status
240 * assert ip
241 * accept (passing status)
242 * }
243 * decline
244 */
245static const irq_cmd_t irq_commands[] = {
246 {
247 .cmd = CMD_PIO_READ_32,
248 .dstarg = 3,
249 .addr = NULL /* intr[0].iman */
250 },
251 {
252 .cmd = CMD_AND,
253 .srcarg = 3,
254 .dstarg = 4,
255 .value = 0 /* host2xhci(32, 1) */
256 },
257 {
258 .cmd = CMD_PREDICATE,
259 .srcarg = 4,
260 .value = 5
261 },
262 {
263 .cmd = CMD_PIO_READ_32,
264 .dstarg = 1,
265 .addr = NULL /* usbsts */
266 },
267 {
268 .cmd = CMD_AND,
269 .srcarg = 1,
270 .dstarg = 2,
271 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
272 },
273 {
274 .cmd = CMD_PIO_WRITE_A_32,
275 .srcarg = 2,
276 .addr = NULL /* usbsts */
277 },
278 {
279 .cmd = CMD_PIO_WRITE_A_32,
280 .srcarg = 3,
281 .addr = NULL /* intr[0].iman */
282 },
283 {
284 .cmd = CMD_ACCEPT
285 },
286 {
287 .cmd = CMD_DECLINE
288 }
289};
290
291
292/**
293 * Generates code to accept interrupts. The xHCI is designed primarily for
294 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
295 * (except 0) are disabled.
296 */
297int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
298{
299 assert(code);
300 assert(hw_res);
301
302 if (hw_res->irqs.count != 1) {
303 usb_log_info("Unexpected HW resources to enable interrupts.");
304 return EINVAL;
305 }
306
307 code->ranges = malloc(sizeof(irq_pio_range_t));
308 if (code->ranges == NULL)
309 return ENOMEM;
310
311 code->cmds = malloc(sizeof(irq_commands));
312 if (code->cmds == NULL) {
313 free(code->ranges);
314 return ENOMEM;
315 }
316
317 code->rangecount = 1;
318 code->ranges[0] = (irq_pio_range_t) {
319 .base = RNGABS(hc->mmio_range),
320 .size = RNGSZ(hc->mmio_range),
321 };
322
323 code->cmdcount = ARRAY_SIZE(irq_commands);
324 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
325
326 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
327 void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
328 code->cmds[0].addr = intr0_iman;
329 code->cmds[1].value = host2xhci(32, 1);
330 code->cmds[3].addr = usbsts;
331 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
332 code->cmds[5].addr = usbsts;
333 code->cmds[6].addr = intr0_iman;
334
335 return hw_res->irqs.irqs[0];
336}
337
338int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
339{
340 /* No legacy support capability, the controller is solely for us */
341 if (!hc->legsup)
342 return EOK;
343
344 /* Section 4.22.1 */
345 /* TODO: Test this with USB3-aware BIOS */
346 usb_log_debug2("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
347 XHCI_REG_WR(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
348 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
349 usb_log_debug2("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
350 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
351 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
352 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
353 assert(XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1);
354 return EOK;
355 }
356 async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
357 }
358 usb_log_error("BIOS did not release XHCI legacy hold!\n");
359
360 return ENOTSUP;
361}
362
363static int hc_reset(xhci_hc_t *hc)
364{
365 /* Stop the HC: set R/S to 0 */
366 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
367
368 /* Wait 16 ms until the HC is halted */
369 async_usleep(16000);
370 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
371
372 /* Reset */
373 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
374
375 /* Wait until the reset is complete */
376 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
377 async_usleep(1000);
378
379 return EOK;
380}
381
382/**
383 * Initialize the HC: section 4.2
384 */
385int hc_start(xhci_hc_t *hc, bool irq)
386{
387 int err;
388
389 if ((err = hc_reset(hc)))
390 return err;
391
392 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
393 async_usleep(1000);
394
395 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
396 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
397 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
398 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
399
400 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
401 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
402 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
403
404 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
405 uint64_t erdp = hc->event_ring.dequeue_ptr;
406 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
407 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
408 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
409 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
410 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
411 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
412
413 if (irq) {
414 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
415 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
416 }
417
418 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
419
420 /* The reset changed status of all ports, and SW originated reason does
421 * not cause an interrupt.
422 */
423 xhci_rh_handle_port_change(&hc->rh);
424
425 return EOK;
426}
427
428/**
429 * Used only when polling. Shall supplement the irq_commands.
430 */
431int hc_status(xhci_hc_t *hc, uint32_t *status)
432{
433 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
434 if (ip) {
435 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
436 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
437 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
438
439 /* interrupt handler expects status from irq_commands, which is
440 * in xhci order. */
441 *status = host2xhci(32, *status);
442 }
443
444 usb_log_debug2("HC(%p): Polled status: %x", hc, *status);
445 return EOK;
446}
447
448int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
449{
450 assert(batch);
451
452 usb_log_debug2("Endpoint(%d:%d) started %s transfer of size %lu.",
453 batch->ep->target.address, batch->ep->target.endpoint,
454 usb_str_transfer_type(batch->ep->transfer_type),
455 batch->buffer_size);
456
457 if (!batch->ep->target.address) {
458 usb_log_error("Attempted to schedule transfer to address 0.");
459 return EINVAL;
460 }
461
462 return xhci_transfer_schedule(hc, batch);
463}
464
465typedef int (*event_handler) (xhci_hc_t *, xhci_trb_t *trb);
466
467static event_handler event_handlers [] = {
468 [XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
469 [XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT] = &xhci_rh_handle_port_status_change_event,
470 [XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
471};
472
473static int hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb, xhci_interrupter_regs_t *intr)
474{
475 unsigned type = TRB_TYPE(*trb);
476 if (type >= ARRAY_SIZE(event_handlers) || !event_handlers[type])
477 return ENOTSUP;
478
479 return event_handlers[type](hc, trb);
480}
481
482static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
483{
484 int err;
485 ssize_t size = 16;
486 xhci_trb_t *queue = malloc(sizeof(xhci_trb_t) * size);
487 if (!queue) {
488 usb_log_error("Not enough memory to run the event ring.");
489 return;
490 }
491
492 xhci_trb_t *head = queue;
493
494 while ((err = xhci_event_ring_dequeue(event_ring, head)) != ENOENT) {
495 if (err != EOK) {
496 usb_log_warning("Error while accessing event ring: %s", str_error(err));
497 break;
498 }
499
500 usb_log_debug2("Dequeued trb from event ring: %s", xhci_trb_str_type(TRB_TYPE(*head)));
501 head++;
502
503 /* Expand the array if needed. */
504 if (head - queue >= size) {
505 size *= 2;
506 xhci_trb_t *new_queue = realloc(queue, size);
507 if (new_queue == NULL)
508 break; /* Will process only those TRBs we have memory for. */
509
510 head = new_queue + (head - queue);
511 }
512 }
513
514 /* Update the ERDP to make room in the ring. */
515 usb_log_debug2("Copying from ring finished, updating ERDP.");
516 uint64_t erdp = hc->event_ring.dequeue_ptr;
517 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
518 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
519 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
520
521 /* Handle all of the collected events if possible. */
522 if (head == queue)
523 usb_log_warning("No events to be handled!");
524
525 for (xhci_trb_t *tail = queue; tail != head; tail++) {
526 if ((err = hc_handle_event(hc, tail, intr)) != EOK) {
527 usb_log_error("Failed to handle event: %s", str_error(err));
528 }
529 }
530
531 free(queue);
532 usb_log_debug2("Event ring run finished.");
533}
534
535void hc_interrupt(xhci_hc_t *hc, uint32_t status)
536{
537 status = xhci2host(32, status);
538
539 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
540 usb_log_debug2("Root hub interrupt.");
541 xhci_rh_handle_port_change(&hc->rh);
542 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
543 }
544
545 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
546 usb_log_error("Host controller error occured. Bad things gonna happen...");
547 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
548 }
549
550 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
551 usb_log_debug2("Event interrupt, running the event ring.");
552 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
553 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
554 }
555
556 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
557 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
558 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
559 }
560
561 if (status) {
562 usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
563 }
564}
565
566static void hc_dcbaa_fini(xhci_hc_t *hc)
567{
568 xhci_scratchpad_free(hc);
569 free32(hc->dcbaa);
570}
571
572void hc_fini(xhci_hc_t *hc)
573{
574 xhci_bus_fini(&hc->bus);
575 xhci_trb_ring_fini(&hc->command_ring);
576 xhci_event_ring_fini(&hc->event_ring);
577 hc_dcbaa_fini(hc);
578 xhci_fini_commands(hc);
579 xhci_rh_fini(&hc->rh);
580 pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
581 usb_log_info("HC(%p): Finalized.", hc);
582}
583
584int hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
585{
586 assert(hc);
587 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
588 pio_write_32(&hc->db_arry[doorbell], v);
589 usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
590 return EOK;
591}
592
593int hc_enable_slot(xhci_hc_t *hc, uint32_t *slot_id)
594{
595 assert(hc);
596
597 int err;
598 xhci_cmd_t cmd;
599 xhci_cmd_init(&cmd);
600
601 if ((err = xhci_send_enable_slot_command(hc, &cmd)) != EOK)
602 return err;
603
604 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT)) != EOK)
605 return err;
606
607 if (slot_id)
608 *slot_id = cmd.slot_id;
609
610 xhci_cmd_fini(&cmd);
611 return EOK;
612}
613
614int hc_disable_slot(xhci_hc_t *hc, uint32_t slot_id)
615{
616 assert(hc);
617
618 int err;
619 xhci_cmd_t cmd;
620 xhci_cmd_init(&cmd);
621
622 cmd.slot_id = slot_id;
623
624 if ((err = xhci_send_disable_slot_command(hc, &cmd)) != EOK)
625 return err;
626
627 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT)) != EOK)
628 return err;
629
630 xhci_cmd_fini(&cmd);
631 return EOK;
632}
633
634int hc_address_device(xhci_hc_t *hc, uint32_t slot_id, xhci_input_ctx_t *ictx)
635{
636 assert(hc);
637
638 int err;
639 xhci_cmd_t cmd;
640 xhci_cmd_init(&cmd);
641
642 cmd.slot_id = slot_id;
643
644 if ((err = xhci_send_address_device_command(hc, &cmd, ictx)) != EOK)
645 return err;
646
647 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT)) != EOK)
648 return err;
649
650 xhci_cmd_fini(&cmd);
651 return EOK;
652}
653
654static int create_valid_input_ctx(xhci_input_ctx_t **out_ictx)
655{
656 xhci_input_ctx_t *ictx = malloc32(sizeof(xhci_input_ctx_t));
657 if (!ictx) {
658 return ENOMEM;
659 }
660
661 memset(ictx, 0, sizeof(xhci_input_ctx_t));
662
663 // Quoting sec. 4.6.6: A1, D0, D1 are down, A0 is up.
664 XHCI_INPUT_CTRL_CTX_ADD_CLEAR(ictx->ctrl_ctx, 1);
665 XHCI_INPUT_CTRL_CTX_DROP_CLEAR(ictx->ctrl_ctx, 0);
666 XHCI_INPUT_CTRL_CTX_DROP_CLEAR(ictx->ctrl_ctx, 1);
667 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, 0);
668
669 if (out_ictx) {
670 *out_ictx = ictx;
671 }
672
673 return EOK;
674}
675
676int hc_address_rh_device(xhci_hc_t *hc, uint32_t slot_id, uint8_t port, xhci_ep_ctx_t *ep_ctx)
677{
678 int err;
679
680 /* Issue configure endpoint command (sec 4.3.5). */
681 xhci_input_ctx_t *ictx;
682 if ((err = create_valid_input_ctx(&ictx))) {
683 goto err;
684 }
685
686 /* Initialize slot_ctx according to section 4.3.3 point 3. */
687 XHCI_SLOT_ROOT_HUB_PORT_SET(ictx->slot_ctx, port);
688 XHCI_SLOT_CTX_ENTRIES_SET(ictx->slot_ctx, 1);
689
690 /* Attaching to root hub port, root string equals to 0. */
691 XHCI_SLOT_ROUTE_STRING_SET(ictx->slot_ctx, 0);
692
693 /* Copy endpoint 0 context and set A1 flag. */
694 memcpy(&ictx->endpoint_ctx[0], ep_ctx, sizeof(xhci_ep_ctx_t));
695 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, 1);
696
697 if ((err = hc_address_device(hc, slot_id, ictx))) {
698 goto err_cmd;
699 }
700
701 free32(ictx);
702 return EOK;
703
704err_cmd:
705 free32(ictx);
706err:
707 return err;
708}
709
710int hc_configure_device(xhci_hc_t *hc, uint32_t slot_id)
711{
712 int err;
713
714 /* Issue configure endpoint command (sec 4.3.5). */
715 xhci_input_ctx_t *ictx;
716 if ((err = create_valid_input_ctx(&ictx))) {
717 goto err;
718 }
719
720 // TODO: Set slot context and other flags. (probably forgot a lot of 'em)
721
722 xhci_cmd_t cmd;
723 xhci_cmd_init(&cmd);
724
725 cmd.slot_id = slot_id;
726
727 if ((err = xhci_send_configure_endpoint_command(hc, &cmd, ictx))) {
728 goto err_cmd;
729 }
730
731 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT))) {
732 goto err_cmd;
733 }
734
735 xhci_cmd_fini(&cmd);
736
737 free32(ictx);
738 return EOK;
739
740err_cmd:
741 free32(ictx);
742err:
743 return err;
744}
745
746int hc_deconfigure_device(xhci_hc_t *hc, uint32_t slot_id)
747{
748 int err;
749
750 /* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
751 xhci_cmd_t cmd;
752 xhci_cmd_init(&cmd);
753
754 cmd.slot_id = slot_id;
755 cmd.deconfigure = true;
756
757 if ((err = xhci_send_configure_endpoint_command(hc, &cmd, NULL))) {
758 return err;
759 }
760
761 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT))) {
762 return err;
763 }
764
765 xhci_cmd_fini(&cmd);
766
767 return EOK;
768}
769
770int hc_add_endpoint(xhci_hc_t *hc, uint32_t slot_id, uint8_t ep_idx, xhci_ep_ctx_t *ep_ctx)
771{
772 int err;
773
774 /* Issue configure endpoint command (sec 4.3.5). */
775 xhci_input_ctx_t *ictx;
776 if ((err = create_valid_input_ctx(&ictx))) {
777 goto err;
778 }
779
780 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, ep_idx + 1); /* Preceded by slot ctx */
781 memcpy(&ictx->endpoint_ctx[ep_idx], ep_ctx, sizeof(xhci_ep_ctx_t));
782
783 // TODO: Set slot context and other flags. (probably forgot a lot of 'em)
784
785 xhci_cmd_t cmd;
786 xhci_cmd_init(&cmd);
787
788 cmd.slot_id = slot_id;
789
790 if ((err = xhci_send_configure_endpoint_command(hc, &cmd, ictx))) {
791 goto err_cmd;
792 }
793
794 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT))) {
795 goto err_cmd;
796 }
797
798 xhci_cmd_fini(&cmd);
799
800 free32(ictx);
801 return EOK;
802
803err_cmd:
804 free32(ictx);
805err:
806 return err;
807}
808
809int hc_drop_endpoint(xhci_hc_t *hc, uint32_t slot_id, uint8_t ep_idx)
810{
811 int err;
812
813 /* Issue configure endpoint command (sec 4.3.5). */
814 xhci_input_ctx_t *ictx;
815 if ((err = create_valid_input_ctx(&ictx))) {
816 goto err;
817 }
818
819 XHCI_INPUT_CTRL_CTX_DROP_SET(ictx->ctrl_ctx, ep_idx + 1); /* Preceded by slot ctx */
820
821 // TODO: Set slot context and other flags. (probably forgot a lot of 'em)
822
823 xhci_cmd_t cmd;
824 xhci_cmd_init(&cmd);
825
826 cmd.slot_id = slot_id;
827
828 if ((err = xhci_send_configure_endpoint_command(hc, &cmd, ictx))) {
829 goto err_cmd;
830 }
831
832 if ((err = xhci_cmd_wait(&cmd, XHCI_DEFAULT_TIMEOUT))) {
833 goto err_cmd;
834 }
835
836 xhci_cmd_fini(&cmd);
837
838 free32(ictx);
839 return EOK;
840
841err_cmd:
842 free32(ictx);
843err:
844 return err;
845}
846
847/**
848 * @}
849 */
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