source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 078e0e63

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 078e0e63 was 078e0e63, checked in by Jaroslav Jindrak <dzejrou@…>, 8 years ago

Removed unnecessary calls to malloc32 and free32.
  • Property mode set to 100644
File size: 16.9 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45
46/**
47 * Default USB Speed ID mapping: Table 157
48 */
49#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
50#define PORT_SPEED(mjr, psie, psim) { \
51 .name = "USB ", \
52 .major = mjr, \
53 .minor = 0, \
54 .rx_bps = PSI_TO_BPS(psie, psim), \
55 .tx_bps = PSI_TO_BPS(psie, psim) \
56}
57static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 2, 12);
58static const xhci_port_speed_t ps_default_low = PORT_SPEED(2, 1, 1500);
59static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 2, 480);
60static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 3, 5);
61
62/**
63 * Walk the list of extended capabilities.
64 */
65static int hc_parse_ec(xhci_hc_t *hc)
66{
67 unsigned psic, major, minor;
68 xhci_sp_name_t name;
69
70 xhci_port_speed_t *speeds = hc->rh.speeds;
71
72 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
73 xhci_dump_extcap(ec);
74 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
75 case XHCI_EC_USB_LEGACY:
76 assert(hc->legsup == NULL);
77 hc->legsup = (xhci_legsup_t *) ec;
78 break;
79 case XHCI_EC_SUPPORTED_PROTOCOL:
80 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
81 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
82 minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
83 name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
84
85 if (name.packed != xhci_name_usb.packed) {
86 /**
87 * The detection of such protocol would work,
88 * but the rest of the implementation is made
89 * for the USB protocol only.
90 */
91 usb_log_error("Unknown protocol %.4s.", name.str);
92 return ENOTSUP;
93 }
94
95 // "Implied" speed
96 if (psic == 0) {
97 assert(minor == 0);
98
99 if (major == 2) {
100 speeds[1] = ps_default_full;
101 speeds[2] = ps_default_low;
102 speeds[3] = ps_default_high;
103 } else if (major == 3) {
104 speeds[4] = ps_default_super;
105 } else {
106 return EINVAL;
107 }
108
109 usb_log_debug2("Implied speed of USB %u.0 set up.", major);
110 } else {
111 for (unsigned i = 0; i < psic; i++) {
112 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
113 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
114 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
115 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
116 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
117
118 speeds[psiv].major = major;
119 speeds[psiv].minor = minor;
120 str_ncpy(speeds[psiv].name, 4, name.str, 4);
121
122 uint64_t bps = PSI_TO_BPS(psie, psim);
123
124 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
125 speeds[psiv].rx_bps = bps;
126 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
127 speeds[psiv].tx_bps = bps;
128 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, speeds[psiv].tx_bps);
129 }
130 }
131 }
132 }
133 }
134 return EOK;
135}
136
137int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
138{
139 int err;
140
141 if (hw_res->mem_ranges.count != 1) {
142 usb_log_error("Unexpected MMIO area, bailing out.");
143 return EINVAL;
144 }
145
146 hc->mmio_range = hw_res->mem_ranges.ranges[0];
147
148 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
149 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
150
151 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
152 return EOVERFLOW;
153
154 void *base;
155 if ((err = pio_enable_range(&hc->mmio_range, &base)))
156 return err;
157
158 hc->base = base;
159 hc->cap_regs = (xhci_cap_regs_t *) base;
160 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
161 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
162 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
163
164 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
165 if (xec_offset > 0)
166 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
167
168 usb_log_debug2("Initialized MMIO reg areas:");
169 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
170 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
171 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
172 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
173
174 xhci_dump_cap_regs(hc->cap_regs);
175
176 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
177 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
178
179 if ((err = hc_parse_ec(hc))) {
180 pio_disable(hc->base, RNGSZ(hc->mmio_range));
181 return err;
182 }
183
184 return EOK;
185}
186
187int hc_init_memory(xhci_hc_t *hc)
188{
189 int err;
190
191 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(uint64_t));
192 if (!hc->dcbaa)
193 return ENOMEM;
194
195 hc->dcbaa_virt = malloc((1 + hc->max_slots) * sizeof(xhci_virt_device_ctx_t));
196 if (!hc->dcbaa_virt) {
197 err = ENOMEM;
198 goto err_dcbaa;
199 }
200
201 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
202 goto err_dcbaa_virt;
203
204 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
205 goto err_cmd_ring;
206
207 if ((err = xhci_scratchpad_alloc(hc)))
208 goto err_event_ring;
209
210 if ((err = xhci_init_commands(hc)))
211 goto err_scratch;
212
213 if ((err = xhci_rh_init(&hc->rh, hc)))
214 goto err_cmd;
215
216 return EOK;
217
218err_cmd:
219 xhci_fini_commands(hc);
220err_scratch:
221 xhci_scratchpad_free(hc);
222err_event_ring:
223 xhci_event_ring_fini(&hc->event_ring);
224err_cmd_ring:
225 xhci_trb_ring_fini(&hc->command_ring);
226err_dcbaa_virt:
227 free32(hc->dcbaa_virt);
228err_dcbaa:
229 free32(hc->dcbaa);
230 return err;
231}
232
233/*
234 * Pseudocode:
235 * ip = read(intr[0].iman)
236 * if (ip) {
237 * status = read(usbsts)
238 * assert status
239 * assert ip
240 * accept (passing status)
241 * }
242 * decline
243 */
244static const irq_cmd_t irq_commands[] = {
245 {
246 .cmd = CMD_PIO_READ_32,
247 .dstarg = 3,
248 .addr = NULL /* intr[0].iman */
249 },
250 {
251 .cmd = CMD_AND,
252 .srcarg = 3,
253 .dstarg = 4,
254 .value = 0 /* host2xhci(32, 1) */
255 },
256 {
257 .cmd = CMD_PREDICATE,
258 .srcarg = 4,
259 .value = 5
260 },
261 {
262 .cmd = CMD_PIO_READ_32,
263 .dstarg = 1,
264 .addr = NULL /* usbsts */
265 },
266 {
267 .cmd = CMD_AND,
268 .srcarg = 1,
269 .dstarg = 2,
270 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
271 },
272 {
273 .cmd = CMD_PIO_WRITE_A_32,
274 .srcarg = 2,
275 .addr = NULL /* usbsts */
276 },
277 {
278 .cmd = CMD_PIO_WRITE_A_32,
279 .srcarg = 3,
280 .addr = NULL /* intr[0].iman */
281 },
282 {
283 .cmd = CMD_ACCEPT
284 },
285 {
286 .cmd = CMD_DECLINE
287 }
288};
289
290
291/**
292 * Generates code to accept interrupts. The xHCI is designed primarily for
293 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
294 * (except 0) are disabled.
295 */
296int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
297{
298 assert(code);
299 assert(hw_res);
300
301 if (hw_res->irqs.count != 1) {
302 usb_log_info("Unexpected HW resources to enable interrupts.");
303 return EINVAL;
304 }
305
306 code->ranges = malloc(sizeof(irq_pio_range_t));
307 if (code->ranges == NULL)
308 return ENOMEM;
309
310 code->cmds = malloc(sizeof(irq_commands));
311 if (code->cmds == NULL) {
312 free(code->ranges);
313 return ENOMEM;
314 }
315
316 code->rangecount = 1;
317 code->ranges[0] = (irq_pio_range_t) {
318 .base = RNGABS(hc->mmio_range),
319 .size = RNGSZ(hc->mmio_range),
320 };
321
322 code->cmdcount = ARRAY_SIZE(irq_commands);
323 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
324
325 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
326 void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
327 code->cmds[0].addr = intr0_iman;
328 code->cmds[1].value = host2xhci(32, 1);
329 code->cmds[3].addr = usbsts;
330 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
331 code->cmds[5].addr = usbsts;
332 code->cmds[6].addr = intr0_iman;
333
334 return hw_res->irqs.irqs[0];
335}
336
337int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
338{
339 /* No legacy support capability, the controller is solely for us */
340 if (!hc->legsup)
341 return EOK;
342
343 /* Section 4.22.1 */
344 /* TODO: Test this with USB3-aware BIOS */
345 usb_log_debug2("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
346 XHCI_REG_WR(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
347 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
348 usb_log_debug2("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
349 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
350 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
351 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
352 assert(XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1);
353 return EOK;
354 }
355 async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
356 }
357 usb_log_error("BIOS did not release XHCI legacy hold!\n");
358
359 return ENOTSUP;
360}
361
362static int hc_reset(xhci_hc_t *hc)
363{
364 /* Stop the HC: set R/S to 0 */
365 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
366
367 /* Wait 16 ms until the HC is halted */
368 async_usleep(16000);
369 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
370
371 /* Reset */
372 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
373
374 /* Wait until the reset is complete */
375 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
376 async_usleep(1000);
377
378 return EOK;
379}
380
381/**
382 * Initialize the HC: section 4.2
383 */
384int hc_start(xhci_hc_t *hc, bool irq)
385{
386 int err;
387
388 if ((err = hc_reset(hc)))
389 return err;
390
391 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
392 async_usleep(1000);
393
394 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
395 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
396 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
397 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
398
399 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
400 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
401 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
402
403 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
404 uint64_t erdp = hc->event_ring.dequeue_ptr;
405 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
406 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
407 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
408 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
409 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
410 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
411
412 if (irq) {
413 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
414 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
415 }
416
417 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
418
419 return EOK;
420}
421
422/**
423 * Used only when polling. Shall supplement the irq_commands.
424 */
425int hc_status(xhci_hc_t *hc, uint32_t *status)
426{
427 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
428 if (ip) {
429 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
430 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
431 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
432
433 /* interrupt handler expects status from irq_commands, which is
434 * in xhci order. */
435 *status = host2xhci(32, *status);
436 }
437
438 usb_log_debug2("HC(%p): Polled status: %x", hc, *status);
439 return EOK;
440}
441
442int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
443{
444 assert(batch);
445
446 /* Check for root hub communication */
447 if (batch->ep->address == xhci_rh_get_address(&hc->rh)) {
448 usb_log_debug("XHCI root hub request.\n");
449 return xhci_rh_schedule(&hc->rh, batch);
450 }
451
452 usb_log_debug2("EP(%d:%d) started %s transfer of size %lu.",
453 batch->ep->address, batch->ep->endpoint,
454 usb_str_transfer_type(batch->ep->transfer_type),
455 batch->buffer_size);
456
457 switch (batch->ep->transfer_type) {
458 case USB_TRANSFER_CONTROL:
459 /* TODO: Send setup stage TRB. */
460 /* TODO: Optionally, send data stage TRB followed by zero or
461 more normal TRB's. */
462 /* TODO: Send status stage TRB. */
463 /* TODO: Ring the appropriate doorbell. */
464 break;
465 case USB_TRANSFER_ISOCHRONOUS:
466 /* TODO: Implement me. */
467 break;
468 case USB_TRANSFER_BULK:
469 /* TODO: Implement me. */
470 break;
471 case USB_TRANSFER_INTERRUPT:
472 /* TODO: Implement me. */
473 break;
474 }
475
476 return EOK;
477}
478
479typedef int (*event_handler) (xhci_hc_t *, xhci_trb_t *trb);
480
481static event_handler event_handlers [] = {
482 [XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
483 [XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT] = &xhci_handle_port_status_change_event,
484};
485
486static int hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb, xhci_interrupter_regs_t *intr)
487{
488 unsigned type = TRB_TYPE(*trb);
489 if (type >= ARRAY_SIZE(event_handlers) || !event_handlers[type])
490 return ENOTSUP;
491
492 return event_handlers[type](hc, trb);
493}
494
495static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
496{
497 int err;
498 ssize_t size = 16;
499 xhci_trb_t *queue = malloc(sizeof(xhci_trb_t) * size);
500 if (!queue) {
501 usb_log_error("Not enough memory to run the event ring.");
502 return;
503 }
504
505 xhci_trb_t *head = queue;
506
507 while ((err = xhci_event_ring_dequeue(event_ring, head)) != ENOENT) {
508 if (err != EOK) {
509 usb_log_warning("Error while accessing event ring: %s", str_error(err));
510 break;
511 }
512
513 usb_log_debug2("Dequeued trb from event ring: %s", xhci_trb_str_type(TRB_TYPE(*head)));
514 head++;
515
516 /* Expand the array if needed. */
517 if (head - queue >= size) {
518 size *= 2;
519 xhci_trb_t *new_queue = realloc(queue, size);
520 if (new_queue == NULL)
521 break; /* Will process only those TRBs we have memory for. */
522
523 head = new_queue + (head - queue);
524 }
525 }
526
527 /* Update the ERDP to make room in the ring. */
528 usb_log_debug2("Copying from ring finished, updating ERDP.");
529 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
530 uint64_t erdp = hc->event_ring.dequeue_ptr;
531 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
532 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
533 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
534
535 /* Handle all of the collected events if possible. */
536 if (head == queue)
537 usb_log_warning("No events to be handled!");
538
539 for (xhci_trb_t *tail = queue; tail != head; tail++) {
540 if ((err = hc_handle_event(hc, tail, intr)) != EOK) {
541 usb_log_error("Failed to handle event: %s", str_error(err));
542 }
543 }
544
545 free(queue);
546 usb_log_debug2("Event ring run finished.");
547}
548
549void hc_interrupt(xhci_hc_t *hc, uint32_t status)
550{
551 status = xhci2host(32, status);
552
553 /* TODO: Figure out how root hub interrupts work. */
554 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
555 usb_log_debug2("Root hub interrupt.");
556 xhci_rh_interrupt(&hc->rh);
557
558 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
559 }
560
561 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
562 usb_log_error("Host controller error occured. Bad things gonna happen...");
563 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
564 }
565
566 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
567 usb_log_debug2("Event interrupt, running the event ring.");
568 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
569 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
570 }
571
572 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
573 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
574 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
575 }
576
577 if (status) {
578 usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
579 }
580}
581
582static void hc_dcbaa_fini(xhci_hc_t *hc)
583{
584 xhci_trb_ring_t* trb_ring;
585 xhci_scratchpad_free(hc);
586
587 /* Idx 0 already deallocated by xhci_scratchpad_free. */
588 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
589 if (hc->dcbaa_virt[i].dev_ctx) {
590 free32(hc->dcbaa_virt[i].dev_ctx);
591 hc->dcbaa_virt[i].dev_ctx = NULL;
592 }
593
594 for (unsigned i = 0; i < XHCI_EP_COUNT; ++i) {
595 trb_ring = hc->dcbaa_virt[i].trs[i];
596 if (trb_ring) {
597 hc->dcbaa_virt[i].trs[i] = NULL;
598 xhci_trb_ring_fini(trb_ring);
599 free32(trb_ring);
600 }
601 }
602 }
603
604 free32(hc->dcbaa);
605 free32(hc->dcbaa_virt);
606}
607
608void hc_fini(xhci_hc_t *hc)
609{
610 xhci_trb_ring_fini(&hc->command_ring);
611 xhci_event_ring_fini(&hc->event_ring);
612 hc_dcbaa_fini(hc);
613 xhci_fini_commands(hc);
614 xhci_rh_fini(&hc->rh);
615 pio_disable(hc->base, RNGSZ(hc->mmio_range));
616 usb_log_info("HC(%p): Finalized.", hc);
617}
618
619
620
621/**
622 * @}
623 */
Note: See TracBrowser for help on using the repository browser.