| 1 | /*
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| 2 | * Copyright (c) 2017 Petr Manek
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief The host controller endpoint management.
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| 34 | */
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| 35 |
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| 36 | #ifndef XHCI_ENDPOINT_H
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| 37 | #define XHCI_ENDPOINT_H
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| 38 |
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| 39 | #include <assert.h>
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| 40 |
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| 41 | #include <usb/debug.h>
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| 42 | #include <usb/host/endpoint.h>
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| 43 | #include <usb/host/hcd.h>
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| 44 |
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| 45 | #include "trb_ring.h"
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| 46 |
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| 47 | #include "transfers.h"
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| 48 |
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| 49 | typedef struct xhci_device xhci_device_t;
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| 50 | typedef struct xhci_endpoint xhci_endpoint_t;
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| 51 | typedef struct xhci_bus xhci_bus_t;
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| 52 |
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| 53 | enum {
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| 54 | EP_TYPE_INVALID = 0,
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| 55 | EP_TYPE_ISOCH_OUT = 1,
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| 56 | EP_TYPE_BULK_OUT = 2,
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| 57 | EP_TYPE_INTERRUPT_OUT = 3,
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| 58 | EP_TYPE_CONTROL = 4,
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| 59 | EP_TYPE_ISOCH_IN = 5,
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| 60 | EP_TYPE_BULK_IN = 6,
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| 61 | EP_TYPE_INTERRUPT_IN = 7
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| 62 | };
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| 63 |
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| 64 | /** Connector structure linking endpoint context to the endpoint. */
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| 65 | typedef struct xhci_endpoint {
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| 66 | endpoint_t base; /**< Inheritance. Keep this first. */
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| 67 |
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| 68 | /** Main transfer ring (unused if streams are enabled) */
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| 69 | xhci_trb_ring_t ring;
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| 70 |
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| 71 | /** There shall be only one transfer active on an endpoint. The
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| 72 | * synchronization is performed using the active flag in base
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| 73 | * endpoint_t */
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| 74 | xhci_transfer_t active_transfer;
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| 75 |
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| 76 | /** Primary stream context array (or NULL if endpoint doesn't use streams) */
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| 77 | xhci_stream_ctx_t *primary_stream_ctx_array;
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| 78 |
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| 79 | /** 2-log of maximum number of primary streams (0-16). Not to be used directly. */
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| 80 | uint8_t max_streams;
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| 81 |
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| 82 | /** Maximum number of consecutive USB transactions (0-15) that should be executed per scheduling opportunity */
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| 83 | uint8_t max_burst;
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| 84 |
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| 85 | /** Maximum number of bursts within an interval that this endpoint supports */
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| 86 | uint8_t mult;
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| 87 | } xhci_endpoint_t;
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| 88 |
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| 89 | #define XHCI_EP_FMT "(%d:%d %s)"
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| 90 | #define XHCI_EP_ARGS(ep) \
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| 91 | ((ep).base.device->address), \
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| 92 | ((ep).base.endpoint), \
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| 93 | (usb_str_transfer_type((ep).base.transfer_type))
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| 94 |
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| 95 | typedef struct xhci_device {
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| 96 | device_t base; /**< Inheritance. Keep this first. */
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| 97 |
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| 98 | /** Slot ID assigned to the device by xHC. */
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| 99 | uint32_t slot_id;
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| 100 |
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| 101 | /** Corresponding port on RH */
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| 102 | uint8_t rh_port;
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| 103 |
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| 104 | /** USB Tier of the device */
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| 105 | uint8_t tier;
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| 106 |
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| 107 | /** Route string */
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| 108 | uint32_t route_str;
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| 109 |
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| 110 | /** Place to store virtual address for allocated context */
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| 111 | xhci_device_ctx_t *dev_ctx;
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| 112 |
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| 113 | /** All endpoints of the device. Inactive ones are NULL */
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| 114 | xhci_endpoint_t *endpoints[XHCI_EP_COUNT];
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| 115 |
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| 116 | /** Number of non-NULL endpoints. Reference count of sorts. */
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| 117 | uint8_t active_endpoint_count;
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| 118 |
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| 119 | /** Flag indicating whether the device is USB3 (it's USB2 otherwise). */
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| 120 | bool usb3;
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| 121 |
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| 122 | /** True if the device can add new endpoints and schedule transfers. */
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| 123 | volatile bool online;
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| 124 | } xhci_device_t;
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| 125 |
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| 126 | int xhci_endpoint_init(xhci_endpoint_t *, xhci_bus_t *);
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| 127 | void xhci_endpoint_fini(xhci_endpoint_t *);
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| 128 | int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *);
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| 129 | int xhci_endpoint_free_transfer_ds(xhci_endpoint_t *);
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| 130 |
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| 131 | uint8_t xhci_endpoint_dci(xhci_endpoint_t *);
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| 132 | uint8_t xhci_endpoint_index(xhci_endpoint_t *);
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| 133 |
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| 134 | void xhci_setup_endpoint_context(xhci_endpoint_t *, xhci_ep_ctx_t *);
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| 135 |
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| 136 | int xhci_device_add_endpoint(xhci_hc_t *, xhci_device_t *, xhci_endpoint_t *);
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| 137 | int xhci_device_remove_endpoint(xhci_hc_t *, xhci_device_t *, xhci_endpoint_t *);
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| 138 | xhci_endpoint_t * xhci_device_get_endpoint(xhci_device_t *, usb_endpoint_t);
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| 139 |
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| 140 | static inline xhci_device_t * xhci_device_get(device_t *dev)
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| 141 | {
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| 142 | assert(dev);
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| 143 | return (xhci_device_t *) dev;
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| 144 | }
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| 145 |
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| 146 | static inline xhci_endpoint_t * xhci_endpoint_get(endpoint_t *ep)
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| 147 | {
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| 148 | assert(ep);
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| 149 | return (xhci_endpoint_t *) ep;
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| 150 | }
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| 151 |
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| 152 | static inline xhci_device_t * xhci_ep_to_dev(xhci_endpoint_t *ep)
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| 153 | {
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| 154 | assert(ep);
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| 155 | return xhci_device_get(ep->base.device);
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| 156 | }
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| 157 |
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| 158 | #endif
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| 159 |
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| 160 | /**
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| 161 | * @}
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| 162 | */
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