| [c0ec9e7] | 1 | /*
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| 2 | * Copyright (c) 2017 Petr Manek
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief The host controller endpoint management.
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| 34 | */
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| 35 |
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| 36 | #ifndef XHCI_ENDPOINT_H
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| 37 | #define XHCI_ENDPOINT_H
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| 38 |
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| 39 | #include <assert.h>
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| 40 |
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| 41 | #include <usb/debug.h>
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| [b80c1ab] | 42 | #include <usb/host/dma_buffer.h>
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| [c0ec9e7] | 43 | #include <usb/host/endpoint.h>
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| 44 | #include <usb/host/hcd.h>
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| [479e32d] | 45 | #include <ddf/driver.h>
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| [c0ec9e7] | 46 |
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| [2cf28b9] | 47 | #include "trb_ring.h"
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| 48 |
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| [2b61945] | 49 | #include "transfers.h"
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| [d7869d7e] | 50 |
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| [c10daa8] | 51 | typedef struct xhci_device xhci_device_t;
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| [41924f30] | 52 | typedef struct xhci_endpoint xhci_endpoint_t;
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| 53 | typedef struct xhci_bus xhci_bus_t;
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| 54 |
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| [370a1c8] | 55 | enum {
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| 56 | EP_TYPE_INVALID = 0,
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| 57 | EP_TYPE_ISOCH_OUT = 1,
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| 58 | EP_TYPE_BULK_OUT = 2,
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| 59 | EP_TYPE_INTERRUPT_OUT = 3,
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| 60 | EP_TYPE_CONTROL = 4,
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| 61 | EP_TYPE_ISOCH_IN = 5,
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| 62 | EP_TYPE_BULK_IN = 6,
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| 63 | EP_TYPE_INTERRUPT_IN = 7
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| 64 | };
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| 65 |
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| [176a70a] | 66 | /** Connector structure linking endpoint context to the endpoint. */
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| 67 | typedef struct xhci_endpoint {
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| [41924f30] | 68 | endpoint_t base; /**< Inheritance. Keep this first. */
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| 69 |
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| [82fe063] | 70 | /** Main transfer ring (unused if streams are enabled) */
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| [2b61945] | 71 | xhci_trb_ring_t ring;
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| 72 |
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| [ef1a3a8] | 73 | /** Primary stream context array (or NULL if endpoint doesn't use streams). */
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| [89cefe78] | 74 | xhci_stream_ctx_t *primary_stream_ctx_array;
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| [b80c1ab] | 75 | dma_buffer_t primary_stream_ctx_dma;
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| [89cefe78] | 76 |
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| [ef1a3a8] | 77 | /** Primary stream ring array (or NULL if endpoint doesn't use streams). */
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| 78 | xhci_trb_ring_t *primary_stream_rings;
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| 79 |
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| 80 | /** Size of the allocated primary stream context array (and ring array). */
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| [3f6c94ed] | 81 | uint16_t primary_stream_ctx_array_size;
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| 82 |
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| [81487c4a] | 83 | /** 2-log of maximum number of primary streams (0-16). Not to be used directly. */
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| [82fe063] | 84 | uint8_t max_streams;
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| [89cefe78] | 85 |
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| [82fe063] | 86 | /** Maximum number of consecutive USB transactions (0-15) that should be executed per scheduling opportunity */
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| [89cefe78] | 87 | uint8_t max_burst;
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| [82fe063] | 88 |
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| 89 | /** Maximum number of bursts within an interval that this endpoint supports */
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| [89cefe78] | 90 | uint8_t mult;
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| [d3086873] | 91 |
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| 92 | /** The maximum size of an isochronous transfer and therefore the size of buffers */
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| 93 | size_t isoch_max_size;
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| 94 |
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| 95 | /** Isochronous scheduled transfers with respective buffers */
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| 96 | #define XHCI_ISOCH_BUFFER_COUNT 4
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| 97 | xhci_isoch_transfer_t* isoch_transfers[XHCI_ISOCH_BUFFER_COUNT];
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| 98 |
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| 99 | /** Indices to transfers */
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| 100 | size_t isoch_dequeue, isoch_enqueue;
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| 101 |
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| 102 | /** Are isochronous transfers started? */
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| 103 | bool isoch_started;
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| [176a70a] | 104 | } xhci_endpoint_t;
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| 105 |
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| [a5b3de6] | 106 | #define XHCI_EP_FMT "(%d:%d %s)"
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| [9620a54] | 107 | /* FIXME: "Device -1" messes up log messages, figure out a better way. */
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| [a5b3de6] | 108 | #define XHCI_EP_ARGS(ep) \
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| [9620a54] | 109 | ((ep).base.device ? (ep).base.device->address : -1), \
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| [a5b3de6] | 110 | ((ep).base.endpoint), \
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| 111 | (usb_str_transfer_type((ep).base.transfer_type))
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| 112 |
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| [c10daa8] | 113 | typedef struct xhci_device {
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| [2b61945] | 114 | device_t base; /**< Inheritance. Keep this first. */
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| [c10daa8] | 115 |
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| [2770b66] | 116 | /** Slot ID assigned to the device by xHC. */
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| [c10daa8] | 117 | uint32_t slot_id;
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| 118 |
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| [2cf28b9] | 119 | /** Corresponding port on RH */
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| 120 | uint8_t rh_port;
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| 121 |
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| 122 | /** USB Tier of the device */
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| 123 | uint8_t tier;
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| 124 |
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| 125 | /** Route string */
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| 126 | uint32_t route_str;
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| 127 |
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| [b80c1ab] | 128 | /** Place to store the allocated context */
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| 129 | dma_buffer_t dev_ctx;
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| [2770b66] | 130 |
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| [9620a54] | 131 | /** All endpoints of the device. Dropped ones are NULL */
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| [9b2f69e] | 132 | xhci_endpoint_t *endpoints[XHCI_EP_COUNT];
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| [2770b66] | 133 |
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| [9b2f69e] | 134 | /** Flag indicating whether the device is USB3 (it's USB2 otherwise). */
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| 135 | bool usb3;
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| [a4e26882] | 136 |
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| 137 | /** True if the device can add new endpoints and schedule transfers. */
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| 138 | volatile bool online;
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| [c10daa8] | 139 | } xhci_device_t;
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| 140 |
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| [9620a54] | 141 | #define XHCI_DEV_FMT "(%s, slot %d)"
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| 142 | #define XHCI_DEV_ARGS(dev) ddf_fun_get_name((dev).base.fun), (dev).slot_id
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| 143 |
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| [41924f30] | 144 | int xhci_endpoint_init(xhci_endpoint_t *, xhci_bus_t *);
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| 145 | void xhci_endpoint_fini(xhci_endpoint_t *);
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| [89cefe78] | 146 | int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *);
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| [9620a54] | 147 | void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *);
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| [c0ec9e7] | 148 |
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| [3f6c94ed] | 149 | int xhci_endpoint_request_streams(xhci_hc_t *, xhci_device_t *, xhci_endpoint_t *, unsigned);
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| 150 |
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| [2b61945] | 151 | uint8_t xhci_endpoint_dci(xhci_endpoint_t *);
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| [dbf32b1] | 152 | uint8_t xhci_endpoint_index(xhci_endpoint_t *);
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| [f971e957] | 153 |
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| [0206d35] | 154 | void xhci_setup_endpoint_context(xhci_endpoint_t *, xhci_ep_ctx_t *);
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| 155 |
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| [8b8c164] | 156 | int xhci_device_add_endpoint(xhci_device_t *, xhci_endpoint_t *);
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| 157 | void xhci_device_remove_endpoint(xhci_endpoint_t *);
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| [c10daa8] | 158 | xhci_endpoint_t * xhci_device_get_endpoint(xhci_device_t *, usb_endpoint_t);
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| 159 |
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| [2b61945] | 160 | static inline xhci_device_t * xhci_device_get(device_t *dev)
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| 161 | {
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| 162 | assert(dev);
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| 163 | return (xhci_device_t *) dev;
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| 164 | }
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| 165 |
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| [41924f30] | 166 | static inline xhci_endpoint_t * xhci_endpoint_get(endpoint_t *ep)
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| [176a70a] | 167 | {
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| [eaf5e86] | 168 | assert(ep);
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| [41924f30] | 169 | return (xhci_endpoint_t *) ep;
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| [176a70a] | 170 | }
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| 171 |
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| [2b61945] | 172 | static inline xhci_device_t * xhci_ep_to_dev(xhci_endpoint_t *ep)
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| 173 | {
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| 174 | assert(ep);
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| 175 | return xhci_device_get(ep->base.device);
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| 176 | }
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| 177 |
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| [c0ec9e7] | 178 | #endif
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| 179 |
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| 180 | /**
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| 181 | * @}
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| 182 | */
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