source: mainline/uspace/drv/bus/usb/xhci/endpoint.h

Last change on this file was ae3a941, checked in by Ondřej Hlavatý <aearsis@…>, 7 years ago

usb: cstyle

  • Property mode set to 100644
File size: 4.6 KB
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[c0ec9e7]1/*
[e0a5d4c]2 * Copyright (c) 2018 Petr Manek, Ondrej Hlavaty, Michal Staruch, Jan Hrach
[c0ec9e7]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller endpoint management.
34 */
35
36#ifndef XHCI_ENDPOINT_H
37#define XHCI_ENDPOINT_H
38
39#include <assert.h>
40
41#include <usb/debug.h>
[3b60ea0]42#include <usb/dma_buffer.h>
[c0ec9e7]43#include <usb/host/endpoint.h>
44#include <usb/host/hcd.h>
[479e32d]45#include <ddf/driver.h>
[c0ec9e7]46
[682c9354]47#include "device.h"
[708d8fcd]48#include "isoch.h"
[2b61945]49#include "transfers.h"
[708d8fcd]50#include "trb_ring.h"
[d7869d7e]51
[c10daa8]52typedef struct xhci_device xhci_device_t;
[41924f30]53typedef struct xhci_endpoint xhci_endpoint_t;
[47e9494]54typedef struct xhci_stream_data xhci_stream_data_t;
[41924f30]55typedef struct xhci_bus xhci_bus_t;
56
[370a1c8]57enum {
58 EP_TYPE_INVALID = 0,
59 EP_TYPE_ISOCH_OUT = 1,
60 EP_TYPE_BULK_OUT = 2,
61 EP_TYPE_INTERRUPT_OUT = 3,
62 EP_TYPE_CONTROL = 4,
63 EP_TYPE_ISOCH_IN = 5,
64 EP_TYPE_BULK_IN = 6,
65 EP_TYPE_INTERRUPT_IN = 7
66};
67
[176a70a]68/** Connector structure linking endpoint context to the endpoint. */
69typedef struct xhci_endpoint {
[41924f30]70 endpoint_t base; /**< Inheritance. Keep this first. */
71
[4db49344]72 /** Guarding scheduling of this endpoint. */
73 fibril_mutex_t guard;
74
[82fe063]75 /** Main transfer ring (unused if streams are enabled) */
[2b61945]76 xhci_trb_ring_t ring;
77
[ae3a941]78 /**
79 * Primary stream context data array
80 * (or NULL if endpoint doesn't use streams).
81 */
[47e9494]82 xhci_stream_data_t *primary_stream_data_array;
83
84 /** Primary stream context array - allocated for xHC hardware. */
[89cefe78]85 xhci_stream_ctx_t *primary_stream_ctx_array;
[b80c1ab]86 dma_buffer_t primary_stream_ctx_dma;
[89cefe78]87
[ae3a941]88 /** Size of the allocated primary stream data and context array. */
[47e9494]89 uint16_t primary_stream_data_size;
[3f6c94ed]90
[bdd8842c]91 /* Maximum number of primary streams (0 - 2^16). */
92 uint32_t max_streams;
[89cefe78]93
[ae3a941]94 /**
95 * Maximum number of consecutive USB transactions (0-15) that
96 * should be executed per scheduling opportunity
97 */
[89cefe78]98 uint8_t max_burst;
[82fe063]99
[ae3a941]100 /**
101 * Maximum number of bursts within an interval that
102 * this endpoint supports
103 */
[89cefe78]104 uint8_t mult;
[d3086873]105
[ae3a941]106 /**
107 * Scheduling interval for periodic endpoints,
108 * as a number of 125us units. (0 - 2^16)
109 */
[bdd8842c]110 uint32_t interval;
[5c75456]111
[ae3a941]112 /**
113 * This field is a valid pointer for (and only for) isochronous
114 * endpoints.
115 */
[708d8fcd]116 xhci_isoch_t isoch [0];
[176a70a]117} xhci_endpoint_t;
118
[a5b3de6]119#define XHCI_EP_FMT "(%d:%d %s)"
[9620a54]120/* FIXME: "Device -1" messes up log messages, figure out a better way. */
[a5b3de6]121#define XHCI_EP_ARGS(ep) \
[9620a54]122 ((ep).base.device ? (ep).base.device->address : -1), \
[a5b3de6]123 ((ep).base.endpoint), \
124 (usb_str_transfer_type((ep).base.transfer_type))
125
[3dd80f8]126extern int xhci_endpoint_type(xhci_endpoint_t *ep);
[47e9494]127
[ae3a941]128extern endpoint_t *xhci_endpoint_create(device_t *,
129 const usb_endpoint_descriptors_t *);
[45457265]130extern errno_t xhci_endpoint_register(endpoint_t *);
[3dd80f8]131extern void xhci_endpoint_unregister(endpoint_t *);
132extern void xhci_endpoint_destroy(endpoint_t *);
[c0ec9e7]133
[3dd80f8]134extern void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *);
135extern xhci_trb_ring_t *xhci_endpoint_get_ring(xhci_endpoint_t *, uint32_t);
[f971e957]136
[3dd80f8]137extern void xhci_setup_endpoint_context(xhci_endpoint_t *, xhci_ep_ctx_t *);
[45457265]138extern errno_t xhci_endpoint_clear_halt(xhci_endpoint_t *, unsigned);
[0206d35]139
[ae3a941]140static inline xhci_endpoint_t *xhci_endpoint_get(endpoint_t *ep)
[176a70a]141{
[eaf5e86]142 assert(ep);
[41924f30]143 return (xhci_endpoint_t *) ep;
[176a70a]144}
145
[ae3a941]146static inline xhci_device_t *xhci_ep_to_dev(xhci_endpoint_t *ep)
[2b61945]147{
148 assert(ep);
149 return xhci_device_get(ep->base.device);
150}
151
[c0ec9e7]152#endif
153
154/**
155 * @}
156 */
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