source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 2896ff6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2896ff6 was 2896ff6, checked in by Petr Manek <petr.manek@…>, 8 years ago

Vaguer log level. Extracted timeout constant from command completion waiting and increased it for a bit.
  • Property mode set to 100644
File size: 13.4 KB
Line 
1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
43#include "hw_struct/context.h"
44#include "hw_struct/trb.h"
45
46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52#define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
53
54/**
55 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
56 */
57#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
58#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
59
60#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
61#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
62#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
63
64int xhci_init_commands(xhci_hc_t *hc)
65{
66 assert(hc);
67
68 list_initialize(&hc->commands);
69 return EOK;
70}
71
72void xhci_fini_commands(xhci_hc_t *hc)
73{
74 // Note: Untested.
75 assert(hc);
76}
77
78int xhci_cmd_wait(xhci_cmd_t *cmd)
79{
80 const suseconds_t timeout = 1000000;
81 int rv = EOK;
82
83 fibril_mutex_lock(&cmd->completed_mtx);
84 while (!cmd->completed) {
85 usb_log_debug2("Waiting for event completion: going to sleep.");
86 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
87
88 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
89 if (rv == ETIMEOUT)
90 break;
91 }
92 fibril_mutex_unlock(&cmd->completed_mtx);
93
94 return rv;
95}
96
97xhci_cmd_t *xhci_cmd_alloc(void)
98{
99 xhci_cmd_t *cmd = malloc(sizeof(xhci_cmd_t));
100 xhci_cmd_init(cmd);
101
102 usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
103 return cmd;
104}
105
106void xhci_cmd_init(xhci_cmd_t *cmd)
107{
108 memset(cmd, 0, sizeof(*cmd));
109
110 link_initialize(&cmd->link);
111
112 fibril_mutex_initialize(&cmd->completed_mtx);
113 fibril_condvar_initialize(&cmd->completed_cv);
114}
115
116void xhci_cmd_fini(xhci_cmd_t *cmd)
117{
118 list_remove(&cmd->link);
119}
120
121void xhci_cmd_free(xhci_cmd_t *cmd)
122{
123 xhci_cmd_fini(cmd);
124 free(cmd);
125}
126
127static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
128{
129 link_t *cmd_link = list_first(&hc->commands);
130
131 while (cmd_link != NULL) {
132 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
133
134 if (cmd->trb_phys == phys)
135 break;
136
137 cmd_link = list_next(cmd_link, &hc->commands);
138 }
139
140 if (cmd_link != NULL) {
141 list_remove(cmd_link);
142
143 return list_get_instance(cmd_link, xhci_cmd_t, link);
144 }
145
146 return NULL;
147}
148
149static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
150{
151 assert(hc);
152 assert(cmd);
153
154 list_append(&cmd->link, &hc->commands);
155
156 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
157 hc_ring_doorbell(hc, doorbell, target);
158
159 usb_log_debug2("HC(%p): Sent command:", hc);
160 xhci_dump_trb(&cmd->trb);
161
162 return EOK;
163}
164
165void xhci_stop_command_ring(xhci_hc_t *hc)
166{
167 assert(hc);
168
169 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
170
171 /**
172 * Note: There is a bug in qemu that checks CS only when CRCR_HI
173 * is written, this (and the read/write in abort) ensures
174 * the command rings stops.
175 */
176 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
177}
178
179void xhci_abort_command_ring(xhci_hc_t *hc)
180{
181 assert(hc);
182
183 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
184 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
185}
186
187void xhci_start_command_ring(xhci_hc_t *hc)
188{
189 assert(hc);
190
191 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
192 hc_ring_doorbell(hc, 0, 0);
193}
194
195static const char *trb_codes [] = {
196#define TRBC(t) [XHCI_TRBC_##t] = #t
197 TRBC(INVALID),
198 TRBC(SUCCESS),
199 TRBC(DATA_BUFFER_ERROR),
200 TRBC(BABBLE_DETECTED_ERROR),
201 TRBC(USB_TRANSACTION_ERROR),
202 TRBC(TRB_ERROR),
203 TRBC(STALL_ERROR),
204 TRBC(RESOURCE_ERROR),
205 TRBC(BANDWIDTH_ERROR),
206 TRBC(NO_SLOTS_ERROR),
207 TRBC(INVALID_STREAM_ERROR),
208 TRBC(SLOT_NOT_ENABLED_ERROR),
209 TRBC(EP_NOT_ENABLED_ERROR),
210 TRBC(SHORT_PACKET),
211 TRBC(RING_UNDERRUN),
212 TRBC(RING_OVERRUN),
213 TRBC(VF_EVENT_RING_FULL),
214 TRBC(PARAMETER_ERROR),
215 TRBC(BANDWIDTH_OVERRUN_ERROR),
216 TRBC(CONTEXT_STATE_ERROR),
217 TRBC(NO_PING_RESPONSE_ERROR),
218 TRBC(EVENT_RING_FULL_ERROR),
219 TRBC(INCOMPATIBLE_DEVICE_ERROR),
220 TRBC(MISSED_SERVICE_ERROR),
221 TRBC(COMMAND_RING_STOPPED),
222 TRBC(COMMAND_ABORTED),
223 TRBC(STOPPED),
224 TRBC(STOPPED_LENGTH_INVALID),
225 TRBC(STOPPED_SHORT_PACKET),
226 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
227 [30] = "<reserved>",
228 TRBC(ISOCH_BUFFER_OVERRUN),
229 TRBC(EVENT_LOST_ERROR),
230 TRBC(UNDEFINED_ERROR),
231 TRBC(INVALID_STREAM_ID_ERROR),
232 TRBC(SECONDARY_BANDWIDTH_ERROR),
233 TRBC(SPLIT_TRANSACTION_ERROR),
234 [XHCI_TRBC_MAX] = NULL
235#undef TRBC
236};
237
238static void report_error(int code)
239{
240 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
241 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
242 else
243 usb_log_error("Command resulted in reserved or vendor specific error.");
244}
245
246int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
247{
248 assert(hc);
249
250 xhci_trb_clean(&cmd->trb);
251
252 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
253
254 return enqueue_command(hc, cmd, 0, 0);
255}
256
257int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
258{
259 assert(hc);
260
261 xhci_trb_clean(&cmd->trb);
262
263 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
264 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
265
266 return enqueue_command(hc, cmd, 0, 0);
267}
268
269int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
270{
271 assert(hc);
272 assert(cmd);
273
274 xhci_trb_clean(&cmd->trb);
275
276 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
277 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
278
279 return enqueue_command(hc, cmd, 0, 0);
280}
281
282int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
283{
284 assert(hc);
285 assert(cmd);
286 assert(ictx);
287
288 /**
289 * TODO: Requirements for this command:
290 * dcbaa[slot_id] is properly sized and initialized
291 * ictx has valids slot context and endpoint 0, all
292 * other should be ignored at this point (see section 4.6.5).
293 */
294
295 xhci_trb_clean(&cmd->trb);
296
297 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
298 TRB_SET_ICTX(cmd->trb, phys_addr);
299
300 /**
301 * Note: According to section 6.4.3.4, we can set the 9th bit
302 * of the control field of the trb (BSR) to 1 and then the xHC
303 * will not issue the SET_ADDRESS request to the USB device.
304 * This can be used to provide compatibility with legacy USB devices
305 * that require their device descriptor to be read before such request.
306 */
307 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
308 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
309
310 return enqueue_command(hc, cmd, 0, 0);
311}
312
313int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
314{
315 assert(hc);
316 assert(cmd);
317 assert(ictx);
318
319 xhci_trb_clean(&cmd->trb);
320
321 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
322 TRB_SET_ICTX(cmd->trb, phys_addr);
323
324 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
325 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
326
327 return enqueue_command(hc, cmd, 0, 0);
328}
329
330int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
331{
332 assert(hc);
333 assert(cmd);
334 assert(ictx);
335
336 /**
337 * Note: All Drop Context flags of the input context shall be 0,
338 * all Add Context flags shall be initialize to indicate IDs
339 * of the contexts affected by the command.
340 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
341 */
342 xhci_trb_clean(&cmd->trb);
343
344 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
345 TRB_SET_ICTX(cmd->trb, phys_addr);
346
347 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
348 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
349
350 return enqueue_command(hc, cmd, 0, 0);
351}
352
353int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
354{
355 assert(hc);
356 assert(cmd);
357
358 /**
359 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
360 * information about this flag.
361 */
362 xhci_trb_clean(&cmd->trb);
363
364 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
365 TRB_SET_TCS(cmd->trb, tcs);
366 TRB_SET_EP(cmd->trb, ep_id);
367 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
368
369 return enqueue_command(hc, cmd, 0, 0);
370}
371
372int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
373{
374 assert(hc);
375 assert(cmd);
376
377 xhci_trb_clean(&cmd->trb);
378
379 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
380 TRB_SET_EP(cmd->trb, ep_id);
381 TRB_SET_SUSP(cmd->trb, susp);
382 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
383
384 return enqueue_command(hc, cmd, 0, 0);
385}
386
387int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
388 uintptr_t dequeue_ptr, uint16_t stream_id,
389 uint32_t ep_id)
390{
391 assert(hc);
392 assert(cmd);
393
394 xhci_trb_clean(&cmd->trb);
395
396 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
397 TRB_SET_EP(cmd->trb, ep_id);
398 TRB_SET_STREAM(cmd->trb, stream_id);
399 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
400 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
401
402 /**
403 * TODO: Set DCS (see section 4.6.10).
404 */
405
406 return enqueue_command(hc, cmd, 0, 0);
407}
408
409int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
410{
411 assert(hc);
412 assert(cmd);
413
414 xhci_trb_clean(&cmd->trb);
415
416 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
417 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
418
419 return enqueue_command(hc, cmd, 0, 0);
420}
421
422int xhci_get_port_bandwidth_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
423 xhci_port_bandwidth_ctx_t *ctx, uint8_t device_speed)
424{
425 assert(hc);
426 assert(cmd);
427
428 xhci_trb_clean(&cmd->trb);
429
430 uint64_t phys_addr = (uint64_t) addr_to_phys(ctx);
431 TRB_SET_ICTX(cmd->trb, phys_addr);
432
433 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
434 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
435 TRB_SET_DEV_SPEED(cmd->trb, device_speed);
436
437 return enqueue_command(hc, cmd, 0, 0);
438}
439
440int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
441{
442 // TODO: Update dequeue ptrs.
443 assert(hc);
444 assert(trb);
445
446 usb_log_debug("HC(%p) Command completed.", hc);
447
448 int code;
449 uint64_t phys;
450 xhci_cmd_t *command;
451
452 code = TRB_GET_CODE(*trb);
453 phys = TRB_GET_PHYS(*trb);;
454 command = get_command(hc, phys);
455 if (command == NULL) {
456 // TODO: STOP & ABORT may not have command structs in the list!
457 usb_log_debug("No command struct for this completion event found.");
458
459 if (code != XHCI_TRBC_SUCCESS)
460 report_error(code);
461
462 return EOK;
463 }
464
465 command->status = code;
466 command->slot_id = TRB_GET_SLOT(*trb);
467
468 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
469 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
470 if (code != XHCI_TRBC_SUCCESS) {
471 report_error(code);
472 xhci_dump_trb(&command->trb);
473 }
474 }
475
476 switch (TRB_TYPE(command->trb)) {
477 case XHCI_TRB_TYPE_NO_OP_CMD:
478 assert(code == XHCI_TRBC_TRB_ERROR);
479 break;
480 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
481 break;
482 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
483 break;
484 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
485 break;
486 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
487 break;
488 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
489 break;
490 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
491 break;
492 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
493 // Note: If the endpoint was in the middle of a transfer, then the xHC
494 // will add a Transfer TRB before the Event TRB, research that and
495 // handle it appropriately!
496 break;
497 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
498 break;
499 default:
500 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
501
502 command->completed = true;
503 return ENAK;
504 }
505
506 fibril_mutex_lock(&command->completed_mtx);
507 command->completed = true;
508 fibril_condvar_broadcast(&command->completed_cv);
509 fibril_mutex_unlock(&command->completed_mtx);
510
511 return EOK;
512}
513
514
515/**
516 * @}
517 */
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