source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 4d28d86

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4d28d86 was 548c123, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci commands: embed TRB into the command structure

Previously, a pointer into the TRB ring itself was contained. That could cause
problems, because the ring does not care and can move/deallocate segments, or
overwrite TRBs inside. To solve the original issue, xhci_trb_ring_enqueue can
now fill physical address of the TRB enqueued.

Also, this eliminates the need to track ownage of TRB.

  • Property mode set to 100644
File size: 12.9 KB
RevLine 
[c9c0e41]1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
[8db42f7]43#include "hw_struct/context.h"
[c9c0e41]44#include "hw_struct/trb.h"
45
[1b78a7c1]46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
[0cabd10]49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
[1b78a7c1]50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52
[0cabd10]53/**
54 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
55 */
56#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
[548c123]57#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
[1b78a7c1]58
59#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
60#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
61#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
62
[110d795]63int xhci_init_commands(xhci_hc_t *hc)
64{
65 assert(hc);
66
67 list_initialize(&hc->commands);
68 return EOK;
69}
70
[c46c356]71void xhci_fini_commands(xhci_hc_t *hc)
72{
73 // Note: Untested.
74 assert(hc);
75
76 // We assume that the hc is dying/stopping, so we ignore
77 // the ownership of the commands.
78 list_foreach(hc->commands, link, xhci_cmd_t, cmd) {
79 xhci_free_command(cmd);
80 }
81}
82
[c4d4fa2]83int xhci_wait_for_command(xhci_cmd_t *cmd, uint32_t timeout)
[110d795]84{
85 uint32_t time = 0;
86 while (!cmd->completed) {
87 async_usleep(1000);
88 time += 1000;
89
90 if (time > timeout)
91 return ETIMEOUT;
92 }
93
94 return EOK;
95}
96
97xhci_cmd_t *xhci_alloc_command(void)
98{
99 xhci_cmd_t *cmd = malloc32(sizeof(xhci_cmd_t));
100 memset(cmd, 0, sizeof(xhci_cmd_t));
101
102 link_initialize(&cmd->link);
103
104 /**
105 * Internal functions will set this to false, other are implicit
106 * owners unless they overwrite this field.
107 * TODO: Is this wise?
108 */
109 cmd->has_owner = true;
110
111 return cmd;
112}
113
114void xhci_free_command(xhci_cmd_t *cmd)
115{
[9304b66]116 list_remove(&cmd->link);
117
[110d795]118 if (cmd->ictx)
119 free32(cmd->ictx);
120
121 free32(cmd);
122}
123
[2fa43d1]124static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
[110d795]125{
126 link_t *cmd_link = list_first(&hc->commands);
127
[548c123]128
129 usb_log_debug2("Searching TRB %lu...", phys);
130
[2fa43d1]131 while (cmd_link != NULL) {
132 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
133
[548c123]134 if (cmd->trb_phys == phys)
[2fa43d1]135 break;
136
137 cmd_link = list_next(cmd_link, &hc->commands);
138 }
139
[110d795]140 if (cmd_link != NULL) {
141 list_remove(cmd_link);
[9f5b613]142
[110d795]143 return list_get_instance(cmd_link, xhci_cmd_t, link);
144 }
145
146 return NULL;
147}
148
[481af21e]149static inline int ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
[c9c0e41]150{
[c058a388]151 assert(hc);
[c9c0e41]152 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
153 pio_write_32(&hc->db_arry[doorbell], v);
154 return EOK;
155}
156
[548c123]157static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
[481af21e]158{
[c058a388]159 assert(hc);
[548c123]160 assert(cmd);
161
162 list_append(&cmd->link, &hc->commands);
[c058a388]163
[548c123]164 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
[481af21e]165 ring_doorbell(hc, doorbell, target);
166
[548c123]167 usb_log_debug2("HC(%p): Sent command:", hc);
168 xhci_dump_trb(&cmd->trb);
[481af21e]169
170 return EOK;
171}
172
[3dc519f]173void xhci_stop_command_ring(xhci_hc_t *hc)
174{
175 assert(hc);
176
177 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
178
179 /**
180 * Note: There is a bug in qemu that checks CS only when CRCR_HI
181 * is written, this (and the read/write in abort) ensures
182 * the command rings stops.
183 */
184 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
185}
186
187void xhci_abort_command_ring(xhci_hc_t *hc)
188{
189 assert(hc);
190
191 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
192 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
193}
194
195void xhci_start_command_ring(xhci_hc_t *hc)
196{
197 assert(hc);
198
199 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
200 ring_doorbell(hc, 0, 0);
201}
202
[4fa5342]203static const char *trb_codes [] = {
204#define TRBC(t) [XHCI_TRBC_##t] = #t
205 TRBC(INVALID),
206 TRBC(SUCCESS),
207 TRBC(DATA_BUFFER_ERROR),
208 TRBC(BABBLE_DETECTED_ERROR),
209 TRBC(USB_TRANSACTION_ERROR),
210 TRBC(TRB_ERROR),
211 TRBC(STALL_ERROR),
212 TRBC(RESOURCE_ERROR),
213 TRBC(BANDWIDTH_ERROR),
214 TRBC(NO_SLOTS_ERROR),
215 TRBC(INVALID_STREAM_ERROR),
216 TRBC(SLOT_NOT_ENABLED_ERROR),
217 TRBC(EP_NOT_ENABLED_ERROR),
218 TRBC(SHORT_PACKET),
219 TRBC(RING_UNDERRUN),
220 TRBC(RING_OVERRUN),
221 TRBC(VF_EVENT_RING_FULL),
222 TRBC(PARAMETER_ERROR),
223 TRBC(BANDWIDTH_OVERRUN_ERROR),
224 TRBC(CONTEXT_STATE_ERROR),
225 TRBC(NO_PING_RESPONSE_ERROR),
226 TRBC(EVENT_RING_FULL_ERROR),
227 TRBC(INCOMPATIBLE_DEVICE_ERROR),
228 TRBC(MISSED_SERVICE_ERROR),
229 TRBC(COMMAND_RING_STOPPED),
230 TRBC(COMMAND_ABORTED),
231 TRBC(STOPPED),
232 TRBC(STOPPED_LENGTH_INVALID),
233 TRBC(STOPPED_SHORT_PACKET),
234 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
235 [30] = "<reserved>",
236 TRBC(ISOCH_BUFFER_OVERRUN),
237 TRBC(EVENT_LOST_ERROR),
238 TRBC(UNDEFINED_ERROR),
239 TRBC(INVALID_STREAM_ID_ERROR),
240 TRBC(SECONDARY_BANDWIDTH_ERROR),
241 TRBC(SPLIT_TRANSACTION_ERROR),
242 [XHCI_TRBC_MAX] = NULL
243#undef TRBC
244};
245
246static void report_error(int code)
247{
248 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
249 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
250 else
251 usb_log_error("Command resulted in reserved or vendor specific error.");
252}
253
[110d795]254int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c9c0e41]255{
[c058a388]256 assert(hc);
257
[548c123]258 xhci_trb_clean(&cmd->trb);
[c9c0e41]259
[548c123]260 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
[110d795]261
[548c123]262 return enqueue_command(hc, cmd, 0, 0);
[c9c0e41]263}
264
[110d795]265int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c9c0e41]266{
[c058a388]267 assert(hc);
268
[548c123]269 xhci_trb_clean(&cmd->trb);
[c9c0e41]270
[548c123]271 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
272 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
[110d795]273
[548c123]274 return enqueue_command(hc, cmd, 0, 0);
[5ac5eb1]275}
276
[110d795]277int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[5ac5eb1]278{
[c058a388]279 assert(hc);
[110d795]280 assert(cmd);
[c058a388]281
[548c123]282 xhci_trb_clean(&cmd->trb);
[5ac5eb1]283
[548c123]284 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
285 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[110d795]286
[548c123]287 return enqueue_command(hc, cmd, 0, 0);
[c9c0e41]288}
289
[110d795]290int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[8db42f7]291{
[c058a388]292 assert(hc);
[110d795]293 assert(cmd);
294 assert(cmd->ictx);
[c058a388]295
[8db42f7]296 /**
297 * TODO: Requirements for this command:
298 * dcbaa[slot_id] is properly sized and initialized
299 * ictx has valids slot context and endpoint 0, all
300 * other should be ignored at this point (see section 4.6.5).
301 */
[548c123]302 xhci_trb_clean(&cmd->trb);
[8db42f7]303
[110d795]304 uint64_t phys_addr = (uint64_t) addr_to_phys(cmd->ictx);
[548c123]305 TRB_SET_ICTX(cmd->trb, phys_addr);
[8db42f7]306
307 /**
308 * Note: According to section 6.4.3.4, we can set the 9th bit
309 * of the control field of the trb (BSR) to 1 and then the xHC
310 * will not issue the SET_ADDRESS request to the USB device.
311 * This can be used to provide compatibility with legacy USB devices
312 * that require their device descriptor to be read before such request.
313 */
[548c123]314 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
315 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[8db42f7]316
[548c123]317 return enqueue_command(hc, cmd, 0, 0);
[8db42f7]318}
319
[110d795]320int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[665bf3c]321{
[c058a388]322 assert(hc);
[110d795]323 assert(cmd);
324 assert(cmd->ictx);
[c058a388]325
[548c123]326 xhci_trb_clean(&cmd->trb);
[665bf3c]327
[110d795]328 uint64_t phys_addr = (uint64_t) addr_to_phys(cmd->ictx);
[548c123]329 TRB_SET_ICTX(cmd->trb, phys_addr);
[110d795]330
[548c123]331 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
332 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[665bf3c]333
[548c123]334 return enqueue_command(hc, cmd, 0, 0);
[665bf3c]335}
336
[110d795]337int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c9ce62ae]338{
[c058a388]339 assert(hc);
[110d795]340 assert(cmd);
341 assert(cmd->ictx);
[c058a388]342
[c9ce62ae]343 /**
344 * Note: All Drop Context flags of the input context shall be 0,
345 * all Add Context flags shall be initialize to indicate IDs
346 * of the contexts affected by the command.
347 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
348 */
[548c123]349 xhci_trb_clean(&cmd->trb);
[c9ce62ae]350
[110d795]351 uint64_t phys_addr = (uint64_t) addr_to_phys(cmd->ictx);
[548c123]352 TRB_SET_ICTX(cmd->trb, phys_addr);
[c9ce62ae]353
[548c123]354 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
355 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[110d795]356
[548c123]357 return enqueue_command(hc, cmd, 0, 0);
[c9ce62ae]358}
359
[110d795]360int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
[05aeee0e]361{
[c058a388]362 assert(hc);
[110d795]363 assert(cmd);
[c058a388]364
[05aeee0e]365 /**
366 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
367 * information about this flag.
368 */
[548c123]369 xhci_trb_clean(&cmd->trb);
[05aeee0e]370
[548c123]371 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
372 TRB_SET_TCS(cmd->trb, tcs);
373 TRB_SET_EP(cmd->trb, ep_id);
374 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[c9bec1c]375
[548c123]376 return enqueue_command(hc, cmd, 0, 0);
[05aeee0e]377}
378
[110d795]379int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
[05aeee0e]380{
[c058a388]381 assert(hc);
[110d795]382 assert(cmd);
[c058a388]383
[548c123]384 xhci_trb_clean(&cmd->trb);
[110d795]385
[548c123]386 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
387 TRB_SET_EP(cmd->trb, ep_id);
388 TRB_SET_SUSP(cmd->trb, susp);
389 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[05aeee0e]390
[548c123]391 return enqueue_command(hc, cmd, 0, 0);
[c058a388]392}
[05aeee0e]393
[0cabd10]394int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
395 uintptr_t dequeue_ptr, uint16_t stream_id,
396 uint32_t ep_id)
397{
398 assert(hc);
399 assert(cmd);
400
[548c123]401 xhci_trb_clean(&cmd->trb);
[0cabd10]402
[548c123]403 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
404 TRB_SET_EP(cmd->trb, ep_id);
405 TRB_SET_STREAM(cmd->trb, stream_id);
406 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
407 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
[0cabd10]408
409 /**
410 * TODO: Set DCS (see section 4.6.10).
411 */
412
[548c123]413 return enqueue_command(hc, cmd, 0, 0);
[0cabd10]414}
415
[110d795]416int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c058a388]417{
418 assert(hc);
[110d795]419 assert(cmd);
[c058a388]420
[548c123]421 xhci_trb_clean(&cmd->trb);
[c058a388]422
[548c123]423 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
424 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[c9bec1c]425
[548c123]426 return enqueue_command(hc, cmd, 0, 0);
[05aeee0e]427}
428
[f9e7fe8]429int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
430{
[110d795]431 // TODO: Update dequeue ptrs.
[c058a388]432 assert(hc);
433 assert(trb);
434
[5ac5eb1]435 usb_log_debug("HC(%p) Command completed.", hc);
[f9e7fe8]436
[5ac5eb1]437 int code;
[2fa43d1]438 uint64_t phys;
[110d795]439 xhci_cmd_t *command;
[f711f06]440
[1b78a7c1]441 code = TRB_GET_CODE(*trb);
442 phys = TRB_GET_PHYS(*trb);;
[2fa43d1]443 command = get_command(hc, phys);
444 if (command == NULL) {
445 // TODO: STOP & ABORT may not have command structs in the list!
446 usb_log_error("No command struct for this completion event");
447
448 if (code != XHCI_TRBC_SUCCESS)
449 report_error(code);
450
451 return EOK;
452 }
[110d795]453
454 command->status = code;
[1b78a7c1]455 command->slot_id = TRB_GET_SLOT(*trb);
[110d795]456
[548c123]457 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
458 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
[665bf3c]459 if (code != XHCI_TRBC_SUCCESS) {
[4fa5342]460 report_error(code);
[548c123]461 xhci_dump_trb(&command->trb);
[665bf3c]462 }
463 }
[c362127]464
[548c123]465 switch (TRB_TYPE(command->trb)) {
[c362127]466 case XHCI_TRB_TYPE_NO_OP_CMD:
[9f5b613]467 assert(code == XHCI_TRBC_TRB_ERROR);
[110d795]468 break;
[c362127]469 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
[110d795]470 break;
[5ac5eb1]471 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
[110d795]472 break;
[8db42f7]473 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
[110d795]474 break;
[665bf3c]475 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
[110d795]476 break;
[c9ce62ae]477 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
[110d795]478 break;
[05aeee0e]479 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
[110d795]480 break;
[05aeee0e]481 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
482 // Note: If the endpoint was in the middle of a transfer, then the xHC
483 // will add a Transfer TRB before the Event TRB, research that and
484 // handle it appropriately!
[110d795]485 break;
[c058a388]486 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
[110d795]487 break;
[c362127]488 default:
[548c123]489 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
[110d795]490
491 command->completed = true;
[665bf3c]492 return ENAK;
[f711f06]493 }
[110d795]494
495 command->completed = true;
496
[c4d4fa2]497 if (!command->has_owner) {
[eff60ca]498 usb_log_debug2("Command has no owner, deallocating.");
[110d795]499 xhci_free_command(command);
[c4d4fa2]500 } else {
[eff60ca]501 usb_log_debug2("Command has owner, don't forget to deallocate!");
[c4d4fa2]502 }
[110d795]503
504 return EOK;
[f9e7fe8]505}
[c9c0e41]506
507
508/**
509 * @}
510 */
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