| [c9c0e41] | 1 | /*
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| 2 | * Copyright (c) 2017 Jaroslav Jindrak
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Command sending functions.
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| 34 | */
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| 35 |
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| 36 | #include <errno.h>
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| 37 | #include <str_error.h>
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| 38 | #include <usb/debug.h>
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| 39 | #include <usb/host/utils/malloc32.h>
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| 40 | #include "commands.h"
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| 41 | #include "debug.h"
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| 42 | #include "hc.h"
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| [8db42f7] | 43 | #include "hw_struct/context.h"
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| [c9c0e41] | 44 | #include "hw_struct/trb.h"
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| 45 |
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| [1b78a7c1] | 46 | #define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
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| 47 | #define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
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| 48 | #define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
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| [0cabd10] | 49 | #define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
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| [1b78a7c1] | 50 | #define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
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| 51 | #define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
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| [60af4cdb] | 52 | #define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
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| [1b78a7c1] | 53 |
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| [0cabd10] | 54 | /**
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| 55 | * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
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| 56 | */
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| 57 | #define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
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| [548c123] | 58 | #define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
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| [1b78a7c1] | 59 |
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| 60 | #define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
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| 61 | #define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
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| 62 | #define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
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| 63 |
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| [110d795] | 64 | int xhci_init_commands(xhci_hc_t *hc)
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| 65 | {
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| 66 | assert(hc);
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| 67 |
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| 68 | list_initialize(&hc->commands);
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| 69 | return EOK;
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| 70 | }
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| 71 |
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| [c46c356] | 72 | void xhci_fini_commands(xhci_hc_t *hc)
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| 73 | {
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| 74 | // Note: Untested.
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| 75 | assert(hc);
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| 76 | }
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| 77 |
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| [2896ff6] | 78 | int xhci_cmd_wait(xhci_cmd_t *cmd)
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| [110d795] | 79 | {
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| [2896ff6] | 80 | const suseconds_t timeout = 1000000;
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| [4688350b] | 81 | int rv = EOK;
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| 82 |
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| 83 | fibril_mutex_lock(&cmd->completed_mtx);
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| [110d795] | 84 | while (!cmd->completed) {
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| [4688350b] | 85 | usb_log_debug2("Waiting for event completion: going to sleep.");
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| 86 | rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
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| [110d795] | 87 |
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| [4688350b] | 88 | usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
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| 89 | if (rv == ETIMEOUT)
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| 90 | break;
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| [110d795] | 91 | }
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| [1f76b7d] | 92 | fibril_mutex_unlock(&cmd->completed_mtx);
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| [110d795] | 93 |
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| [4688350b] | 94 | return rv;
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| [110d795] | 95 | }
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| 96 |
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| [04df063] | 97 | xhci_cmd_t *xhci_cmd_alloc(void)
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| [110d795] | 98 | {
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| [078e0e6] | 99 | xhci_cmd_t *cmd = malloc(sizeof(xhci_cmd_t));
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| [4688350b] | 100 | xhci_cmd_init(cmd);
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| [04df063] | 101 |
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| 102 | usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
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| [4688350b] | 103 | return cmd;
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| 104 | }
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| 105 |
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| 106 | void xhci_cmd_init(xhci_cmd_t *cmd)
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| 107 | {
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| 108 | memset(cmd, 0, sizeof(*cmd));
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| [110d795] | 109 |
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| 110 | link_initialize(&cmd->link);
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| 111 |
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| [4688350b] | 112 | fibril_mutex_initialize(&cmd->completed_mtx);
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| 113 | fibril_condvar_initialize(&cmd->completed_cv);
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| [110d795] | 114 | }
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| 115 |
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| [04df063] | 116 | void xhci_cmd_fini(xhci_cmd_t *cmd)
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| [110d795] | 117 | {
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| [9304b66] | 118 | list_remove(&cmd->link);
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| [04df063] | 119 | }
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| [9304b66] | 120 |
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| [04df063] | 121 | void xhci_cmd_free(xhci_cmd_t *cmd)
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| 122 | {
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| 123 | xhci_cmd_fini(cmd);
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| [078e0e6] | 124 | free(cmd);
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| [110d795] | 125 | }
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| 126 |
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| [2fa43d1] | 127 | static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
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| [110d795] | 128 | {
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| 129 | link_t *cmd_link = list_first(&hc->commands);
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| 130 |
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| [2fa43d1] | 131 | while (cmd_link != NULL) {
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| 132 | xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
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| 133 |
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| [548c123] | 134 | if (cmd->trb_phys == phys)
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| [2fa43d1] | 135 | break;
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| 136 |
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| 137 | cmd_link = list_next(cmd_link, &hc->commands);
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| 138 | }
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| 139 |
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| [110d795] | 140 | if (cmd_link != NULL) {
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| 141 | list_remove(cmd_link);
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| [9f5b613] | 142 |
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| [110d795] | 143 | return list_get_instance(cmd_link, xhci_cmd_t, link);
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| 144 | }
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| 145 |
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| 146 | return NULL;
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| 147 | }
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| 148 |
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| [548c123] | 149 | static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
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| [481af21e] | 150 | {
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| [c058a388] | 151 | assert(hc);
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| [548c123] | 152 | assert(cmd);
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| 153 |
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| 154 | list_append(&cmd->link, &hc->commands);
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| [c058a388] | 155 |
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| [548c123] | 156 | xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
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| [a0be5d0] | 157 | hc_ring_doorbell(hc, doorbell, target);
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| [481af21e] | 158 |
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| [548c123] | 159 | usb_log_debug2("HC(%p): Sent command:", hc);
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| 160 | xhci_dump_trb(&cmd->trb);
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| [481af21e] | 161 |
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| 162 | return EOK;
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| 163 | }
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| 164 |
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| [3dc519f] | 165 | void xhci_stop_command_ring(xhci_hc_t *hc)
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| 166 | {
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| 167 | assert(hc);
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| 168 |
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| 169 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
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| 170 |
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| 171 | /**
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| 172 | * Note: There is a bug in qemu that checks CS only when CRCR_HI
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| 173 | * is written, this (and the read/write in abort) ensures
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| 174 | * the command rings stops.
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| 175 | */
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| 176 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
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| 177 | }
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| 178 |
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| 179 | void xhci_abort_command_ring(xhci_hc_t *hc)
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| 180 | {
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| 181 | assert(hc);
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| 182 |
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| 183 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
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| 184 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
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| 185 | }
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| 186 |
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| 187 | void xhci_start_command_ring(xhci_hc_t *hc)
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| 188 | {
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| 189 | assert(hc);
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| 190 |
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| 191 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
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| [a0be5d0] | 192 | hc_ring_doorbell(hc, 0, 0);
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| [3dc519f] | 193 | }
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| 194 |
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| [4fa5342] | 195 | static const char *trb_codes [] = {
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| 196 | #define TRBC(t) [XHCI_TRBC_##t] = #t
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| 197 | TRBC(INVALID),
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| 198 | TRBC(SUCCESS),
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| 199 | TRBC(DATA_BUFFER_ERROR),
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| 200 | TRBC(BABBLE_DETECTED_ERROR),
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| 201 | TRBC(USB_TRANSACTION_ERROR),
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| 202 | TRBC(TRB_ERROR),
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| 203 | TRBC(STALL_ERROR),
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| 204 | TRBC(RESOURCE_ERROR),
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| 205 | TRBC(BANDWIDTH_ERROR),
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| 206 | TRBC(NO_SLOTS_ERROR),
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| 207 | TRBC(INVALID_STREAM_ERROR),
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| 208 | TRBC(SLOT_NOT_ENABLED_ERROR),
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| 209 | TRBC(EP_NOT_ENABLED_ERROR),
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| 210 | TRBC(SHORT_PACKET),
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| 211 | TRBC(RING_UNDERRUN),
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| 212 | TRBC(RING_OVERRUN),
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| 213 | TRBC(VF_EVENT_RING_FULL),
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| 214 | TRBC(PARAMETER_ERROR),
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| 215 | TRBC(BANDWIDTH_OVERRUN_ERROR),
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| 216 | TRBC(CONTEXT_STATE_ERROR),
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| 217 | TRBC(NO_PING_RESPONSE_ERROR),
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| 218 | TRBC(EVENT_RING_FULL_ERROR),
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| 219 | TRBC(INCOMPATIBLE_DEVICE_ERROR),
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| 220 | TRBC(MISSED_SERVICE_ERROR),
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| 221 | TRBC(COMMAND_RING_STOPPED),
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| 222 | TRBC(COMMAND_ABORTED),
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| 223 | TRBC(STOPPED),
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| 224 | TRBC(STOPPED_LENGTH_INVALID),
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| 225 | TRBC(STOPPED_SHORT_PACKET),
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| 226 | TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
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| 227 | [30] = "<reserved>",
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| 228 | TRBC(ISOCH_BUFFER_OVERRUN),
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| 229 | TRBC(EVENT_LOST_ERROR),
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| 230 | TRBC(UNDEFINED_ERROR),
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| 231 | TRBC(INVALID_STREAM_ID_ERROR),
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| 232 | TRBC(SECONDARY_BANDWIDTH_ERROR),
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| 233 | TRBC(SPLIT_TRANSACTION_ERROR),
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| 234 | [XHCI_TRBC_MAX] = NULL
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| 235 | #undef TRBC
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| 236 | };
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| 237 |
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| 238 | static void report_error(int code)
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| 239 | {
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| 240 | if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
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| 241 | usb_log_error("Command resulted in error: %s.", trb_codes[code]);
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| 242 | else
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| 243 | usb_log_error("Command resulted in reserved or vendor specific error.");
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| 244 | }
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| 245 |
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| [110d795] | 246 | int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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| [c9c0e41] | 247 | {
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| [c058a388] | 248 | assert(hc);
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| 249 |
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| [548c123] | 250 | xhci_trb_clean(&cmd->trb);
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| [c9c0e41] | 251 |
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| [548c123] | 252 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
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| [110d795] | 253 |
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| [548c123] | 254 | return enqueue_command(hc, cmd, 0, 0);
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| [c9c0e41] | 255 | }
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| 256 |
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| [110d795] | 257 | int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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| [c9c0e41] | 258 | {
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| [c058a388] | 259 | assert(hc);
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| 260 |
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| [548c123] | 261 | xhci_trb_clean(&cmd->trb);
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| [c9c0e41] | 262 |
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| [548c123] | 263 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
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| 264 | cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
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| [110d795] | 265 |
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| [548c123] | 266 | return enqueue_command(hc, cmd, 0, 0);
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| [5ac5eb1] | 267 | }
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| 268 |
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| [110d795] | 269 | int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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| [5ac5eb1] | 270 | {
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| [c058a388] | 271 | assert(hc);
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| [110d795] | 272 | assert(cmd);
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| [c058a388] | 273 |
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| [548c123] | 274 | xhci_trb_clean(&cmd->trb);
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| [5ac5eb1] | 275 |
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| [548c123] | 276 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
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| 277 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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| [110d795] | 278 |
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| [548c123] | 279 | return enqueue_command(hc, cmd, 0, 0);
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| [c9c0e41] | 280 | }
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| 281 |
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| [04df063] | 282 | int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
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| [8db42f7] | 283 | {
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| [c058a388] | 284 | assert(hc);
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| [110d795] | 285 | assert(cmd);
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| [04df063] | 286 | assert(ictx);
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| [c058a388] | 287 |
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| [8db42f7] | 288 | /**
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| 289 | * TODO: Requirements for this command:
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| 290 | * dcbaa[slot_id] is properly sized and initialized
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| 291 | * ictx has valids slot context and endpoint 0, all
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| 292 | * other should be ignored at this point (see section 4.6.5).
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| 293 | */
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| [04df063] | 294 |
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| [548c123] | 295 | xhci_trb_clean(&cmd->trb);
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| [8db42f7] | 296 |
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| [04df063] | 297 | uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
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| [548c123] | 298 | TRB_SET_ICTX(cmd->trb, phys_addr);
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| [8db42f7] | 299 |
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| 300 | /**
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| 301 | * Note: According to section 6.4.3.4, we can set the 9th bit
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| 302 | * of the control field of the trb (BSR) to 1 and then the xHC
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| 303 | * will not issue the SET_ADDRESS request to the USB device.
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| 304 | * This can be used to provide compatibility with legacy USB devices
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| 305 | * that require their device descriptor to be read before such request.
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| 306 | */
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| [548c123] | 307 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
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| 308 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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| [8db42f7] | 309 |
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| [548c123] | 310 | return enqueue_command(hc, cmd, 0, 0);
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| [8db42f7] | 311 | }
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| 312 |
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| [04df063] | 313 | int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
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| [665bf3c] | 314 | {
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| [c058a388] | 315 | assert(hc);
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| [110d795] | 316 | assert(cmd);
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| [04df063] | 317 | assert(ictx);
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| [c058a388] | 318 |
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| [548c123] | 319 | xhci_trb_clean(&cmd->trb);
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| [665bf3c] | 320 |
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| [04df063] | 321 | uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
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| [548c123] | 322 | TRB_SET_ICTX(cmd->trb, phys_addr);
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| [110d795] | 323 |
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| [548c123] | 324 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
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| 325 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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| [665bf3c] | 326 |
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| [548c123] | 327 | return enqueue_command(hc, cmd, 0, 0);
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| [665bf3c] | 328 | }
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| 329 |
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| [04df063] | 330 | int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
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| [c9ce62ae] | 331 | {
|
|---|
| [c058a388] | 332 | assert(hc);
|
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| [110d795] | 333 | assert(cmd);
|
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| [04df063] | 334 | assert(ictx);
|
|---|
| [c058a388] | 335 |
|
|---|
| [c9ce62ae] | 336 | /**
|
|---|
| 337 | * Note: All Drop Context flags of the input context shall be 0,
|
|---|
| 338 | * all Add Context flags shall be initialize to indicate IDs
|
|---|
| 339 | * of the contexts affected by the command.
|
|---|
| 340 | * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
|
|---|
| 341 | */
|
|---|
| [548c123] | 342 | xhci_trb_clean(&cmd->trb);
|
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| [c9ce62ae] | 343 |
|
|---|
| [04df063] | 344 | uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
|
|---|
| [548c123] | 345 | TRB_SET_ICTX(cmd->trb, phys_addr);
|
|---|
| [c9ce62ae] | 346 |
|
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| [548c123] | 347 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
|
|---|
| 348 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
|---|
| [110d795] | 349 |
|
|---|
| [548c123] | 350 | return enqueue_command(hc, cmd, 0, 0);
|
|---|
| [c9ce62ae] | 351 | }
|
|---|
| 352 |
|
|---|
| [110d795] | 353 | int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
|
|---|
| [05aeee0e] | 354 | {
|
|---|
| [c058a388] | 355 | assert(hc);
|
|---|
| [110d795] | 356 | assert(cmd);
|
|---|
| [c058a388] | 357 |
|
|---|
| [05aeee0e] | 358 | /**
|
|---|
| 359 | * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
|
|---|
| 360 | * information about this flag.
|
|---|
| 361 | */
|
|---|
| [548c123] | 362 | xhci_trb_clean(&cmd->trb);
|
|---|
| [05aeee0e] | 363 |
|
|---|
| [548c123] | 364 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
|
|---|
| 365 | TRB_SET_TCS(cmd->trb, tcs);
|
|---|
| 366 | TRB_SET_EP(cmd->trb, ep_id);
|
|---|
| 367 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
|---|
| [c9bec1c] | 368 |
|
|---|
| [548c123] | 369 | return enqueue_command(hc, cmd, 0, 0);
|
|---|
| [05aeee0e] | 370 | }
|
|---|
| 371 |
|
|---|
| [110d795] | 372 | int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
|
|---|
| [05aeee0e] | 373 | {
|
|---|
| [c058a388] | 374 | assert(hc);
|
|---|
| [110d795] | 375 | assert(cmd);
|
|---|
| [c058a388] | 376 |
|
|---|
| [548c123] | 377 | xhci_trb_clean(&cmd->trb);
|
|---|
| [110d795] | 378 |
|
|---|
| [548c123] | 379 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
|
|---|
| 380 | TRB_SET_EP(cmd->trb, ep_id);
|
|---|
| 381 | TRB_SET_SUSP(cmd->trb, susp);
|
|---|
| 382 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
|---|
| [05aeee0e] | 383 |
|
|---|
| [548c123] | 384 | return enqueue_command(hc, cmd, 0, 0);
|
|---|
| [c058a388] | 385 | }
|
|---|
| [05aeee0e] | 386 |
|
|---|
| [0cabd10] | 387 | int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
|
|---|
| 388 | uintptr_t dequeue_ptr, uint16_t stream_id,
|
|---|
| 389 | uint32_t ep_id)
|
|---|
| 390 | {
|
|---|
| 391 | assert(hc);
|
|---|
| 392 | assert(cmd);
|
|---|
| 393 |
|
|---|
| [548c123] | 394 | xhci_trb_clean(&cmd->trb);
|
|---|
| [0cabd10] | 395 |
|
|---|
| [548c123] | 396 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
|
|---|
| 397 | TRB_SET_EP(cmd->trb, ep_id);
|
|---|
| 398 | TRB_SET_STREAM(cmd->trb, stream_id);
|
|---|
| 399 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
|---|
| 400 | TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
|
|---|
| [0cabd10] | 401 |
|
|---|
| 402 | /**
|
|---|
| 403 | * TODO: Set DCS (see section 4.6.10).
|
|---|
| 404 | */
|
|---|
| 405 |
|
|---|
| [548c123] | 406 | return enqueue_command(hc, cmd, 0, 0);
|
|---|
| [0cabd10] | 407 | }
|
|---|
| 408 |
|
|---|
| [110d795] | 409 | int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
|---|
| [c058a388] | 410 | {
|
|---|
| 411 | assert(hc);
|
|---|
| [110d795] | 412 | assert(cmd);
|
|---|
| [c058a388] | 413 |
|
|---|
| [548c123] | 414 | xhci_trb_clean(&cmd->trb);
|
|---|
| [c058a388] | 415 |
|
|---|
| [548c123] | 416 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
|
|---|
| 417 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
|---|
| [c9bec1c] | 418 |
|
|---|
| [548c123] | 419 | return enqueue_command(hc, cmd, 0, 0);
|
|---|
| [05aeee0e] | 420 | }
|
|---|
| 421 |
|
|---|
| [60af4cdb] | 422 | int xhci_get_port_bandwidth_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
|
|---|
| 423 | xhci_port_bandwidth_ctx_t *ctx, uint8_t device_speed)
|
|---|
| 424 | {
|
|---|
| 425 | assert(hc);
|
|---|
| 426 | assert(cmd);
|
|---|
| 427 |
|
|---|
| 428 | xhci_trb_clean(&cmd->trb);
|
|---|
| 429 |
|
|---|
| 430 | uint64_t phys_addr = (uint64_t) addr_to_phys(ctx);
|
|---|
| 431 | TRB_SET_ICTX(cmd->trb, phys_addr);
|
|---|
| 432 |
|
|---|
| 433 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
|
|---|
| 434 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
|---|
| 435 | TRB_SET_DEV_SPEED(cmd->trb, device_speed);
|
|---|
| 436 |
|
|---|
| 437 | return enqueue_command(hc, cmd, 0, 0);
|
|---|
| 438 | }
|
|---|
| 439 |
|
|---|
| [f9e7fe8] | 440 | int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
|
|---|
| 441 | {
|
|---|
| [110d795] | 442 | // TODO: Update dequeue ptrs.
|
|---|
| [c058a388] | 443 | assert(hc);
|
|---|
| 444 | assert(trb);
|
|---|
| 445 |
|
|---|
| [5ac5eb1] | 446 | usb_log_debug("HC(%p) Command completed.", hc);
|
|---|
| [f9e7fe8] | 447 |
|
|---|
| [5ac5eb1] | 448 | int code;
|
|---|
| [2fa43d1] | 449 | uint64_t phys;
|
|---|
| [110d795] | 450 | xhci_cmd_t *command;
|
|---|
| [f711f06] | 451 |
|
|---|
| [1b78a7c1] | 452 | code = TRB_GET_CODE(*trb);
|
|---|
| 453 | phys = TRB_GET_PHYS(*trb);;
|
|---|
| [2fa43d1] | 454 | command = get_command(hc, phys);
|
|---|
| 455 | if (command == NULL) {
|
|---|
| 456 | // TODO: STOP & ABORT may not have command structs in the list!
|
|---|
| [04df063] | 457 | usb_log_debug("No command struct for this completion event found.");
|
|---|
| [2fa43d1] | 458 |
|
|---|
| 459 | if (code != XHCI_TRBC_SUCCESS)
|
|---|
| 460 | report_error(code);
|
|---|
| 461 |
|
|---|
| 462 | return EOK;
|
|---|
| 463 | }
|
|---|
| [110d795] | 464 |
|
|---|
| 465 | command->status = code;
|
|---|
| [1b78a7c1] | 466 | command->slot_id = TRB_GET_SLOT(*trb);
|
|---|
| [110d795] | 467 |
|
|---|
| [548c123] | 468 | usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
|
|---|
| 469 | if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
|
|---|
| [665bf3c] | 470 | if (code != XHCI_TRBC_SUCCESS) {
|
|---|
| [4fa5342] | 471 | report_error(code);
|
|---|
| [548c123] | 472 | xhci_dump_trb(&command->trb);
|
|---|
| [665bf3c] | 473 | }
|
|---|
| 474 | }
|
|---|
| [c362127] | 475 |
|
|---|
| [548c123] | 476 | switch (TRB_TYPE(command->trb)) {
|
|---|
| [c362127] | 477 | case XHCI_TRB_TYPE_NO_OP_CMD:
|
|---|
| [9f5b613] | 478 | assert(code == XHCI_TRBC_TRB_ERROR);
|
|---|
| [110d795] | 479 | break;
|
|---|
| [c362127] | 480 | case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
|
|---|
| [110d795] | 481 | break;
|
|---|
| [5ac5eb1] | 482 | case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
|
|---|
| [110d795] | 483 | break;
|
|---|
| [8db42f7] | 484 | case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
|
|---|
| [110d795] | 485 | break;
|
|---|
| [665bf3c] | 486 | case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
|
|---|
| [110d795] | 487 | break;
|
|---|
| [c9ce62ae] | 488 | case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
|
|---|
| [110d795] | 489 | break;
|
|---|
| [05aeee0e] | 490 | case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
|
|---|
| [110d795] | 491 | break;
|
|---|
| [05aeee0e] | 492 | case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
|
|---|
| 493 | // Note: If the endpoint was in the middle of a transfer, then the xHC
|
|---|
| 494 | // will add a Transfer TRB before the Event TRB, research that and
|
|---|
| 495 | // handle it appropriately!
|
|---|
| [110d795] | 496 | break;
|
|---|
| [c058a388] | 497 | case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
|
|---|
| [110d795] | 498 | break;
|
|---|
| [c362127] | 499 | default:
|
|---|
| [548c123] | 500 | usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
|
|---|
| [110d795] | 501 |
|
|---|
| 502 | command->completed = true;
|
|---|
| [665bf3c] | 503 | return ENAK;
|
|---|
| [f711f06] | 504 | }
|
|---|
| [110d795] | 505 |
|
|---|
| [4688350b] | 506 | fibril_mutex_lock(&command->completed_mtx);
|
|---|
| [110d795] | 507 | command->completed = true;
|
|---|
| [4688350b] | 508 | fibril_condvar_broadcast(&command->completed_cv);
|
|---|
| 509 | fibril_mutex_unlock(&command->completed_mtx);
|
|---|
| 510 |
|
|---|
| [110d795] | 511 | return EOK;
|
|---|
| [f9e7fe8] | 512 | }
|
|---|
| [c9c0e41] | 513 |
|
|---|
| 514 |
|
|---|
| 515 | /**
|
|---|
| 516 | * @}
|
|---|
| 517 | */
|
|---|