source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 1a9a72a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 1a9a72a was 60af4cdb, checked in by Michal Staruch <salmelu@…>, 8 years ago

Added get port bandwidth command

  • Property mode set to 100644
File size: 13.4 KB
RevLine 
[c9c0e41]1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
[8db42f7]43#include "hw_struct/context.h"
[c9c0e41]44#include "hw_struct/trb.h"
45
[1b78a7c1]46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
[0cabd10]49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
[1b78a7c1]50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
[60af4cdb]52#define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
[1b78a7c1]53
[0cabd10]54/**
55 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
56 */
57#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
[548c123]58#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
[1b78a7c1]59
60#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
61#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
62#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
63
[110d795]64int xhci_init_commands(xhci_hc_t *hc)
65{
66 assert(hc);
67
68 list_initialize(&hc->commands);
69 return EOK;
70}
71
[c46c356]72void xhci_fini_commands(xhci_hc_t *hc)
73{
74 // Note: Untested.
75 assert(hc);
76}
77
[04df063]78int xhci_cmd_wait(xhci_cmd_t *cmd, suseconds_t timeout)
[110d795]79{
[4688350b]80 int rv = EOK;
81
82 fibril_mutex_lock(&cmd->completed_mtx);
[110d795]83 while (!cmd->completed) {
[4688350b]84 usb_log_debug2("Waiting for event completion: going to sleep.");
85 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
[110d795]86
[4688350b]87 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
88 if (rv == ETIMEOUT)
89 break;
[110d795]90 }
[1f76b7d]91 fibril_mutex_unlock(&cmd->completed_mtx);
[110d795]92
[4688350b]93 return rv;
[110d795]94}
95
[04df063]96xhci_cmd_t *xhci_cmd_alloc(void)
[110d795]97{
[078e0e6]98 xhci_cmd_t *cmd = malloc(sizeof(xhci_cmd_t));
[4688350b]99 xhci_cmd_init(cmd);
[04df063]100
101 usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
[4688350b]102 return cmd;
103}
104
105void xhci_cmd_init(xhci_cmd_t *cmd)
106{
107 memset(cmd, 0, sizeof(*cmd));
[110d795]108
109 link_initialize(&cmd->link);
110
[4688350b]111 fibril_mutex_initialize(&cmd->completed_mtx);
112 fibril_condvar_initialize(&cmd->completed_cv);
[110d795]113}
114
[04df063]115void xhci_cmd_fini(xhci_cmd_t *cmd)
[110d795]116{
[9304b66]117 list_remove(&cmd->link);
[04df063]118}
[9304b66]119
[04df063]120void xhci_cmd_free(xhci_cmd_t *cmd)
121{
122 xhci_cmd_fini(cmd);
[078e0e6]123 free(cmd);
[110d795]124}
125
[2fa43d1]126static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
[110d795]127{
128 link_t *cmd_link = list_first(&hc->commands);
129
[2fa43d1]130 while (cmd_link != NULL) {
131 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
132
[548c123]133 if (cmd->trb_phys == phys)
[2fa43d1]134 break;
135
136 cmd_link = list_next(cmd_link, &hc->commands);
137 }
138
[110d795]139 if (cmd_link != NULL) {
140 list_remove(cmd_link);
[9f5b613]141
[110d795]142 return list_get_instance(cmd_link, xhci_cmd_t, link);
143 }
144
145 return NULL;
146}
147
[548c123]148static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
[481af21e]149{
[c058a388]150 assert(hc);
[548c123]151 assert(cmd);
152
153 list_append(&cmd->link, &hc->commands);
[c058a388]154
[548c123]155 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
[a0be5d0]156 hc_ring_doorbell(hc, doorbell, target);
[481af21e]157
[548c123]158 usb_log_debug2("HC(%p): Sent command:", hc);
159 xhci_dump_trb(&cmd->trb);
[481af21e]160
161 return EOK;
162}
163
[3dc519f]164void xhci_stop_command_ring(xhci_hc_t *hc)
165{
166 assert(hc);
167
168 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
169
170 /**
171 * Note: There is a bug in qemu that checks CS only when CRCR_HI
172 * is written, this (and the read/write in abort) ensures
173 * the command rings stops.
174 */
175 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
176}
177
178void xhci_abort_command_ring(xhci_hc_t *hc)
179{
180 assert(hc);
181
182 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
183 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
184}
185
186void xhci_start_command_ring(xhci_hc_t *hc)
187{
188 assert(hc);
189
190 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
[a0be5d0]191 hc_ring_doorbell(hc, 0, 0);
[3dc519f]192}
193
[4fa5342]194static const char *trb_codes [] = {
195#define TRBC(t) [XHCI_TRBC_##t] = #t
196 TRBC(INVALID),
197 TRBC(SUCCESS),
198 TRBC(DATA_BUFFER_ERROR),
199 TRBC(BABBLE_DETECTED_ERROR),
200 TRBC(USB_TRANSACTION_ERROR),
201 TRBC(TRB_ERROR),
202 TRBC(STALL_ERROR),
203 TRBC(RESOURCE_ERROR),
204 TRBC(BANDWIDTH_ERROR),
205 TRBC(NO_SLOTS_ERROR),
206 TRBC(INVALID_STREAM_ERROR),
207 TRBC(SLOT_NOT_ENABLED_ERROR),
208 TRBC(EP_NOT_ENABLED_ERROR),
209 TRBC(SHORT_PACKET),
210 TRBC(RING_UNDERRUN),
211 TRBC(RING_OVERRUN),
212 TRBC(VF_EVENT_RING_FULL),
213 TRBC(PARAMETER_ERROR),
214 TRBC(BANDWIDTH_OVERRUN_ERROR),
215 TRBC(CONTEXT_STATE_ERROR),
216 TRBC(NO_PING_RESPONSE_ERROR),
217 TRBC(EVENT_RING_FULL_ERROR),
218 TRBC(INCOMPATIBLE_DEVICE_ERROR),
219 TRBC(MISSED_SERVICE_ERROR),
220 TRBC(COMMAND_RING_STOPPED),
221 TRBC(COMMAND_ABORTED),
222 TRBC(STOPPED),
223 TRBC(STOPPED_LENGTH_INVALID),
224 TRBC(STOPPED_SHORT_PACKET),
225 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
226 [30] = "<reserved>",
227 TRBC(ISOCH_BUFFER_OVERRUN),
228 TRBC(EVENT_LOST_ERROR),
229 TRBC(UNDEFINED_ERROR),
230 TRBC(INVALID_STREAM_ID_ERROR),
231 TRBC(SECONDARY_BANDWIDTH_ERROR),
232 TRBC(SPLIT_TRANSACTION_ERROR),
233 [XHCI_TRBC_MAX] = NULL
234#undef TRBC
235};
236
237static void report_error(int code)
238{
239 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
240 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
241 else
242 usb_log_error("Command resulted in reserved or vendor specific error.");
243}
244
[110d795]245int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c9c0e41]246{
[c058a388]247 assert(hc);
248
[548c123]249 xhci_trb_clean(&cmd->trb);
[c9c0e41]250
[548c123]251 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
[110d795]252
[548c123]253 return enqueue_command(hc, cmd, 0, 0);
[c9c0e41]254}
255
[110d795]256int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c9c0e41]257{
[c058a388]258 assert(hc);
259
[548c123]260 xhci_trb_clean(&cmd->trb);
[c9c0e41]261
[548c123]262 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
263 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
[110d795]264
[548c123]265 return enqueue_command(hc, cmd, 0, 0);
[5ac5eb1]266}
267
[110d795]268int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[5ac5eb1]269{
[c058a388]270 assert(hc);
[110d795]271 assert(cmd);
[c058a388]272
[548c123]273 xhci_trb_clean(&cmd->trb);
[5ac5eb1]274
[548c123]275 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
276 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[110d795]277
[548c123]278 return enqueue_command(hc, cmd, 0, 0);
[c9c0e41]279}
280
[04df063]281int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
[8db42f7]282{
[c058a388]283 assert(hc);
[110d795]284 assert(cmd);
[04df063]285 assert(ictx);
[c058a388]286
[8db42f7]287 /**
288 * TODO: Requirements for this command:
289 * dcbaa[slot_id] is properly sized and initialized
290 * ictx has valids slot context and endpoint 0, all
291 * other should be ignored at this point (see section 4.6.5).
292 */
[04df063]293
[548c123]294 xhci_trb_clean(&cmd->trb);
[8db42f7]295
[04df063]296 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
[548c123]297 TRB_SET_ICTX(cmd->trb, phys_addr);
[8db42f7]298
299 /**
300 * Note: According to section 6.4.3.4, we can set the 9th bit
301 * of the control field of the trb (BSR) to 1 and then the xHC
302 * will not issue the SET_ADDRESS request to the USB device.
303 * This can be used to provide compatibility with legacy USB devices
304 * that require their device descriptor to be read before such request.
305 */
[548c123]306 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
307 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[8db42f7]308
[548c123]309 return enqueue_command(hc, cmd, 0, 0);
[8db42f7]310}
311
[04df063]312int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
[665bf3c]313{
[c058a388]314 assert(hc);
[110d795]315 assert(cmd);
[04df063]316 assert(ictx);
[c058a388]317
[548c123]318 xhci_trb_clean(&cmd->trb);
[665bf3c]319
[04df063]320 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
[548c123]321 TRB_SET_ICTX(cmd->trb, phys_addr);
[110d795]322
[548c123]323 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
324 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[665bf3c]325
[548c123]326 return enqueue_command(hc, cmd, 0, 0);
[665bf3c]327}
328
[04df063]329int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
[c9ce62ae]330{
[c058a388]331 assert(hc);
[110d795]332 assert(cmd);
[04df063]333 assert(ictx);
[c058a388]334
[c9ce62ae]335 /**
336 * Note: All Drop Context flags of the input context shall be 0,
337 * all Add Context flags shall be initialize to indicate IDs
338 * of the contexts affected by the command.
339 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
340 */
[548c123]341 xhci_trb_clean(&cmd->trb);
[c9ce62ae]342
[04df063]343 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
[548c123]344 TRB_SET_ICTX(cmd->trb, phys_addr);
[c9ce62ae]345
[548c123]346 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
347 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[110d795]348
[548c123]349 return enqueue_command(hc, cmd, 0, 0);
[c9ce62ae]350}
351
[110d795]352int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
[05aeee0e]353{
[c058a388]354 assert(hc);
[110d795]355 assert(cmd);
[c058a388]356
[05aeee0e]357 /**
358 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
359 * information about this flag.
360 */
[548c123]361 xhci_trb_clean(&cmd->trb);
[05aeee0e]362
[548c123]363 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
364 TRB_SET_TCS(cmd->trb, tcs);
365 TRB_SET_EP(cmd->trb, ep_id);
366 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[c9bec1c]367
[548c123]368 return enqueue_command(hc, cmd, 0, 0);
[05aeee0e]369}
370
[110d795]371int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
[05aeee0e]372{
[c058a388]373 assert(hc);
[110d795]374 assert(cmd);
[c058a388]375
[548c123]376 xhci_trb_clean(&cmd->trb);
[110d795]377
[548c123]378 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
379 TRB_SET_EP(cmd->trb, ep_id);
380 TRB_SET_SUSP(cmd->trb, susp);
381 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[05aeee0e]382
[548c123]383 return enqueue_command(hc, cmd, 0, 0);
[c058a388]384}
[05aeee0e]385
[0cabd10]386int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
387 uintptr_t dequeue_ptr, uint16_t stream_id,
388 uint32_t ep_id)
389{
390 assert(hc);
391 assert(cmd);
392
[548c123]393 xhci_trb_clean(&cmd->trb);
[0cabd10]394
[548c123]395 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
396 TRB_SET_EP(cmd->trb, ep_id);
397 TRB_SET_STREAM(cmd->trb, stream_id);
398 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
399 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
[0cabd10]400
401 /**
402 * TODO: Set DCS (see section 4.6.10).
403 */
404
[548c123]405 return enqueue_command(hc, cmd, 0, 0);
[0cabd10]406}
407
[110d795]408int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
[c058a388]409{
410 assert(hc);
[110d795]411 assert(cmd);
[c058a388]412
[548c123]413 xhci_trb_clean(&cmd->trb);
[c058a388]414
[548c123]415 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
416 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
[c9bec1c]417
[548c123]418 return enqueue_command(hc, cmd, 0, 0);
[05aeee0e]419}
420
[60af4cdb]421int xhci_get_port_bandwidth_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
422 xhci_port_bandwidth_ctx_t *ctx, uint8_t device_speed)
423{
424 assert(hc);
425 assert(cmd);
426
427 xhci_trb_clean(&cmd->trb);
428
429 uint64_t phys_addr = (uint64_t) addr_to_phys(ctx);
430 TRB_SET_ICTX(cmd->trb, phys_addr);
431
432 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
433 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
434 TRB_SET_DEV_SPEED(cmd->trb, device_speed);
435
436 return enqueue_command(hc, cmd, 0, 0);
437}
438
[f9e7fe8]439int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
440{
[110d795]441 // TODO: Update dequeue ptrs.
[c058a388]442 assert(hc);
443 assert(trb);
444
[5ac5eb1]445 usb_log_debug("HC(%p) Command completed.", hc);
[f9e7fe8]446
[5ac5eb1]447 int code;
[2fa43d1]448 uint64_t phys;
[110d795]449 xhci_cmd_t *command;
[f711f06]450
[1b78a7c1]451 code = TRB_GET_CODE(*trb);
452 phys = TRB_GET_PHYS(*trb);;
[2fa43d1]453 command = get_command(hc, phys);
454 if (command == NULL) {
455 // TODO: STOP & ABORT may not have command structs in the list!
[04df063]456 usb_log_debug("No command struct for this completion event found.");
[2fa43d1]457
458 if (code != XHCI_TRBC_SUCCESS)
459 report_error(code);
460
461 return EOK;
462 }
[110d795]463
464 command->status = code;
[1b78a7c1]465 command->slot_id = TRB_GET_SLOT(*trb);
[110d795]466
[548c123]467 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
468 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
[665bf3c]469 if (code != XHCI_TRBC_SUCCESS) {
[4fa5342]470 report_error(code);
[548c123]471 xhci_dump_trb(&command->trb);
[665bf3c]472 }
473 }
[c362127]474
[548c123]475 switch (TRB_TYPE(command->trb)) {
[c362127]476 case XHCI_TRB_TYPE_NO_OP_CMD:
[9f5b613]477 assert(code == XHCI_TRBC_TRB_ERROR);
[110d795]478 break;
[c362127]479 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
[110d795]480 break;
[5ac5eb1]481 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
[110d795]482 break;
[8db42f7]483 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
[110d795]484 break;
[665bf3c]485 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
[110d795]486 break;
[c9ce62ae]487 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
[110d795]488 break;
[05aeee0e]489 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
[110d795]490 break;
[05aeee0e]491 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
492 // Note: If the endpoint was in the middle of a transfer, then the xHC
493 // will add a Transfer TRB before the Event TRB, research that and
494 // handle it appropriately!
[110d795]495 break;
[c058a388]496 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
[110d795]497 break;
[c362127]498 default:
[548c123]499 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
[110d795]500
501 command->completed = true;
[665bf3c]502 return ENAK;
[f711f06]503 }
[110d795]504
[4688350b]505 fibril_mutex_lock(&command->completed_mtx);
[110d795]506 command->completed = true;
[4688350b]507 fibril_condvar_broadcast(&command->completed_cv);
508 fibril_mutex_unlock(&command->completed_mtx);
509
[110d795]510 return EOK;
[f9e7fe8]511}
[c9c0e41]512
513
514/**
515 * @}
516 */
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